From 3a1d7ce2fb4fd4aca8b6876ef3aa060027e7f0e6 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Wed, 14 May 2025 10:10:17 +0100
Subject: [PATCH] Update TSMC28nm SRAM tie offs
---
sram/TSMC28nm/verilog/sl_sram.v | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/sram/TSMC28nm/verilog/sl_sram.v b/sram/TSMC28nm/verilog/sl_sram.v
index 192e61b..738ad8f 100644
--- a/sram/TSMC28nm/verilog/sl_sram.v
+++ b/sram/TSMC28nm/verilog/sl_sram.v
@@ -33,7 +33,7 @@ module sl_sram #(
);
// fixed pre-compiled 16K instance supported
-localparam TIE_EMA = 3'b010;
+localparam TIE_EMA = 3'b011;
localparam TIE_EMAW = 2'b00;
wire [AW-3:0] ADDR12 = ADDR;
wire [31:0] WDATA32 = WDATA;
@@ -64,7 +64,7 @@ generate
.RET1N (TIE_RET1N),
.EMAS (1'b0),
.STOV (1'b0),
- .WABL (1'b1),
+ .WABL (1'b0),
.WABLM (2'b00)
);
@@ -88,7 +88,7 @@ generate
.RET1N (TIE_RET1N),
.EMAS (1'b0),
.STOV (1'b0),
- .WABL (1'b1),
+ .WABL (1'b0),
.WABLM (2'b00)
);
end
--
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