Setup simulation infrastucture

.gitignore

+simulate/
+
+verif/cocotb/*.ini
+verif/cocotb/*.xml
+verif/cocotb/transcript
+verif/cocotb/sim_build
+verif/cocotb/__pycache__

.gitmodules

+[submodule "soctools_flow"]
+	path = soctools_flow
+	url = https://git.soton.ac.uk/soclabs/soctools_flow.git

flist/Top/ahb_QSPI.flist

+
+
+$(SOCLABS_AHB_QSPI_DIR)/logical/top_ahb_qspi/logical/top_ahb_qspi.v
\ No newline at end of file

flows/makefile.simulate

+#-----------------------------------------------------------------------------
+# AHB QSPI Simulation Makefile 
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+# ------- Cocotb Variables -----------
+# Convert Simulator Name for Cocotb
+COCOTB_SIMULATOR ?= questa
+
+ifeq ($(SIMULATOR),mti)
+	COCOTB_SIMULATOR := questa
+else ifeq ($(SIMULATOR),xm)
+	COCOTB_SIMULATOR := xcelium
+else ifeq ($(SIMULATOR),vcs)
+	COCOTB_SIMULATOR := vcs
+endif
+
+# Cocotb GUI Variable
+GUI ?= 0
+
+# Cocotb Test Location
+COCOTB_TEST_DIR := $(SOCLABS_AHB_QSPI_DIR)/verif/cocotb
+
+
+# Cocotb Scratch Directory
+COCOTB_DIR := $(SIM_TOP_DIR)/cocotb
+COCOTB_SCRATCH_DIR := $(COCOTB_DIR)/scratch
+
+# Filelist for Cocotb 
+MAKEFILE_FILELIST     := $(COCOTB_DIR)/makefile.flist
+
+
+# Generate Make filelist from flists
+flist_makefile_nanosoc: 
+	@mkdir -p $(COCOTB_DIR)
+	@(cd $(COCOTB_DIR); \
+	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -m -f $(DESIGN_VC) -o $(MAKEFILE_FILELIST);)
+
+run_cocotb: flist_makefile_nanosoc
+	@mkdir -p $(SIM_DIR)
+	@cd $(SIM_DIR); $(MAKE) -C $(SOCLABS_AHB_QSPI_DIR)/verif/cocotb clean SIM_BUILD=$(COCOTB_SCRATCH_DIR)
+	@cd $(SIM_DIR); $(MAKE) -C $(SOCLABS_AHB_QSPI_DIR)/verif/cocotb sim SIM=$(COCOTB_SIMULATOR) GUI=$(GUI) SIM_BUILD=$(COCOTB_SCRATCH_DIR) TESTCASE=$(TESTCASE)
+
+sim_cocotb: GUI=1
+sim_cocotb: run_cocotb
+
+

makefile

+#-------------------------------------
+# - Commonly Overloaded Variables
+#-------------------------------------
+# Simulator type (mti/vcs/xm)
+SIMULATOR   = mti
+
+#-------------------------------------
+# - Directory Setups
+#-------------------------------------
+# Directory to put simulation files
+SIM_TOP_DIR ?= $(SOCLABS_AHB_QSPI_DIR)/simulate/sim
+SIM_DIR ?= $(SIM_TOP_DIR)
+
+
+ifeq ($(ASIC),yes)
+	DESIGN_VC ?= $(SOCLABS_AHB_QSPI_DIR)/flist/Top/ahb_QSPI_ASIC.flist
+else
+	DESIGN_VC ?= $(SOCLABS_AHB_QSPI_DIR)/flist/Top/ahb_QSPI.flist
+endif
+
+#Include flows
+include ./flows/makefile.simulate

set_env.sh

+export SOCLABS_AHB_QSPI_DIR=$(pwd)
+export SOCLABS_SOCTOOLS_FLOW_DIR=$SOCLABS_AHB_QSPI_DIR/soctools_flow
\ No newline at end of file

soctools_flow @ 3e339941

+Subproject commit 3e339941d8b4536f4bd096fc4191a4e36e38978a

verif/cocotb/ahb_qspi_cocotb.v

@@ -23,6 +23,7 @@ module ahb_qspi_cocotb(
 top_ahb_qspi u_top_ahb_qspi(
     .HCLK(HCLK),
     .HRESETn(HRESETn),
+
     .HADDR(cocotb_HADDR),
     .HTRANS(cocotb_HTRANS),
     .HWRITE(cocotb_HWRITE),
@@ -35,12 +36,15 @@ top_ahb_qspi u_top_ahb_qspi(
     .HREADY(cocotb_HREADY),
     .HREADYOUT(cocotb_HREADYOUT),
     .HRESP(cocotb_HRESP),
+
     .QSPI_SCLK(),
     .QSPI_nCS(),
     .QSPI_IO_o(),
     .QSPI_IO_i(),
     .QSPI_IO_e()
-)
+);
+
+
 
 
 endmodule 
\ No newline at end of file

verif/cocotb/makefile

@@ -53,7 +53,7 @@ else ifeq ($(SIM), verilator)
 else ifeq ($(SIM), questa)
 	COMPILE_ARGS += +acc
 endif
-#include $(SOCLABS_SRAM_CHIPLET_DIR)/simulate/sim/cocotb/makefile.flist
+include $(SOCLABS_AHB_QSPI_DIR)/simulate/sim/cocotb/makefile.flist
 include $(shell cocotb-config --makefiles)/Makefile.sim
 
 iverilog_dump.v: