Initial

logical/top_ahb_qspi/logical/top_ahb_qspi.v

+
+
+module top_ahb_qspi #(
+    parameter ADDR_W = 16,
+    parameter DATA_W = 32
+    )(
+    input  wire                 HCLK,
+    input  wire                 HRESETn,
+
+    // AHB Signals
+    input  wire [ADDR_W-1:0]    HADDR,
+    input  wire [1:0]           HTRANS,
+    input  wire                 HWRITE,
+    input  wire [2:0]           HSIZE,
+    input  wire [2:0]           HBURST,
+    input  wire [3:0]           HPROT,
+    input  wire [DATA_W-1:0]    HWDATA,
+    input  wire                 HSELx,
+    output wire [DATA_W-1:0]    HRDATA,
+    input  wire                 HREADY,
+    output wire                 HREADYOUT,
+    output wire                 HRESP,
+
+    // QSPI Signals
+    output wire                 QSPI_SCLK,
+    output wire                 QSPI_nCS,
+    output wire [3:0]           QSPI_IO_o,
+    input  wire [3:0]           QSPI_IO_i,
+    output wire [3:0]           QSPI_IO_e
+);
+
+
+endmodule
\ No newline at end of file

verif/cocotb/ahb_qspi_cocotb.v

+`timescale 1ns/1ps 
+
+module ahb_qspi_cocotb(
+    input  wire                 HCLK,
+    input  wire                 HRESETn,
+
+    // AHB Signals
+    input  wire [32-1:0]    cocotb_HADDR,
+    input  wire [1:0]       cocotb_HTRANS,
+    input  wire             cocotb_HWRITE,
+    input  wire [2:0]       cocotb_HSIZE,
+    input  wire [2:0]       cocotb_HBURST,
+    input  wire [3:0]       cocotb_HPROT,
+    input  wire [32-1:0]    cocotb_HWDATA,
+    input  wire             cocotb_HSELx,
+    output wire [32-1:0]    cocotb_HRDATA,
+    input  wire             cocotb_HREADY,
+    output wire             cocotb_HREADYOUT,
+    output wire             cocotb_HRESP
+);
+
+
+top_ahb_qspi u_top_ahb_qspi(
+    .HCLK(HCLK),
+    .HRESETn(HRESETn),
+    .HADDR(cocotb_HADDR),
+    .HTRANS(cocotb_HTRANS),
+    .HWRITE(cocotb_HWRITE),
+    .HSIZE(cocotb_HSIZE),
+    .HBURST(cocotb_HBURST),
+    .HPROT(cocotb_HPROT),
+    .HWDATA(cocotb_HWDATA),
+    .HSELx(cocotb_HSELx),
+    .HRDATA(cocotb_HRDATA),
+    .HREADY(cocotb_HREADY),
+    .HREADYOUT(cocotb_HREADYOUT),
+    .HRESP(cocotb_HRESP),
+    .QSPI_SCLK(),
+    .QSPI_nCS(),
+    .QSPI_IO_o(),
+    .QSPI_IO_i(),
+    .QSPI_IO_e()
+)
+
+
+endmodule 
\ No newline at end of file

verif/cocotb/ahb_qspi_tests.py

+import itertools
+import logging
+import os
+from numpy import random
+import numpy as np
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer, ClockCycles
+from cocotb.regression import TestFactory
+
+from cocotbext.ahb import AHBLiteMaster, AHBBus
+
+class TB:
+    def __init__(self,dut):
+        self.dut = dut
+        
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.HCLK, 10, units="ns").start())
+        self.ahb_master = AHBLiteMaster(AHBBus.from_prefix(dut,"cocotb"), dut.HCLK, dut.HRESETn)
+    async def cycle_reset(self):
+        self.dut.HRESETn.setimmediatevalue(0)
+        await ClockCycles(self.dut.HCLK,20)
+        self.dut.HRESETn.setimmediatevalue(1)
+        await ClockCycles(self.dut.HCLK,10)
+            
+@cocotb.test()
+async def AHB_QSPI_1(dut):
+    tb = TB(dut)
+    await tb.cycle_reset()
+    
+    await tb.ahb_master.write(0x00,0x15)
\ No newline at end of file

verif/cocotb/makefile

+# Copyright (c) 2020 Alex Forencich
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= questa
+WAVES ?= 0
+GUI ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ns
+
+DUT      = ahb_qspi_cocotb
+TOPLEVEL = ahb_qspi_cocotb
+MODULE   = ahb_qspi_tests
+
+VERILOG_SOURCES += ./ahb_qspi_cocotb.v
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		VERILOG_SOURCES += iverilog_dump.v
+		COMPILE_ARGS += -s iverilog_dump
+	endif
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+	endif
+else ifeq ($(SIM), questa)
+	COMPILE_ARGS += +acc
+endif
+#include $(SOCLABS_SRAM_CHIPLET_DIR)/simulate/sim/cocotb/makefile.flist
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+iverilog_dump.v:
+	echo 'module iverilog_dump();' > $@
+	echo 'initial begin' >> $@
+	echo '    $$dumpfile("$(TOPLEVEL).fst");' >> $@
+	echo '    $$dumpvars(0, $(TOPLEVEL));' >> $@
+	echo 'end' >> $@
+	echo 'endmodule' >> $@
+
+clean::
+	@rm -rf iverilog_dump.v
+	@rm -rf dump.fst $(TOPLEVEL).fst

verif/cocotb/results.xml

+<testsuites name="results">
+  <testsuite name="all" package="all">
+    <property name="random_seed" value="1726223252" />
+    <testcase classname="ahb_qspi_tests" file="/home/dwn1c21/SoC-Labs/ahb_qspi/verif/cocotb/ahb_qspi_tests.py" lineno="29" name="AHB_QSPI_1" ratio_time="57536.30253728772" sim_time_ns="1290.001" time="0.022420644760131836">
+      <failure message="Test failed with RANDOM_SEED=1726223252" />
+    </testcase>
+  </testsuite>
+</testsuites>

verif/cocotb/sim_build/runsim.do

+# Autogenerated file
+onerror {
+	quit -f -code 1
+}
+vmap -c
+if [file exists sim_build/work] {vdel -lib sim_build/work -all}
+vlib sim_build/work
+vmap work sim_build/work
+vlog -work work +define+COCOTB_SIM -sv -timescale 1ns/1ns -mfcu +acc +acc  ./ahb_qspi_cocotb.v
+vsim  -onfinish exit -pli /usr/local/lib64/python3.6/site-packages/cocotb/libs/libcocotbvpi_modelsim.so   sim_build/work.ahb_qspi_cocotb
+onbreak resume
+run -all
+quit