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Commit e0680b96 authored by David Mapstone's avatar David Mapstone
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Updated Sourceme behaviour and added script to read in system stimulus from... 

Updated Sourceme behaviour and added script to read in system stimulus from accelerator and generate addressed 32bit writes
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flow/stimgen.py 0 → 100644
+ 94
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View file @ e0680b96
import csv, os
class InputBlockStruct:
def __init__(self):
self.word_list = []
def word_append(self, word):
self.word_list.append(word)
class InputPacketStruct:
def __init__(self):
self.block_list = []
def block_append(self, block):
self.block_list.append(block)
class WordStruct:
def __init__(self, data = 0x0, addr = 0x0, packet_num = 0, block_num = 0, trans = "W"):
self.data = data
self.addr = addr
self.trans = trans
self.packet_num = packet_num
self.block_num = block_num
def stimulus_generation(in_file, start_address, size):
# Calculate End Address
end_address = start_address + size - 0x4
# print(f"End Address is {hex(end_address)}")
# Open File
with open(in_file, "r") as stim:
csvreader = csv.reader(stim, delimiter=",")
stim_list = list(csvreader)
# Initialise Packet List
packet_list = []
# Initialise Temporary Structures
temppacketstruct = InputPacketStruct()
tempblockstruct = InputBlockStruct()
# Read Data into Structs
for i in stim_list:
tempblockstruct.word_append(int(i[0],16))
# If Last Word in Block, Append to Packet and Reset Temporary block structure
if (int(i[1])):
temppacketstruct.block_append(tempblockstruct)
tempblockstruct = InputBlockStruct()
# If Last Block in Packet , Append Packet to Packet List and Reset Temp Packet
if (int(i[2])):
packet_list.append(temppacketstruct)
temppacketstruct = InputPacketStruct()
print(f"Number of Packets is: {len(packet_list)}")
# List of Ouptut Transactions
output_word_list = []
# Generate Address for Packet
for packet_num, packet in enumerate(packet_list):
# Calculate Number of Blocks in First Packet
num_blocks = len(packet.block_list)
# Each Block Can Contain 16 32-bit Words (512 bits) (0x4 * 16 = 0x40)
# - Work Out Required Size = (0x40 * NumBlocks)
# - Work Out Beginning Address = (end_address + 0x4) - Size
req_write_size = 0x40 * num_blocks
start_write_addr = start_address + size - req_write_size
print(f"Packet: {int(packet_num)} | Start Address: {hex(start_write_addr)}")
write_addr = start_write_addr
for block_num, block in enumerate(packet.block_list):
for word in block.word_list:
word_data = WordStruct(word, write_addr, packet_num, block_num)
output_word_list.append(word_data)
# Increment Address
write_addr += 0x4
# for word in output_word_list:
prev_block_num = 0
for word in output_word_list:
if (word.packet_num > 0):
break
if (word.block_num != prev_block_num):
print("New Block")
print(f"{hex(word.addr)} {hex(word.data)} {word.trans}")
prev_block_num = word.block_num
if __name__ == "__main__":
accelerator_address = 0x6001_0000
accelerator_size = 0x0000_8000
in_file = os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/system/" + "input_data_32bit_stim.csv"
stimulus_generation(in_file, accelerator_address, accelerator_size)
\ No newline at end of file
hdl/verif/cmdsk_ahb_ram_beh.v 0 → 100644
+ 209
− 0
View file @ e0680b96
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Simple AHB RAM behavioral model
//-----------------------------------------------------------------------------
module cmsdk_ahb_ram_beh #(
parameter AW = 16,// Address width
parameter filename = "",
parameter WS_N = 0, // First access wait state
parameter WS_S = 0) // Subsequent access wait state
(
input wire HCLK, // Clock
input wire HRESETn, // Reset
input wire HSEL, // Device select
input wire [AW-1:0] HADDR, // Address
input wire [1:0] HTRANS, // Transfer control
input wire [2:0] HSIZE, // Transfer size
input wire HWRITE, // Write control
input wire [31:0] HWDATA, // Write data
input wire HREADY, // Transfer phase done
output wire HREADYOUT, // Device ready
output wire [31:0] HRDATA, // Read data output
output wire HRESP); // Device response (always OKAY)
// Internal signals
reg [7:0] ram_data[0:((1<<AW)-1)]; // 64k byte of RAM data
wire read_valid; // Address phase read valid
wire write_valid; // Address phase write valid
reg read_enable; // Data phase read enable
reg write_enable; // Data phase write enable
reg [3:0] reg_byte_lane; // Data phase byte lane
reg [3:0] next_byte_lane; // Next state of reg_byte_lane
reg [7:0] rdata_out_0; // Read Data Output byte#0
reg [7:0] rdata_out_1; // Read Data Output byte#1
reg [7:0] rdata_out_2; // Read Data Output byte#2
reg [7:0] rdata_out_3; // Read Data Output byte#3
reg [AW-1:0] word_addr; // Word aligned address
wire [AW-1:0] nxt_word_addr; // Word aligned address
integer i; // Loop counter
// Wait state control
wire [31:0] nxt_waitstate_cnt;
reg [31:0] reg_waitstate_cnt;
wire sequential_access;
// Start of main code
// Initialize ROM
initial
begin
for (i=0;i<(1<<AW);i=i+1)
begin
ram_data[i] = 8'h00; //Initialize all data to 0
end
if (filename != "")
begin
$readmemh(filename, ram_data); // Then read in program code
end
end
// Generate read control (address phase)
assign read_valid = HSEL & HREADY & HTRANS[1] & (~HWRITE);
// Generate write control (address phase)
assign write_valid = HSEL & HREADY & HTRANS[1] & HWRITE;
// Read enable for each byte (address phase)
always @(read_valid or write_valid or HADDR or HSIZE)
begin
if (read_valid | write_valid)
begin
case (HSIZE)
0 : // Byte
begin
case (HADDR[1:0])
0: next_byte_lane = 4'b0001; // Byte 0
1: next_byte_lane = 4'b0010; // Byte 1
2: next_byte_lane = 4'b0100; // Byte 2
3: next_byte_lane = 4'b1000; // Byte 3
default:next_byte_lane = 4'b0000; // Address not valid
endcase
end
1 : // Halfword
begin
if (HADDR[1])
next_byte_lane = 4'b1100; // Upper halfword
else
next_byte_lane = 4'b0011; // Lower halfword
end
default : // Word
next_byte_lane = 4'b1111; // Whole word
endcase
end
else
next_byte_lane = 4'b0000; // Not reading
end
// Registering control signals to data phase
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
begin
reg_byte_lane <= 4'b0000;
read_enable <= 1'b0;
write_enable <= 1'b0;
word_addr <= {AW{1'b0}};
end
else if (HREADY)
begin
reg_byte_lane <= next_byte_lane;
read_enable <= read_valid;
write_enable <= write_valid;
word_addr <= nxt_word_addr;
end
end
assign nxt_word_addr = {HADDR[AW-1:2], 2'b00};
// Read operation
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[0]))
rdata_out_0 = ram_data[word_addr ];
else
rdata_out_0 = 8'h00;
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[1]))
rdata_out_1 = ram_data[word_addr+1];
else
rdata_out_1 = 8'h00;
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[2]))
rdata_out_2 = ram_data[word_addr+2];
else
rdata_out_2 = 8'h00;
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[3]))
rdata_out_3 = ram_data[word_addr+3];
else
rdata_out_3 = 8'h00;
// Registered write
always @(posedge HCLK)
begin
if (write_enable & reg_byte_lane[0])
begin
ram_data[word_addr ] = HWDATA[ 7: 0];
end
if (write_enable & reg_byte_lane[1])
begin
ram_data[word_addr+1] = HWDATA[15: 8];
end
if (write_enable & reg_byte_lane[2])
begin
ram_data[word_addr+2] = HWDATA[23:16];
end
if (write_enable & reg_byte_lane[3])
begin
ram_data[word_addr+3] = HWDATA[31:24];
end
end
// Wait state control
// Wait state generate treat access as sequential if
// HTRANS = 2'b11, or access address is in the same word,
// or if the access is in the next word
assign sequential_access = (HTRANS==2'b11) |
(HADDR[AW-1:2] == word_addr[AW-1:2]) |
(HADDR[AW-1:2] == (word_addr[AW-1:2]+1));
assign nxt_waitstate_cnt = (read_valid|write_valid) ?
((sequential_access) ? WS_S : WS_N) :
((reg_waitstate_cnt!=0) ? (reg_waitstate_cnt - 1) : 0);
// Register wait state counter
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
reg_waitstate_cnt <= 0;
else
reg_waitstate_cnt <= nxt_waitstate_cnt;
end
// Connect to top level
assign HREADYOUT = (reg_waitstate_cnt==0) ? 1'b1 : 1'b0;
assign HRESP = 1'b0; // Always response with OKAY
// Read data output
assign HRDATA = {rdata_out_3, rdata_out_2, rdata_out_1,rdata_out_0};
endmodule
hdl/verif/cmsdk_ahb_default_slave.v 0 → 100644
+ 141
− 0
View file @ e0680b96
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : AHB-Lite Default Slave
//-----------------------------------------------------------------------------
//
// Returns an error response when selected for a transfer
//
module cmsdk_ahb_default_slave (
// Inputs
input wire HCLK, // Clock
input wire HRESETn, // Reset
input wire HSEL, // Slave select
input wire [1:0] HTRANS, // Transfer type
input wire HREADY, // System ready
// Outputs
output wire HREADYOUT, // Slave ready
output wire HRESP); // Slave response
//
// Start of main code
//
// Internal signals
wire trans_req; // Transfer Request
reg [1:0] resp_state; // Current FSM state for two-cycle error response
wire [1:0] next_state; // Next FSM state
// Transfer address phase completes
assign trans_req = HSEL & HTRANS[1] & HREADY;
// Generate next state for the FSM.
// Bit 0 is connected to HREADYOUT and bit 1 is connected to HRESP,
// so the state encodings are:
// 01 - Idle
// 10 - 1st cycle of error response
// 11 - 2nd cycle of error response
assign next_state = { trans_req | (~resp_state[0]),
~trans_req };
// Registering FSM state
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn)
resp_state <= 2'b01; // ensure HREADYOUT is HIGH at reset
else
resp_state <= next_state;
// Connect to output
assign HREADYOUT = resp_state[0];
assign HRESP = resp_state[1];
`ifdef ARM_AHB_ASSERT_ON
// ------------------------------------------------------------
// Assertions
// ------------------------------------------------------------
`include "std_ovl_defines.h"
reg ovl_last_hreadyout;
reg ovl_last_hsel;
reg [1:0] ovl_last_htrans;
reg ovl_last_hready;
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
begin
ovl_last_hreadyout <= 1'b1;
ovl_last_hsel <= 1'b0;
ovl_last_htrans <= 2'b00;
ovl_last_hready <= 1'b1;
end
else
begin
ovl_last_hreadyout <= HREADYOUT;
ovl_last_hsel <= HSEL;
ovl_last_htrans <= HTRANS;
ovl_last_hready <= HREADY;
end
end
assert_implication
#(`OVL_ERROR,`OVL_ASSERT,
"If HREADYOUT is 0, HRESP must be high")
u_ovl_error_response_check_1
(.clk(HCLK), .reset_n(HRESETn),
.antecedent_expr(~HREADYOUT),
.consequent_expr(HRESP)
);
assert_implication
#(`OVL_ERROR,`OVL_ASSERT,
"If in last cycle HREADYOUT is 0, this cycle both HRESP and HREADYOUT")
u_ovl_error_response_check_2
(.clk(HCLK), .reset_n(HRESETn),
.antecedent_expr(~ovl_last_hreadyout),
.consequent_expr(HRESP & HREADYOUT)
);
assert_implication
#(`OVL_ERROR,`OVL_ASSERT,
"If device is not selected, or if transfer is idle/busy, response must be OKAY")
u_ovl_error_fault_check_1
(.clk(HCLK), .reset_n(HRESETn),
.antecedent_expr(~(ovl_last_hsel & ovl_last_htrans[1]) & ovl_last_hready),
.consequent_expr((~HRESP) & HREADYOUT)
);
assert_implication
#(`OVL_ERROR,`OVL_ASSERT,
"If device is selected, and if transfer is nseq/seq, response must be ERROR")
u_ovl_error_fault_check_2
(.clk(HCLK), .reset_n(HRESETn),
.antecedent_expr(ovl_last_hsel & ovl_last_htrans[1] & ovl_last_hready),
.consequent_expr(HRESP & (~HREADYOUT))
);
`endif
endmodule
hdl/verif/tb_wrapper_top.sv 0 → 100644
+ 291
− 0
View file @ e0680b96
//-----------------------------------------------------------------------------
// SoC Labs Basic Testbench for Top-level AHB Wrapper
// Modified from tb_frbm_example.v
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Abstract : Example for File Reader Bus Master
// Testbench for the example AHB Lite slave.
//=========================================================================--
`include "cmsdk_ahb_filereadcore.v"
`include "cmsdk_ahb_fileread_funnel.v"
`include "cmsdk_ahb_fileread_master32.v"
`include "cmsdk_ahb_default_slave.v"
`include "cmsdk_ahb_ram_beh.v"
`timescale 1ns/1ps
module tb_wrapper_top;
parameter CLK_PERIOD = 10;
parameter ADDRWIDTH = 12;
parameter InputFileName = "tp_wrapper_top.out";
parameter MessageTag = "FileReader:";
parameter StimArraySize = 5000;
//********************************************************************************
// Internal Wires
//********************************************************************************
// AHB Lite BUS SIGNALS
wire hready;
wire hresp;
wire [31:0] hrdata;
wire [1:0] htrans;
wire [2:0] hburst;
wire [3:0] hprot;
wire [2:0] hsize;
wire hwrite;
wire hmastlock;
wire [31:0] haddr;
wire [31:0] hwdata;
// AHB Multiplexor signals, currently 3 slaves : example AHB slave, SRAM and default slave
wire hsel0;
wire hreadyout0;
wire hresp0;
wire [31:0] hrdata0;
wire hsel1;
wire hreadyout1;
wire hresp1;
wire [31:0] hrdata1;
wire hsel2;
wire hreadyout2;
wire hresp2;
wire [31:0] hrdata2;
reg HCLK;
reg HRESETn;
//********************************************************************************
// Clock and reset generation
//********************************************************************************
initial
begin
HRESETn = 1'b0;
HCLK = 1'b0;
# (10*CLK_PERIOD);
HRESETn = 1'b1;
end
always
begin
HCLK = #(CLK_PERIOD/2) ~HCLK;
end
//********************************************************************************
// Address decoder, need to be changed for other configuration
//********************************************************************************
// 0x10000000 - 0x10000FFF : HSEL #0 - Hash Accelerator
// 0x11000000 - 0x11000FFF : HSEL #1 - SRAM
// Other addresses : HSEL #2 - Default slave
assign hsel0 = (haddr[31:12] == 20'h10000)? 1'b1:1'b0;
assign hsel1 = (haddr[31:12] == 20'h11000)? 1'b1:1'b0;
assign hsel2 = (hsel0|hsel1)? 1'b0:1'b1;
//********************************************************************************
// File read bus master:
// generate AHB Master signal by reading a file which store the AHB Operations
//********************************************************************************
cmsdk_ahb_fileread_master32
#(.InputFileName(InputFileName), .MessageTag(MessageTag),.StimArraySize(StimArraySize))
u_ahb_fileread_master32(
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (hready),
.HRESP ({hresp}), //AHB Lite response to AHB response
.HRDATA (hrdata),
.EXRESP (1'b0), // Exclusive response (tie low if not used)
.HTRANS (htrans),
.HBURST (hburst),
.HPROT (hprot),
.EXREQ (), // Exclusive access request (not used)
.MEMATTR (), // Memory attribute (not used)
.HSIZE (hsize),
.HWRITE (hwrite),
.HMASTLOCK (hmastlock),
.HADDR (haddr),
.HWDATA (hwdata),
.LINENUM ()
);
//********************************************************************************
// Slave multiplexer module:
// multiplex the slave signals to master, three ports are enabled
//********************************************************************************
cmsdk_ahb_slave_mux #(
.PORT0_ENABLE(1),
.PORT1_ENABLE(1),
.PORT2_ENABLE(1),
.PORT3_ENABLE(0),
.PORT4_ENABLE(0),
.PORT5_ENABLE(0),
.PORT6_ENABLE(0),
.PORT7_ENABLE(0),
.PORT8_ENABLE(0),
.PORT9_ENABLE(0)
)
u_ahb_slave_mux (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (hready),
.HSEL0 (hsel0), // Input Port 0
.HREADYOUT0 (hreadyout0),
.HRESP0 (hresp0),
.HRDATA0 (hrdata0),
.HSEL1 (hsel1), // Input Port 1
.HREADYOUT1 (hreadyout1),
.HRESP1 (hresp1),
.HRDATA1 (hrdata1),
.HSEL2 (hsel2), // Input Port 2
.HREADYOUT2 (hreadyout2),
.HRESP2 (hresp2),
.HRDATA2 (hrdata2),
.HSEL3 (1'b0), // Input Port 3
.HREADYOUT3 (),
.HRESP3 (),
.HRDATA3 (),
.HSEL4 (1'b0), // Input Port 4
.HREADYOUT4 (),
.HRESP4 (),
.HRDATA4 (),
.HSEL5 (1'b0), // Input Port 5
.HREADYOUT5 (),
.HRESP5 (),
.HRDATA5 (),
.HSEL6 (1'b0), // Input Port 6
.HREADYOUT6 (),
.HRESP6 (),
.HRDATA6 (),
.HSEL7 (1'b0), // Input Port 7
.HREADYOUT7 (),
.HRESP7 (),
.HRDATA7 (),
.HSEL8 (1'b0), // Input Port 8
.HREADYOUT8 (),
.HRESP8 (),
.HRDATA8 (),
.HSEL9 (1'b0), // Input Port 9
.HREADYOUT9 (),
.HRESP9 (),
.HRDATA9 (),
.HREADYOUT (hready), // Outputs
.HRESP (hresp),
.HRDATA (hrdata)
);
//********************************************************************************
// Slave module 1: example AHB slave module
//********************************************************************************
cmsdk_ahb_eg_slave #(.ADDRWIDTH(ADDRWIDTH))
u_ahb_eg_slave(
.HCLK (HCLK),
.HRESETn (HRESETn),
// Input slave port: 32 bit data bus interface
.HSELS (hsel0),
.HADDRS (haddr[ADDRWIDTH-1:0]),
.HTRANSS (htrans),
.HSIZES (hsize),
.HWRITES (hwrite),
.HREADYS (hready),
.HWDATAS (hwdata),
.ECOREVNUM (4'h0),
.HREADYOUTS (hreadyout0),
.HRESPS (hresp0),
.HRDATAS (hrdata0)
);
//********************************************************************************
// Slave module 2: Behaviour AHB SRAM slave module
//********************************************************************************
// Behavioral SRAM model
cmsdk_ahb_ram_beh
#(.AW(20),
.filename(""),
.WS_N(5), // First access wait state
.WS_S(5) // Subsequent access wait state
)
u_ahb_ram_beh (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (hsel1), // AHB inputs
.HADDR (haddr[19:0]),
.HTRANS (htrans),
.HSIZE (hsize),
.HWRITE (hwrite),
.HWDATA (hwdata),
.HREADY (hready),
.HREADYOUT (hreadyout1), // Outputs
.HRDATA (hrdata1),
.HRESP (hresp1)
);
//********************************************************************************
// Slave module 3: AHB default slave module
//********************************************************************************
cmsdk_ahb_default_slave u_ahb_default_slave(
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (hsel2),
.HTRANS (htrans),
.HREADY (hready),
.HREADYOUT (hreadyout2),
.HRESP (hresp2)
);
assign hrdata2 = {32{1'b0}}; // Default slave don't have data
endmodule
\ No newline at end of file
sourceme
+ 17
− 6
View file @ e0680b96
...@@ -11,11 +11,22 @@ ...@@ -11,11 +11,22 @@
#!/usr/bin/env bash #!/usr/bin/env bash
# Set environment Variables for Repository if [ -z "$WRAP_ACC_DIR" ]; then
export WRAP_ACC_DIR="$( cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )" # Set environment Variables for Repository
export WRAP_ACC_DIR="$( cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )"
# Add flow directory to Path # Add flow directory to Path
export PATH=$PATH:$WRAP_ACC_DIR/flow export PATH=$PATH:$WRAP_ACC_DIR/flow
# Set Default Simulator # Set Default Simulator
export SIMULATOR="ivlog" export SIMULATOR="ivlog"
\ No newline at end of file
# Source Top-level sourceme
for d in $WRAP_ACC_DIR/../* ; do
if [ -d "$d" ]; then
if test -f "$d/sourceme"; then
source $d/sourceme
fi
fi
done
fi
\ No newline at end of file
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