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Added Initial Wrapper Files and Arm Example VIP

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# Sample GitLab Project # SoC Labs Accelerator Wrapper
This sample project shows how a project in GitLab looks for demonstration purposes. It contains issues, merge requests and Markdown files in many branches, This sample project shows how a project in GitLab looks for demonstration purposes. It contains issues, merge requests and Markdown files in many branches,
named and filled with lorem ipsum. named and filled with lorem ipsum.
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module wrapper_ahb_deconstruct #(
parameter PACKETWIDTH=512,
parameter ADDRWIDTH=11
)(
input logic hclk, // clock
input logic hresetn, // reset
//Register interface
input logic [ADDRWIDTH-1:0] addr,
input logic read_en,
input logic write_en,
input logic [3:0] byte_strobe,
input logic [31:0] wdata,
output logic [31:0] rdata,
output logic wready,
output logic rready,
// Valid/Ready interface
output logic [PACKETWIDTH-1:0] data_out,
output logic data_out_last,
output logic data_out_valid,
input logic data_out_ready
);
// 4KiB of Address Space for Accelerator (11:0)
// Capture Address to be used for comparision to test for address jumping
logic [ADDRWIDTH-1:0] last_wr_addr;
// Create Construction Buffer
logic [PACKETWIDTH-1:0] const_buffer;
logic const_buffer_last;
logic [ADDRWIDTH-1:0] addr_top_bit;
assign addr_top_bit = (addr[5:2] * 32) - 1;
// Dump data on one of two conditions
// - An address ends [5:0] in 0x3C i.e. [5:2] == 0xF
// - Address Moved to different 512 bit word
// Write Condition
always_ff @(posedge hclk or negedge hresetn) begin
if (~hresetn) begin
// Reset Construction Buffer
const_buffer <= {PACKETWIDTH{1'b0}};
end else begin
if (write_en) begin
// If not (awaiting handshake AND address generates new data payload)
if (!((data_out_valid && !data_out_ready) && (addr[5:2] == 4'hF))) begin
// Buffer Address for future Comparison
last_wr_addr <= addr;
// If 512 Word Address Changed, Clear Buffer
if (last_wr_addr[ADDRWIDTH-1:6] != addr [ADDRWIDTH-1:6]) const_buffer <= {PACKETWIDTH{1'b0}};
// Write Word into Construction Buffer
const_buffer[addr_top_bit -: 32] <= wdata;
// If last 32 bit word of 512 bit buffer
if (addr[5:2] == 4'hF) begin
// Produce Data Output
data_out <= {wdata,const_buffer[479:0]}; // Top word won't be in const_buffer
// - until next cycle to splice it in to out data combinatorially
// Calculate Last Flag
data_out_last <= (addr[ADDRWIDTH-1:6] == 5'h1F) ? 1'b1 : 1'b0;
// Take Valid High
data_out_valid <= 1'b1;
// Reset Construction Buffer
const_buffer <= 512'd0;
end
end else begin
// TODO: Implement Error Propogation/Waitstates
end
end
end
end
// Read Condition
always_comb begin
if (read_en) begin
// Read appropriate 32 bits from buffer - wrapping behaviour
rdata = const_buffer[addr_top_bit -: 32];
end else begin
rdata = 32'd0;
end
end
// Register Ready Control
always_comb begin
rready = 1'b1; // Always able to read - may return 0
wready = ~((data_out_valid && ~data_out_ready) && (addr[5:2] == 4'hF));
end
endmodule
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//-----------------------------------------------------------------------------
// SoC Labs AHB Wrapper Interface
// - Adapted from ARM AHB-lite example slave interface module.
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : AHB-lite example slave interface module. Transfer AHB-Lite BUS protocol to
// simple register read write protocol
//-----------------------------------------------------------------------------
module wrapper_ahb_interface #(
//parameter for address width
parameter ADDRWIDTH=12)
(
input logic hclk, // clock
input logic hresetn, // reset
// AHB connection to master
input logic hsels,
input logic [ADDRWIDTH-1:0] haddrs,
input logic [1:0] htranss,
input logic [2:0] hsizes,
input logic hwrites,
input logic hreadys,
input logic [31:0] hwdatas,
output logic hreadyouts,
output logic hresps,
output logic [31:0] hrdatas,
// Register interface - Accelerator Engine Input
output logic [ADDRWIDTH-2:0] input_addr,
output logic input_read_en,
output logic input_write_en,
output logic [3:0] input_byte_strobe,
output logic [31:0] input_wdata,
input logic [31:0] input_rdata,
input logic input_wready,
input logic input_rready,
// Register interface - Accelerator Engine Output
output logic [ADDRWIDTH-2:0] output_addr,
output logic output_read_en,
output logic output_write_en,
output logic [3:0] output_byte_strobe,
output logic [31:0] output_wdata,
input logic [31:0] output_rdata,
input output_wready,
input output_rready
);
// ----------------------------------------
// Internal wires declarations
logic input_trans_req = hreadys & hsels & htranss[1] & (~haddrs[ADDRWIDTH-1]);
logic output_trans_req = hreadys & hsels & htranss[1] & haddrs[ADDRWIDTH-1];
// use top bit of address to decifer which channel to communciate with
// transfer request issued only in SEQ and NONSEQ status and slave is
// selected and last transfer finish
// Engine Input Signal Generation
logic input_ahb_read_req = input_trans_req & (~hwrites);// AHB read request
logic input_ahb_write_req = input_trans_req & hwrites; // AHB write request
logic input_update_read_req; // To update the read enable register
logic input_update_write_req; // To update the write enable register
logic [ADDRWIDTH-2:0] input_addr_reg; // address signal, logicistered
logic input_read_en_reg; // read enable signal, registered
logic input_write_en_reg; // write enable signal, registered
logic [3:0] input_byte_strobe_reg; // registered output for byte strobe
// Engine Output Signal Generation
logic output_ahb_read_req = output_trans_req & (~hwrites);// AHB read request
logic output_ahb_write_req = output_trans_req & hwrites; // AHB write request
logic output_update_read_req; // To update the read enable register
logic output_update_write_req; // To update the write enable register
logic [ADDRWIDTH-2:0] output_addr_reg; // address signal, logicistered
logic output_read_en_reg; // read enable signal, registered
logic output_write_en_reg; // write enable signal, registered
logic [3:0] output_byte_strobe_reg; // registered output for byte strobe
logic [3:0] byte_strobe_nxt; // next state for byte_strobe_reg
// Channel Selection Register
logic channel_sel;
//-----------------------------------------------------------
// Module logic start
//----------------------------------------------------------
// Address signal registering, to make the address and data active at the same cycle
always_ff @(posedge hclk or negedge hresetn)
begin
if (~hresetn) begin
input_addr_reg <= {(ADDRWIDTH-1){1'b0}}; //default address 0 is selected
output_addr_reg <= {(ADDRWIDTH-1){1'b0}}; //default address 0 is selected
end else begin
if (input_trans_req) begin
input_addr_reg <= haddrs[ADDRWIDTH-2:0]; // register address for data phase
channel_sel <= haddrs[ADDRWIDTH-1];
end else if (output_trans_req) begin
output_addr_reg <= haddrs[ADDRWIDTH-2:0]; // register address for data phase
channel_sel <= haddrs[ADDRWIDTH-1];
end
end
end
// register read signal generation
assign input_update_read_req = input_ahb_read_req | (input_read_en_reg & hreadys); // Update read enable control if
// 1. When there is a valid read request
// 2. When there is an active read, update it at the end of transfer (HREADY=1)
assign output_update_read_req = output_ahb_read_req | (output_read_en_reg & hreadys); // Update read enable control if
// 1. When there is a valid read request
// 2. When there is an active read, update it at the end of transfer (HREADY=1)
always_ff @(posedge hclk or negedge hresetn)
begin
if (~hresetn) begin
input_read_en_reg <= 1'b0;
output_read_en_reg <= 1'b0;
end else begin
if (input_update_read_req) begin
input_read_en_reg <= input_ahb_read_req;
end else if (output_update_read_req) begin
output_read_en_reg <= output_ahb_read_req;
end
end
end
// register write signal generation
assign input_update_write_req = input_ahb_write_req |( input_write_en_reg & hreadys); // Update write enable control if
// 1. When there is a valid write request
// 2. When there is an active write, update it at the end of transfer (HREADY=1)
assign output_update_write_req = output_ahb_write_req |( output_write_en_reg & hreadys); // Update write enable control if
// 1. When there is a valid write request
// 2. When there is an active write, update it at the end of transfer (HREADY=1)
always_ff @(posedge hclk or negedge hresetn)
begin
if (~hresetn)
begin
input_write_en_reg <= 1'b0;
output_write_en_reg <= 1'b0;
end
else begin
if (input_update_write_req) begin
input_write_en_reg <= input_ahb_write_req;
end else if (output_update_write_req) begin
output_write_en_reg <= output_ahb_write_req;
end
end
end
// byte strobe signal
always @(hsizes or haddrs)
begin
if (hsizes == 3'b000) //byte
begin
case(haddrs[1:0])
2'b00: byte_strobe_nxt = 4'b0001;
2'b01: byte_strobe_nxt = 4'b0010;
2'b10: byte_strobe_nxt = 4'b0100;
2'b11: byte_strobe_nxt = 4'b1000;
default: byte_strobe_nxt = 4'bxxxx;
endcase
end
else if (hsizes == 3'b001) //half word
begin
if(haddrs[1]==1'b1)
byte_strobe_nxt = 4'b1100;
else
byte_strobe_nxt = 4'b0011;
end
else // default 32 bits, word
begin
byte_strobe_nxt = 4'b1111;
end
end
always_ff @(posedge hclk or negedge hresetn)
begin
if (~hresetn) begin
input_byte_strobe_reg <= {4{1'b0}};
output_byte_strobe_reg <= {4{1'b0}};
end else begin
if (input_update_read_req|input_update_write_req) begin
// Update byte strobe registers if
// 1. if there is a valid read/write transfer request
// 2. if there is an on going transfer
input_byte_strobe_reg <= byte_strobe_nxt;
end else if (output_update_read_req|output_update_write_req) begin
// Update byte strobe registers if
// 1. if there is a valid read/write transfer request
// 2. if there is an on going transfer
output_byte_strobe_reg <= byte_strobe_nxt;
end
end
end
//-----------------------------------------------------------
// Outputs
//-----------------------------------------------------------
// Input Channel Data Assignments
assign input_addr = input_addr_reg[ADDRWIDTH-2:0];
assign input_read_en = input_read_en_reg;
assign input_write_en = input_write_en_reg;
assign input_wdata = hwdatas;
assign input_byte_strobe = input_byte_strobe_reg;
// Output Channel Data Assignments
assign output_addr = output_addr_reg[ADDRWIDTH-2:0];
assign output_read_en = output_read_en_reg;
assign output_write_en = output_write_en_reg;
assign output_wdata = hwdatas;
assign output_byte_strobe = output_byte_strobe_reg;
assign hresps = 1'b0; // OKAY response from slave
// Always has okay response - won't generate error
// just wait until buffers able to be read from/written to
// Multiplex Read data back onto AHB
assign hrdatas = channel_sel ? output_rdata : input_rdata;
logic read_en_sel;
logic write_en_sel;
logic [2:0] hready_sel;
assign write_en_sel = input_write_en | output_write_en;
assign read_en_sel = input_read_en | output_read_en;
assign hready_sel = {channel_sel,write_en_sel,read_en_sel};
// Hreadyout Assignment
// - Need to assign combinatorially depending on channel connected to and whether channel is being written to/read from
// - 4-way MUX
always_comb begin
// Channel Selection
case(hready_sel)
// Input Channel Selects
3'b000: hreadyouts = 1'b1; // Defaultly Ready when no transaction taking place
3'b001: hreadyouts = input_rready; // Read Transaction Response
3'b010: hreadyouts = input_wready; // Write Transaction Response
3'b011: hreadyouts = 1'bx; // Both Read & Write Selected - Error State
// Output Channel Selects
3'b100: hreadyouts = 1'b1; // Defaultly Ready when no transaction taking place
3'b101: hreadyouts = output_rready; // Read Transaction Response
3'b110: hreadyouts = output_wready; // Write Transaction Response
3'b111: hreadyouts = 1'bx; // Both Read & Write Selected - Error State
default: hreadyouts = 1'bx;
endcase
end
//-----------------------------------------------------------
//Module logic end
//----------------------------------------------------------
endmodule
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//-----------------------------------------------------------------------------
// SoC Labs Basic Top-level AHB Wrapper
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : AHB-lite example slave, support 4 32-bit register read and write,
// each register can be accessed by byte, half word or word.
// The example slave always output ready and OKAY response to the master
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "ahb_packet_deconstruct.sv"
`include "fifo_vr.sv"
module wrapper_top #(
parameter ADDRWIDTH=12 // Peripheral Address Width
)(
input logic HCLK, // Clock
input logic HRESETn, // Reset
// AHB connection to Initiator
input logic HSELS,
input logic [ADDRWIDTH-1:0] HADDRS,
input logic [1:0] HTRANSS,
input logic [2:0] HSIZES,
input logic HWRITES,
input logic HREADYS,
input logic [31:0] HWDATAS,
output logic HREADYOUTS,
output logic HRESPS,
output logic [31:0] HRDATAS
);
// ----------------------------------------
// Internal wires declarations
// Register module interface signals
logic [ADDRWIDTH-1:0] in_buf_addr;
logic in_buf_read_en;
logic in_buf_write_en;
logic [3:0] in_buf_byte_strobe;
logic [31:0] in_buf_wdata;
logic [31:0] in_buf_rdata;
// Input Port Wire Declarations
logic [ADDRWIDTH-2:0] input_addr
logic input_read_en
logic input_write_en
logic input_byte_strobe
logic input_wdata
logic input_rdata
logic input_wready
logic input_rready
// Output Port Wire Declarations
logic output_addr
logic output_read_en
logic output_write_en
logic output_byte_strobe
logic output_wdata
logic output_rdata
logic output_wready
logic output_rready
//-----------------------------------------------------------
// Module logic start
//----------------------------------------------------------
// Interface block to convert AHB transfers to Register transfers to engine input/output channels
// engine Input/Output Channels
wrapper_ahb_interface
#(.ADDRWIDTH (ADDRWIDTH))
u_wrapper_ahb_interface (
.hclk (HCLK),
.hresetn (HRESETn),
// Input slave port: 32 bit data bus interface
.hsels (HSELS),
.haddrs (HADDRS),
.htranss (HTRANSS),
.hsizes (HSIZES),
.hwrites (HWRITES),
.hreadys (HREADYS),
.hwdatas (HWDATAS),
.hreadyouts (HREADYOUTS),
.hresps (HRESPS),
.hrdatas (HRDATAS),
// Register interface - Accelerator Engine Input
.input_addr (input_addr),
.input_read_en (input_read_en),
.input_write_en (input_write_en),
.input_byte_strobe (input_byte_strobe),
.input_wdata (input_wdata),
.input_rdata (input_rdata),
.input_wready (input_wready),
.input_rready (input_rready),
// Register interface - Accelerator Engine Output
.output_addr (output_addr),
.output_read_en (output_read_en),
.output_write_en (output_write_en),
.output_byte_strobe (output_byte_strobe),
.output_wdata (output_wdata),
.output_rdata (output_rdata),
.output_wready (output_wready),
.output_rready (output_rready)
);
wrapper_ahb_deconstruct
#(.ADDRWIDTH (ADDRWIDTH-1)) // Only half address map allocated to this device
u_wrapper_ahb_deconstruct (
.hclk (HCLK),
.hresetn (HRESETn),
// Register interface
.addr (addr),
.read_en (read_en),
.write_en (write_en),
.byte_strobe (byte_strobe),
.wdata (wdata),
.rdata (rdata),
.wready (wready),
.rready (rready),
// Valid/Ready Interface
.data_out (data_out),
.data_out_last (data_out_last),
.data_out_valid (data_out_valid),
.data_out_ready (data_out_ready)
);
wrapper_ahb_deconstruct
#(.ADDRWIDTH (ADDRWIDTH))
u_wrapper_ahb_deconstruct (
.hclk (HCLK),
.hresetn (HRESETn),
// Input slave port: 32 bit data bus interface
.hsels (HSELS),
.haddrs (HADDRS),
.htranss (HTRANSS),
.hsizes (HSIZES),
.hwrites (HWRITES),
.hreadys (HREADYS),
.hwdatas (HWDATAS),
.hreadyouts (HREADYOUTS),
.hresps (HRESPS),
.hrdatas (HRDATAS),
// Register interface
.addr (reg_addr),
.read_en (reg_read_en),
.write_en (reg_write_en),
.byte_strobe (reg_byte_strobe),
.wdata (reg_wdata),
.rdata (reg_rdata)
);
// Simple data register block with four 32-bit registers
cmsdk_ahb_eg_slave_reg
#(.ADDRWIDTH (ADDRWIDTH))
u_ahb_eg_slave_reg (
.hclk (HCLK),
.hresetn (HRESETn),
// Register interface
.addr (reg_addr),
.read_en (reg_read_en),
.write_en (reg_write_en),
.byte_strobe (reg_byte_strobe),
.wdata (reg_wdata),
.ecorevnum (ECOREVNUM),
.rdata (reg_rdata)
);
//-----------------------------------------------------------
//Module logic end
//----------------------------------------------------------
`ifdef ARM_AHB_ASSERT_ON
`include "std_ovl_defines.h"
// ------------------------------------------------------------
// Assertions
// ------------------------------------------------------------
logic ovl_trans_req = HREADYS & HSELS & HTRANSS[1];
// Check the reg_write_en signal generated
assert_next
#(`OVL_ERROR, 1,1,0,
`OVL_ASSERT,
"Error! register write signal was not generated! "
)
u_ovl_ahb_eg_slave_reg_write
(.clk ( HCLK ),
.reset_n (HRESETn),
.start_event ((ovl_trans_req & HWRITES)),
.test_expr (reg_write_en == 1'b1)
);
// Check the reg_read_en signal generated
assert_next
#(`OVL_ERROR, 1,1,0,
`OVL_ASSERT,
"Error! register read signal was not generated! "
)
u_ovl_ahb_eg_slave_reg_read
(.clk ( HCLK ),
.reset_n (HRESETn),
.start_event ((ovl_trans_req & (~HWRITES))),
.test_expr (reg_read_en == 1'b1)
);
// Check register read and write operation won't assert at the same cycle
assert_never
#(`OVL_ERROR,
`OVL_ASSERT,
"Error! register read and write active at the same cycle!")
u_ovl_ahb_eg_slave_rd_wr_illegal
(.clk(HCLK),
.reset_n(HRESETn),
.test_expr((reg_write_en & reg_read_en))
);
`endif
endmodule
// Data In data and Handshaking
logic [511:0] engine_data_in;
logic [5:0] engine_data_in_id;
logic engine_data_in_last;
logic enigne_data_in_valid;
logic enigne_data_in_ready;
// Data Out data and Handshaking
logic [255:0] engine_data_out;
logic [5:0] engine_data_out_id;
logic engine_data_out_last;
logic engine_data_out_valid;
logic engine_data_out_ready;
// Input Buffer
fifo_vr #(16, // Depth
512 // Data Width
) data_in_buffer (
.clk (clk),
.nrst (nrst),
.en (en),
.sync_rst (sync_rst),
.data_in (data_in),
.data_in_valid (data_in_valid),
.data_in_ready (data_in_ready),
.data_in_last (data_in_last),
.data_out (data_in_buffered),
.data_out_last (data_in_last_buffered),
.data_out_valid (data_in_valid_buffered),
.data_out_ready (data_in_ready_buffered)
);
// Input Word Combiner
endmodule
\ No newline at end of file
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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Convert 64-bit bus from ahb_fileread_core to 32-bit
//-----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Purpose : A data bus multiplexor, used to connect a 32 bit slave
// to a 64 bit bus.
// Supports transfers up to 32 bit in size.
// --========================================================================--
module cmsdk_ahb_fileread_funnel (
// Clock and Reset
input wire HCLK,
input wire HRESETn,
// Interface to AHB
input wire HADDR2S,
input wire [63:0] HWDATAS,
input wire HREADYS,
output wire [63:0] HRDATAS,
// Interface to slave
output reg [31:0] HWDATAM,
input wire [31:0] HRDATAM);
// -----------------------------------------------------------------------------
// Signal Declarations
// -----------------------------------------------------------------------------
reg haddr2s_reg; // Delayed version of address bit2
// =============================================================================
// Beginning of main verilog code
// =============================================================================
//------------------------------------------------------------------------------
// Generate Delayed version of HADDR2S
//------------------------------------------------------------------------------
always@(posedge HCLK or negedge HRESETn)
begin : p_haddr2s_reg
if (HRESETn == 1'b0)
haddr2s_reg <= 1'b0;
else
begin
if (HREADYS == 1'b1)
haddr2s_reg <= HADDR2S;
end
end // block: p_haddr2s_reg
// -----------------------------------------------------------------------------
// Write Data MUX
// -----------------------------------------------------------------------------
// Note: To support Big-Endian systems the polarity of the HWDATAM MUX should be
// reversed.
always@(haddr2s_reg or HWDATAS)
begin : p_write_mux
if (haddr2s_reg == 1'b0)
HWDATAM = HWDATAS[31:0];
else
HWDATAM = HWDATAS[63:32];
end // block: p_write_mux
// -----------------------------------------------------------------------------
// Read Data bus
// -----------------------------------------------------------------------------
assign HRDATAS = {HRDATAM,HRDATAM};
endmodule
// --================================= End ===================================--
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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : 32-bit AHB File Reader Bus Master
//-----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Purpose : This entity ties together the sub blocks that
// form the 32-bit File Reader Bus Master, namely an
// AHB-Lite File Reader Core and a bus funnel .
// --========================================================================--
// Note
// This top level file converts AHB Lite extension
// signals in ARM1136 to sideband signals used in
// Cortex-M3/M4
// --========================================================================--
module cmsdk_ahb_fileread_master32 #(
parameter InputFileName = "filestim.m2d", // stimulus data file name
parameter MessageTag = "FileReader:", // tag on each FileReader message
parameter StimArraySize = 5000) // stimulus data array size:
// should be large enough to hold
// entire stimulus data file
(
// system ports
input wire HCLK, // system clock
input wire HRESETn, // system reset
// AHB ports
input wire HREADY, // slave ready signal
input wire HRESP, // slave response bus
input wire [31:0] HRDATA, // data, slave to master
input wire EXRESP, // Exclusive response (tie low if not used)
output wire [1:0] HTRANS, // transfer type
output wire [2:0] HBURST, // burst type
output wire [3:0] HPROT, // transfer protection
output wire EXREQ, // Exclusive access request
output wire [1:0] MEMATTR, // Memory attribute
output wire [2:0] HSIZE, // transfer size
output wire HWRITE, // transfer direction
output wire HMASTLOCK, // transfer is locked
output wire [31:0] HADDR, // transfer address
output wire [31:0] HWDATA, // data, master to slave
output wire [31:0] LINENUM); // line number in stimulus file
// Internal AHB-Lite Bus Signals
wire [2:0] hresp_core; // slave response
wire [63:0] hrdata_core; // data from slave to master
wire [31:0] haddr_core; // transfer address
wire [63:0] hwdata_core; // data from master to slave
wire [5:0] hprot_core; // transfer protection
//------------------------------------------------------------------------------
// structural
//------------------------------------------------------------------------------
// Instance of AHB-Lite File Reader connected to internal AHB-Lite system
cmsdk_ahb_filereadcore
#(.input_filename(InputFileName),
.message_tag(MessageTag),
.stim_array_size(StimArraySize))
u_ahb_filereadcore (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (HREADY),
.HRESP (hresp_core),
.HRDATA (hrdata_core),
.HTRANS (HTRANS),
.HBURST (HBURST),
.HPROT (hprot_core),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HMASTLOCK (HMASTLOCK),
.HADDR (haddr_core),
.HWDATA (hwdata_core),
.HUNALIGN (),
.HBSTRB (),
.LINENUM (LINENUM)
);
// Instance of a Funnel to translate the 64-bit AHB-Lite data bus to 32-bit.
cmsdk_ahb_fileread_funnel u_ahb_fileread_funnel (
.HCLK (HCLK),
.HRESETn (HRESETn),
// 64-bit interface to AHB
.HREADYS (HREADY),
.HADDR2S (haddr_core[2]),
.HWDATAS (hwdata_core),
.HRDATAS (hrdata_core),
// 32-bit interface to slave
.HWDATAM (HWDATA),
.HRDATAM (HRDATA)
);
// Convert internal versions of port signals
assign HADDR = haddr_core; // Drive port with internal signal
assign HPROT = hprot_core[3:0];
assign EXREQ = hprot_core[5];
assign MEMATTR = {1'b0, hprot_core[4]};
assign hresp_core = {EXRESP, 1'b0,HRESP}; // Drive unused bit of hresp_core
endmodule
// --================================ End ==================================--
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#-----------------------------------------------------------------------------
# SoC Labs Environment Setup Script
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Mapstone (d.a.mapstone@soton.ac.uk)
#
# Copyright 2022, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
#!/usr/bin/env bash
# Set environment Variables for Repository
export WRAP_ACC_DIR="$( cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )"
# Add flow directory to Path
export PATH=$PATH:$WRAP_ACC_DIR/flow
# Set Default Simulator
export SIMULATOR="ivlog"
\ No newline at end of file
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