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Commit b481897a authored by David Mapstone's avatar David Mapstone
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Renamed example to VR Loopback

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hdl/src/wrapper_vr_loopback.sv 0 → 100644
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//-----------------------------------------------------------------------------
// SoC Labs Basic Wrapper Source
// - Valid-Ready Loopback example connecting packet constructor to deconstructor
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : AHB-lite example slave, support 4 32-bit register read and write,
// each register can be accessed by byte, half word or word.
// The example slave always output ready and OKAY response to the master
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "wrapper_packet_construct.sv"
`include "wrapper_packet_deconstruct.sv"
`include "wrapper_ahb_interface.sv"
module wrapper_vr_loopback #(
parameter ADDRWIDTH=12 // Peripheral Address Width
)(
input logic HCLK, // Clock
input logic HRESETn, // Reset
// AHB connection to Initiator
input logic HSELS,
input logic [ADDRWIDTH-1:0] HADDRS,
input logic [1:0] HTRANSS,
input logic [2:0] HSIZES,
input logic HWRITES,
input logic HREADYS,
input logic [31:0] HWDATAS,
output logic HREADYOUTS,
output logic HRESPS,
output logic [31:0] HRDATAS
);
// ----------------------------------------
// Internal wires declarations
// Register module interface signals
logic [ADDRWIDTH-1:0] in_buf_addr;
logic in_buf_read_en;
logic in_buf_write_en;
logic [3:0] in_buf_byte_strobe;
logic [31:0] in_buf_wdata;
logic [31:0] in_buf_rdata;
// Input Port Wire Declarations
logic [ADDRWIDTH-2:0] input_addr;
logic input_read_en;
logic input_write_en;
logic [3:0] input_byte_strobe;
logic [31:0] input_wdata;
logic [31:0] input_rdata;
logic input_wready;
logic input_rready;
// Output Port Wire Declarations
logic [ADDRWIDTH-2:0] output_addr;
logic output_read_en;
logic output_write_en;
logic [3:0] output_byte_strobe;
logic [31:0] output_wdata;
logic [31:0] output_rdata;
logic output_wready;
logic output_rready;
// Internal Wiring
logic [511:0] packet_data_out;
logic packet_data_out_last;
logic packet_data_out_valid;
logic packet_data_out_ready;
// Internal Wiring
logic [511:0] packet_data_in;
logic packet_data_in_last;
logic packet_data_in_valid;
logic packet_data_in_ready;
// Test Wire Assignments
assign packet_data_in = packet_data_out;
assign packet_data_in_last = packet_data_out_last;
assign packet_data_in_valid = packet_data_out_valid;
assign packet_data_out_ready = packet_data_in_ready;
//-----------------------------------------------------------
// Module logic start
//----------------------------------------------------------
// Interface block to convert AHB transfers to Register transfers to engine input/output channels
// engine Input/Output Channels
wrapper_ahb_interface #(
ADDRWIDTH
) u_wrapper_ahb_interface (
.hclk (HCLK),
.hresetn (HRESETn),
// Input slave port: 32 bit data bus interface
.hsels (HSELS),
.haddrs (HADDRS),
.htranss (HTRANSS),
.hsizes (HSIZES),
.hwrites (HWRITES),
.hreadys (HREADYS),
.hwdatas (HWDATAS),
.hreadyouts (HREADYOUTS),
.hresps (HRESPS),
.hrdatas (HRDATAS),
// Register interface - Accelerator Engine Input
.input_addr (input_addr),
.input_read_en (input_read_en),
.input_write_en (input_write_en),
.input_byte_strobe (input_byte_strobe),
.input_wdata (input_wdata),
.input_rdata (input_rdata),
.input_wready (input_wready),
.input_rready (input_rready),
// Register interface - Accelerator Engine Output
.output_addr (output_addr),
.output_read_en (output_read_en),
.output_write_en (output_write_en),
.output_byte_strobe (output_byte_strobe),
.output_wdata (output_wdata),
.output_rdata (output_rdata),
.output_wready (output_wready),
.output_rready (output_rready)
);
wrapper_packet_construct #(
(ADDRWIDTH - 1), // Only half address map allocated to this device
512 // Packet Width
) u_wrapper_packet_construct (
.hclk (HCLK),
.hresetn (HRESETn),
// Register interface
.addr (input_addr),
.read_en (input_read_en),
.write_en (input_write_en),
.byte_strobe (input_byte_strobe),
.wdata (input_wdata),
.rdata (input_rdata),
.wready (input_wready),
.rready (input_rready),
// Valid/Ready Interface
.data_out (packet_data_out),
.data_out_last (packet_data_out_last),
.data_out_valid (packet_data_out_valid),
.data_out_ready (packet_data_out_ready)
);
wrapper_packet_deconstruct #(
(ADDRWIDTH - 1), // Only half address map allocated to this device
512 // Ouptut Packet WIdth
) u_wrapper_packet_deconstruct (
.hclk (HCLK),
.hresetn (HRESETn),
// Register interface
.addr (output_addr),
.read_en (output_read_en),
.write_en (output_write_en),
.byte_strobe (output_byte_strobe),
.wdata (output_wdata),
.rdata (output_rdata),
.wready (output_wready),
.rready (output_rready),
// Valid/Ready Interface
.data_in (packet_data_in),
.data_in_last (packet_data_in_last),
.data_in_valid (packet_data_in_valid),
.data_in_ready (packet_data_in_ready)
);
//-----------------------------------------------------------
//Module logic end
//----------------------------------------------------------
//---------------------
//Test Logic
//---------------------
// assign data_out_ready = 1'b1;
// assign output_wready = 1'b1;
// assign output_rready = 1'b1;
// assign output_wready = 1'b1;
// assign output_rready = 1'b1;
`ifdef ARM_AHB_ASSERT_ON
`include "std_ovl_defines.h"
// ------------------------------------------------------------
// Assertions
// ------------------------------------------------------------
logic ovl_trans_req = HREADYS & HSELS & HTRANSS[1];
// Check the reg_write_en signal generated
assert_next
#(`OVL_ERROR, 1,1,0,
`OVL_ASSERT,
"Error! register write signal was not generated! "
)
u_ovl_ahb_eg_slave_reg_write
(.clk ( HCLK ),
.reset_n (HRESETn),
.start_event ((ovl_trans_req & HWRITES)),
.test_expr (reg_write_en == 1'b1)
);
// Check the reg_read_en signal generated
assert_next
#(`OVL_ERROR, 1,1,0,
`OVL_ASSERT,
"Error! register read signal was not generated! "
)
u_ovl_ahb_eg_slave_reg_read
(.clk ( HCLK ),
.reset_n (HRESETn),
.start_event ((ovl_trans_req & (~HWRITES))),
.test_expr (reg_read_en == 1'b1)
);
// Check register read and write operation won't assert at the same cycle
assert_never
#(`OVL_ERROR,
`OVL_ASSERT,
"Error! register read and write active at the same cycle!")
u_ovl_ahb_eg_slave_rd_wr_illegal
(.clk(HCLK),
.reset_n(HRESETn),
.test_expr((reg_write_en & reg_read_en))
);
`endif
endmodule
\ No newline at end of file
hdl/verif/tb_wrapper_vr_loopback.sv 0 → 100644
+ 260
− 0
View file @ b481897a
//-----------------------------------------------------------------------------
// SoC Labs Basic Testbench for Top-level AHB Wrapper
// Modified from tb_frbm_example.v
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Abstract : Example for File Reader Bus Master
// Testbench for the example AHB Lite slave.
//=========================================================================--
`include "cmsdk_ahb_filereadcore.v"
`include "cmsdk_ahb_fileread_funnel.v"
`include "cmsdk_ahb_fileread_master32.v"
`include "cmsdk_ahb_default_slave.v"
`include "cmsdk_ahb_slave_mux.v"
`include "wrapper_vr_loopback.sv"
`timescale 1ns/1ps
module tb_wrapper_vr_loopback;
parameter CLK_PERIOD = 10;
parameter ADDRWIDTH = 12;
// parameter InputFileName = "ahb_input_hash_stim.m2d";
parameter InputFileName = ("../stimulus/ahb_input_hash_stim.m2d");
parameter MessageTag = "FileReader:";
parameter StimArraySize = 10000;
//********************************************************************************
// Internal Wires
//********************************************************************************
// AHB Lite BUS SIGNALS
wire hready;
wire hresp;
wire [31:0] hrdata;
wire [1:0] htrans;
wire [2:0] hburst;
wire [3:0] hprot;
wire [2:0] hsize;
wire hwrite;
wire hmastlock;
wire [31:0] haddr;
wire [31:0] hwdata;
// Accelerator AHB Signals
wire hsel0;
wire hreadyout0;
wire hresp0;
wire [31:0] hrdata0;
// Default Slave AHB Signals
wire hsel1;
wire hreadyout1;
wire hresp1;
wire [31:0] hrdata1;
reg HCLK;
reg HRESETn;
//********************************************************************************
// Clock and reset generation
//********************************************************************************
initial
begin
$dumpfile("wrapper_vr_loopback.vcd");
$dumpvars(0, tb_wrapper_vr_loopback);
HRESETn = 1'b0;
HCLK = 1'b0;
# (10*CLK_PERIOD);
HRESETn = 1'b1;
end
always
begin
HCLK = #(CLK_PERIOD/2) ~HCLK;
end
//********************************************************************************
// Address decoder, need to be changed for other configuration
//********************************************************************************
// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator
// Other addresses : HSEL #1 - Default slave
assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0;
assign hsel1 = hsel0 ? 1'b0:1'b1;
//********************************************************************************
// File read bus master:
// generate AHB Master signal by reading a file which store the AHB Operations
//********************************************************************************
cmsdk_ahb_fileread_master32 #(InputFileName,
MessageTag,
StimArraySize
) u_ahb_fileread_master32 (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (hready),
.HRESP ({hresp}), //AHB Lite response to AHB response
.HRDATA (hrdata),
.EXRESP (1'b0), // Exclusive response (tie low if not used)
.HTRANS (htrans),
.HBURST (hburst),
.HPROT (hprot),
.EXREQ (), // Exclusive access request (not used)
.MEMATTR (), // Memory attribute (not used)
.HSIZE (hsize),
.HWRITE (hwrite),
.HMASTLOCK (hmastlock),
.HADDR (haddr),
.HWDATA (hwdata),
.LINENUM ()
);
//********************************************************************************
// Slave multiplexer module:
// multiplex the slave signals to master, three ports are enabled
//********************************************************************************
cmsdk_ahb_slave_mux #(
1, //PORT0_ENABLE
1, //PORT1_ENABLE
1, //PORT2_ENABLE
0, //PORT3_ENABLE
0, //PORT4_ENABLE
0, //PORT5_ENABLE
0, //PORT6_ENABLE
0, //PORT7_ENABLE
0, //PORT8_ENABLE
0 //PORT9_ENABLE
) u_ahb_slave_mux (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (hready),
.HSEL0 (hsel0), // Input Port 0
.HREADYOUT0 (hreadyout0),
.HRESP0 (hresp0),
.HRDATA0 (hrdata0),
.HSEL1 (hsel1), // Input Port 1
.HREADYOUT1 (hreadyout1),
.HRESP1 (hresp1),
.HRDATA1 (hrdata1),
.HSEL2 (1'b0), // Input Port 2
.HREADYOUT2 (),
.HRESP2 (),
.HRDATA2 (),
.HSEL3 (1'b0), // Input Port 3
.HREADYOUT3 (),
.HRESP3 (),
.HRDATA3 (),
.HSEL4 (1'b0), // Input Port 4
.HREADYOUT4 (),
.HRESP4 (),
.HRDATA4 (),
.HSEL5 (1'b0), // Input Port 5
.HREADYOUT5 (),
.HRESP5 (),
.HRDATA5 (),
.HSEL6 (1'b0), // Input Port 6
.HREADYOUT6 (),
.HRESP6 (),
.HRDATA6 (),
.HSEL7 (1'b0), // Input Port 7
.HREADYOUT7 (),
.HRESP7 (),
.HRDATA7 (),
.HSEL8 (1'b0), // Input Port 8
.HREADYOUT8 (),
.HRESP8 (),
.HRDATA8 (),
.HSEL9 (1'b0), // Input Port 9
.HREADYOUT9 (),
.HRESP9 (),
.HRDATA9 (),
.HREADYOUT (hready), // Outputs
.HRESP (hresp),
.HRDATA (hrdata)
);
//********************************************************************************
// Slave module 1: example AHB slave module
//********************************************************************************
wrapper_vr_loopback #(ADDRWIDTH
) accelerator (
.HCLK (HCLK),
.HRESETn (HRESETn),
// Input slave port: 32 bit data bus interface
.HSELS (hsel0),
.HADDRS (haddr[ADDRWIDTH-1:0]),
.HTRANSS (htrans),
.HSIZES (hsize),
.HWRITES (hwrite),
.HREADYS (hready),
.HWDATAS (hwdata),
.HREADYOUTS (hreadyout0),
.HRESPS (hresp0),
.HRDATAS (hrdata0)
);
//********************************************************************************
// Slave module 2: AHB default slave module
//********************************************************************************
cmsdk_ahb_default_slave u_ahb_default_slave(
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (hsel1),
.HTRANS (htrans),
.HREADY (hready),
.HREADYOUT (hreadyout1),
.HRESP (hresp1)
);
assign hrdata1 = {32{1'b0}}; // Default slave don't have data
endmodule
\ No newline at end of file
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