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Commit 51823191 authored by David Mapstone's avatar David Mapstone
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SOC1-143: Moved wrapper design files from wrapper repo to system top

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README.md
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# SoC Labs Accelerator Wrapper
Tests
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named and filled with lorem ipsum.
You can look around to get an idea how to structure your project and, when done, you can safely delete this project.
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This Repo Contains Accelerator Wrapper IP which should be used at the top-level repository to stitch your accelerator together with.
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//-----------------------------------------------------------------------------
// Accelerator Wrapper CMSDK Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for Accelerator CMSDK Wrapper Components
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= Accelerator Module search path =============
-y $(ACC_WRAPPER_DIR)/hdl/verif/
-y $(ACC_WRAPPER_DIR)/hdl/verif/cmsdk
+incdir+$(ACC_WRAPPER_DIR)/hdl/verif/
+incdir+$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/
$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_filereadcore.v
$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_fileread_funnel.v
$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_fileread_master32.v
$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_default_slave.v
$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_slave_mux.v
\ No newline at end of file
flist/accelerator_wrapper.flist → flist/wrapper_ip.flist
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......@@ -9,7 +9,7 @@
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for Accelerator Wrapper example
// Abstract : Verilog Command File for Accelerator Wrapper IP
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
......@@ -20,7 +20,6 @@
+incdir+$(ACC_WRAPPER_DIR)/hdl/src/
$(ACC_WRAPPER_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
$(ACC_WRAPPER_DIR)/hdl/src/wrapper_ahb_to_vr_interface.sv
$(ACC_WRAPPER_DIR)/hdl/src/wrapper_ahb_vr_interface.sv
$(ACC_WRAPPER_DIR)/hdl/src/wrapper_packet_construct.sv
$(ACC_WRAPPER_DIR)/hdl/src/wrapper_packet_deconstruct.sv
$(ACC_WRAPPER_DIR)/hdl/src/wrapper_sha256_hashing_stream.sv
\ No newline at end of file
hdl/.DS_Store
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hdl/src/wrapper_ahb_to_vr_interface.sv → hdl/src/wrapper_ahb_vr_interface.sv
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......@@ -35,7 +35,7 @@
// Abstract : AHB-lite example slave interface module. Transfer AHB-Lite BUS protocol to
// simple register read write protocol
//-----------------------------------------------------------------------------
module wrapper_ahb_to_vr_interface #(
module wrapper_ahb_vr_interface #(
//parameter for address width
parameter ADDRWIDTH=12)
(
......
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//-----------------------------------------------------------------------------
// SoC Labs Basic Accelerator Wrapper for Hashing Stream
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : AHB-lite example slave, support 4 32-bit register read and write,
// each register can be accessed by byte, half word or word.
// The example slave always output ready and OKAY response to the master
//-----------------------------------------------------------------------------
module wrapper_sha256_hashing_stream #(
parameter ADDRWIDTH=12
) (
input logic HCLK, // Clock
input logic HRESETn, // Reset
// AHB connection to Initiator
input logic HSELS,
input logic [ADDRWIDTH-1:0] HADDRS,
input logic [1:0] HTRANSS,
input logic [2:0] HSIZES,
input logic HWRITES,
input logic HREADYS,
input logic [31:0] HWDATAS,
output logic HREADYOUTS,
output logic HRESPS,
output logic [31:0] HRDATAS
);
// ----------------------------------------
// Internal wires declarations
// Register module interface signals
logic [ADDRWIDTH-1:0] in_buf_addr;
logic in_buf_read_en;
logic in_buf_write_en;
logic [3:0] in_buf_byte_strobe;
logic [31:0] in_buf_wdata;
logic [31:0] in_buf_rdata;
// Input Port Wire Declarations
logic [ADDRWIDTH-2:0] input_addr;
logic input_read_en;
logic input_write_en;
logic [3:0] input_byte_strobe;
logic [31:0] input_wdata;
logic [31:0] input_rdata;
logic input_wready;
logic input_rready;
// Output Port Wire Declarations
logic [ADDRWIDTH-2:0] output_addr;
logic output_read_en;
logic output_write_en;
logic [3:0] output_byte_strobe;
logic [31:0] output_wdata;
logic [31:0] output_rdata;
logic output_wready;
logic output_rready;
// Internal Wiring
// Input Packet Wires
logic [511:0] in_packet;
logic in_packet_last;
logic in_packet_valid;
logic in_packet_ready;
// Output Packet Wires
logic [255:0] out_packet;
logic out_packet_last;
logic out_packet_valid;
logic out_packet_ready;
// Configuration Tie Off
logic [63:0] cfg_size;
logic [1:0] cfg_scheme;
logic cfg_last;
logic cfg_valid;
logic cfg_ready;
assign cfg_size = 64'd512;
assign cfg_scheme = 2'd0;
assign cfg_last = 1'b1;
assign cfg_valid = 1'b1;
//-----------------------------------------------------------
// Module logic start
//----------------------------------------------------------
// Interface block to convert AHB transfers to Register transfers to engine input/output channels
// engine Input/Output Channels
wrapper_ahb_to_vr_interface #(
ADDRWIDTH
) u_wrapper_ahb_interface (
.hclk (HCLK),
.hresetn (HRESETn),
// Input slave port: 32 bit data bus interface
.hsels (HSELS),
.haddrs (HADDRS),
.htranss (HTRANSS),
.hsizes (HSIZES),
.hwrites (HWRITES),
.hreadys (HREADYS),
.hwdatas (HWDATAS),
.hreadyouts (HREADYOUTS),
.hresps (HRESPS),
.hrdatas (HRDATAS),
// Register interface - Accelerator Engine Input
.input_addr (input_addr),
.input_read_en (input_read_en),
.input_write_en (input_write_en),
.input_byte_strobe (input_byte_strobe),
.input_wdata (input_wdata),
.input_rdata (input_rdata),
.input_wready (input_wready),
.input_rready (input_rready),
// Register interface - Accelerator Engine Output
.output_addr (output_addr),
.output_read_en (output_read_en),
.output_write_en (output_write_en),
.output_byte_strobe (output_byte_strobe),
.output_wdata (output_wdata),
.output_rdata (output_rdata),
.output_wready (output_wready),
.output_rready (output_rready)
);
wrapper_packet_construct #(
(ADDRWIDTH - 1), // Only half address map allocated to this device
512 // Packet Width
) u_wrapper_packet_construct (
.hclk (HCLK),
.hresetn (HRESETn),
// Register interface
.addr (input_addr),
.read_en (input_read_en),
.write_en (input_write_en),
.byte_strobe (input_byte_strobe),
.wdata (input_wdata),
.rdata (input_rdata),
.wready (input_wready),
.rready (input_rready),
// Valid/Ready Interface
.packet_data (in_packet),
.packet_data_last (in_packet_last),
.packet_data_valid (in_packet_valid),
.packet_data_ready (in_packet_ready)
);
sha256_hashing_stream u_sha256_hashing_stream (
.clk (HCLK),
.nrst (HRESETn),
.en (1'b1),
.sync_rst (1'b0),
// Data in Channel
.data_in (in_packet),
.data_in_valid (in_packet_valid),
.data_in_ready (in_packet_ready),
.data_in_last (in_packet_last),
// Config In Channel
.cfg_size (cfg_size),
.cfg_scheme (cfg_scheme),
.cfg_last (cfg_last),
.cfg_valid (cfg_valid),
.cfg_ready (cfg_ready),
// Data Out Channel
.data_out (out_packet),
.data_out_last (out_packet_last),
.data_out_valid (out_packet_valid),
.data_out_ready (out_packet_ready)
);
wrapper_packet_deconstruct #(
(ADDRWIDTH - 1), // Only half address map allocated to this device
256 // Ouptut Packet WIdth
) u_wrapper_packet_deconstruct (
.hclk (HCLK),
.hresetn (HRESETn),
// Register interface
.addr (output_addr),
.read_en (output_read_en),
.write_en (output_write_en),
.byte_strobe (output_byte_strobe),
.wdata (output_wdata),
.rdata (output_rdata),
.wready (output_wready),
.rready (output_rready),
// Valid/Ready Interface
.packet_data (out_packet),
.packet_data_last (out_packet_last),
.packet_data_valid (out_packet_valid),
.packet_data_ready (out_packet_ready)
);
endmodule
\ No newline at end of file
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//-----------------------------------------------------------------------------
// SoC Labs Basic Wrapper Source
// - Valid-Ready Loopback example connecting packet constructor to deconstructor
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : AHB-lite example slave, support 4 32-bit register read and write,
// each register can be accessed by byte, half word or word.
// The example slave always output ready and OKAY response to the master
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "wrapper_packet_construct.sv"
`include "wrapper_packet_deconstruct.sv"
`include "wrapper_ahb_interface.sv"
module wrapper_vr_loopback #(
parameter ADDRWIDTH=12 // Peripheral Address Width
)(
input logic HCLK, // Clock
input logic HRESETn, // Reset
// AHB connection to Initiator
input logic HSELS,
input logic [ADDRWIDTH-1:0] HADDRS,
input logic [1:0] HTRANSS,
input logic [2:0] HSIZES,
input logic HWRITES,
input logic HREADYS,
input logic [31:0] HWDATAS,
output logic HREADYOUTS,
output logic HRESPS,
output logic [31:0] HRDATAS
);
// ----------------------------------------
// Internal wires declarations
// Register module interface signals
logic [ADDRWIDTH-1:0] in_buf_addr;
logic in_buf_read_en;
logic in_buf_write_en;
logic [3:0] in_buf_byte_strobe;
logic [31:0] in_buf_wdata;
logic [31:0] in_buf_rdata;
// Input Port Wire Declarations
logic [ADDRWIDTH-2:0] input_addr;
logic input_read_en;
logic input_write_en;
logic [3:0] input_byte_strobe;
logic [31:0] input_wdata;
logic [31:0] input_rdata;
logic input_wready;
logic input_rready;
// Output Port Wire Declarations
logic [ADDRWIDTH-2:0] output_addr;
logic output_read_en;
logic output_write_en;
logic [3:0] output_byte_strobe;
logic [31:0] output_wdata;
logic [31:0] output_rdata;
logic output_wready;
logic output_rready;
// Internal Wiring
logic [511:0] packet;
logic packet_last;
logic packet_valid;
logic packet_ready;
//-----------------------------------------------------------
// Module logic start
//----------------------------------------------------------
// Interface block to convert AHB transfers to Register transfers to engine input/output channels
// engine Input/Output Channels
wrapper_ahb_to_vr_interface #(
ADDRWIDTH
) u_wrapper_ahb_interface (
.hclk (HCLK),
.hresetn (HRESETn),
// Input slave port: 32 bit data bus interface
.hsels (HSELS),
.haddrs (HADDRS),
.htranss (HTRANSS),
.hsizes (HSIZES),
.hwrites (HWRITES),
.hreadys (HREADYS),
.hwdatas (HWDATAS),
.hreadyouts (HREADYOUTS),
.hresps (HRESPS),
.hrdatas (HRDATAS),
// Register interface - Accelerator Engine Input
.input_addr (input_addr),
.input_read_en (input_read_en),
.input_write_en (input_write_en),
.input_byte_strobe (input_byte_strobe),
.input_wdata (input_wdata),
.input_rdata (input_rdata),
.input_wready (input_wready),
.input_rready (input_rready),
// Register interface - Accelerator Engine Output
.output_addr (output_addr),
.output_read_en (output_read_en),
.output_write_en (output_write_en),
.output_byte_strobe (output_byte_strobe),
.output_wdata (output_wdata),
.output_rdata (output_rdata),
.output_wready (output_wready),
.output_rready (output_rready)
);
wrapper_packet_construct #(
(ADDRWIDTH - 1), // Only half address map allocated to this device
512 // Packet Width
) u_wrapper_packet_construct (
.hclk (HCLK),
.hresetn (HRESETn),
// Register interface
.addr (input_addr),
.read_en (input_read_en),
.write_en (input_write_en),
.byte_strobe (input_byte_strobe),
.wdata (input_wdata),
.rdata (input_rdata),
.wready (input_wready),
.rready (input_rready),
// Valid/Ready Interface
.packet_data (packet),
.packet_data_last (packet_last),
.packet_data_valid (packet_valid),
.packet_data_ready (packet_ready)
);
wrapper_packet_deconstruct #(
(ADDRWIDTH - 1), // Only half address map allocated to this device
512 // Ouptut Packet WIdth
) u_wrapper_packet_deconstruct (
.hclk (HCLK),
.hresetn (HRESETn),
// Register interface
.addr (output_addr),
.read_en (output_read_en),
.write_en (output_write_en),
.byte_strobe (output_byte_strobe),
.wdata (output_wdata),
.rdata (output_rdata),
.wready (output_wready),
.rready (output_rready),
// Valid/Ready Interface
.packet_data (packet),
.packet_data_last (packet_last),
.packet_data_valid (packet_valid),
.packet_data_ready (packet_ready)
);
//-----------------------------------------------------------
//Module logic end
//----------------------------------------------------------
`ifdef ARM_AHB_ASSERT_ON
`include "std_ovl_defines.h"
// ------------------------------------------------------------
// Assertions
// ------------------------------------------------------------
logic ovl_trans_req = HREADYS & HSELS & HTRANSS[1];
// Check the reg_write_en signal generated
assert_next
#(`OVL_ERROR, 1,1,0,
`OVL_ASSERT,
"Error! register write signal was not generated! "
)
u_ovl_ahb_eg_slave_reg_write
(.clk ( HCLK ),
.reset_n (HRESETn),
.start_event ((ovl_trans_req & HWRITES)),
.test_expr (reg_write_en == 1'b1)
);
// Check the reg_read_en signal generated
assert_next
#(`OVL_ERROR, 1,1,0,
`OVL_ASSERT,
"Error! register read signal was not generated! "
)
u_ovl_ahb_eg_slave_reg_read
(.clk ( HCLK ),
.reset_n (HRESETn),
.start_event ((ovl_trans_req & (~HWRITES))),
.test_expr (reg_read_en == 1'b1)
);
// Check register read and write operation won't assert at the same cycle
assert_never
#(`OVL_ERROR,
`OVL_ASSERT,
"Error! register read and write active at the same cycle!")
u_ovl_ahb_eg_slave_rd_wr_illegal
(.clk(HCLK),
.reset_n(HRESETn),
.test_expr((reg_write_en & reg_read_en))
);
`endif
endmodule
\ No newline at end of file
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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : AHB-Lite Default Slave
//-----------------------------------------------------------------------------
//
// Returns an error response when selected for a transfer
//
module cmsdk_ahb_default_slave (
// Inputs
input wire HCLK, // Clock
input wire HRESETn, // Reset
input wire HSEL, // Slave select
input wire [1:0] HTRANS, // Transfer type
input wire HREADY, // System ready
// Outputs
output wire HREADYOUT, // Slave ready
output wire HRESP); // Slave response
//
// Start of main code
//
// Internal signals
wire trans_req; // Transfer Request
reg [1:0] resp_state; // Current FSM state for two-cycle error response
wire [1:0] next_state; // Next FSM state
// Transfer address phase completes
assign trans_req = HSEL & HTRANS[1] & HREADY;
// Generate next state for the FSM.
// Bit 0 is connected to HREADYOUT and bit 1 is connected to HRESP,
// so the state encodings are:
// 01 - Idle
// 10 - 1st cycle of error response
// 11 - 2nd cycle of error response
assign next_state = { trans_req | (~resp_state[0]),
~trans_req };
// Registering FSM state
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn)
resp_state <= 2'b01; // ensure HREADYOUT is HIGH at reset
else
resp_state <= next_state;
// Connect to output
assign HREADYOUT = resp_state[0];
assign HRESP = resp_state[1];
`ifdef ARM_AHB_ASSERT_ON
// ------------------------------------------------------------
// Assertions
// ------------------------------------------------------------
`include "std_ovl_defines.h"
reg ovl_last_hreadyout;
reg ovl_last_hsel;
reg [1:0] ovl_last_htrans;
reg ovl_last_hready;
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
begin
ovl_last_hreadyout <= 1'b1;
ovl_last_hsel <= 1'b0;
ovl_last_htrans <= 2'b00;
ovl_last_hready <= 1'b1;
end
else
begin
ovl_last_hreadyout <= HREADYOUT;
ovl_last_hsel <= HSEL;
ovl_last_htrans <= HTRANS;
ovl_last_hready <= HREADY;
end
end
assert_implication
#(`OVL_ERROR,`OVL_ASSERT,
"If HREADYOUT is 0, HRESP must be high")
u_ovl_error_response_check_1
(.clk(HCLK), .reset_n(HRESETn),
.antecedent_expr(~HREADYOUT),
.consequent_expr(HRESP)
);
assert_implication
#(`OVL_ERROR,`OVL_ASSERT,
"If in last cycle HREADYOUT is 0, this cycle both HRESP and HREADYOUT")
u_ovl_error_response_check_2
(.clk(HCLK), .reset_n(HRESETn),
.antecedent_expr(~ovl_last_hreadyout),
.consequent_expr(HRESP & HREADYOUT)
);
assert_implication
#(`OVL_ERROR,`OVL_ASSERT,
"If device is not selected, or if transfer is idle/busy, response must be OKAY")
u_ovl_error_fault_check_1
(.clk(HCLK), .reset_n(HRESETn),
.antecedent_expr(~(ovl_last_hsel & ovl_last_htrans[1]) & ovl_last_hready),
.consequent_expr((~HRESP) & HREADYOUT)
);
assert_implication
#(`OVL_ERROR,`OVL_ASSERT,
"If device is selected, and if transfer is nseq/seq, response must be ERROR")
u_ovl_error_fault_check_2
(.clk(HCLK), .reset_n(HRESETn),
.antecedent_expr(ovl_last_hsel & ovl_last_htrans[1] & ovl_last_hready),
.consequent_expr(HRESP & (~HREADYOUT))
);
`endif
endmodule
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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Convert 64-bit bus from ahb_fileread_core to 32-bit
//-----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Purpose : A data bus multiplexor, used to connect a 32 bit slave
// to a 64 bit bus.
// Supports transfers up to 32 bit in size.
// --========================================================================--
module cmsdk_ahb_fileread_funnel (
// Clock and Reset
input wire HCLK,
input wire HRESETn,
// Interface to AHB
input wire HADDR2S,
input wire [63:0] HWDATAS,
input wire HREADYS,
output wire [63:0] HRDATAS,
// Interface to slave
output reg [31:0] HWDATAM,
input wire [31:0] HRDATAM);
// -----------------------------------------------------------------------------
// Signal Declarations
// -----------------------------------------------------------------------------
reg haddr2s_reg; // Delayed version of address bit2
// =============================================================================
// Beginning of main verilog code
// =============================================================================
//------------------------------------------------------------------------------
// Generate Delayed version of HADDR2S
//------------------------------------------------------------------------------
always@(posedge HCLK or negedge HRESETn)
begin : p_haddr2s_reg
if (HRESETn == 1'b0)
haddr2s_reg <= 1'b0;
else
begin
if (HREADYS == 1'b1)
haddr2s_reg <= HADDR2S;
end
end // block: p_haddr2s_reg
// -----------------------------------------------------------------------------
// Write Data MUX
// -----------------------------------------------------------------------------
// Note: To support Big-Endian systems the polarity of the HWDATAM MUX should be
// reversed.
always@(haddr2s_reg or HWDATAS)
begin : p_write_mux
if (haddr2s_reg == 1'b0)
HWDATAM = HWDATAS[31:0];
else
HWDATAM = HWDATAS[63:32];
end // block: p_write_mux
// -----------------------------------------------------------------------------
// Read Data bus
// -----------------------------------------------------------------------------
assign HRDATAS = {HRDATAM,HRDATAM};
endmodule
// --================================= End ===================================--
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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : 32-bit AHB File Reader Bus Master
//-----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Purpose : This entity ties together the sub blocks that
// form the 32-bit File Reader Bus Master, namely an
// AHB-Lite File Reader Core and a bus funnel .
// --========================================================================--
// Note
// This top level file converts AHB Lite extension
// signals in ARM1136 to sideband signals used in
// Cortex-M3/M4
// --========================================================================--
module cmsdk_ahb_fileread_master32 #(
parameter InputFileName = "filestim.m2d", // stimulus data file name
parameter MessageTag = "FileReader:", // tag on each FileReader message
parameter StimArraySize = 5000) // stimulus data array size:
// should be large enough to hold
// entire stimulus data file
(
// system ports
input wire HCLK, // system clock
input wire HRESETn, // system reset
// AHB ports
input wire HREADY, // slave ready signal
input wire HRESP, // slave response bus
input wire [31:0] HRDATA, // data, slave to master
input wire EXRESP, // Exclusive response (tie low if not used)
output wire [1:0] HTRANS, // transfer type
output wire [2:0] HBURST, // burst type
output wire [3:0] HPROT, // transfer protection
output wire EXREQ, // Exclusive access request
output wire [1:0] MEMATTR, // Memory attribute
output wire [2:0] HSIZE, // transfer size
output wire HWRITE, // transfer direction
output wire HMASTLOCK, // transfer is locked
output wire [31:0] HADDR, // transfer address
output wire [31:0] HWDATA, // data, master to slave
output wire [31:0] LINENUM); // line number in stimulus file
// Internal AHB-Lite Bus Signals
wire [2:0] hresp_core; // slave response
wire [63:0] hrdata_core; // data from slave to master
wire [31:0] haddr_core; // transfer address
wire [63:0] hwdata_core; // data from master to slave
wire [5:0] hprot_core; // transfer protection
//------------------------------------------------------------------------------
// structural
//------------------------------------------------------------------------------
// Instance of AHB-Lite File Reader connected to internal AHB-Lite system
cmsdk_ahb_filereadcore
#(.input_filename(InputFileName),
.message_tag(MessageTag),
.stim_array_size(StimArraySize))
u_ahb_filereadcore (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (HREADY),
.HRESP (hresp_core),
.HRDATA (hrdata_core),
.HTRANS (HTRANS),
.HBURST (HBURST),
.HPROT (hprot_core),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HMASTLOCK (HMASTLOCK),
.HADDR (haddr_core),
.HWDATA (hwdata_core),
.HUNALIGN (),
.HBSTRB (),
.LINENUM (LINENUM)
);
// Instance of a Funnel to translate the 64-bit AHB-Lite data bus to 32-bit.
cmsdk_ahb_fileread_funnel u_ahb_fileread_funnel (
.HCLK (HCLK),
.HRESETn (HRESETn),
// 64-bit interface to AHB
.HREADYS (HREADY),
.HADDR2S (haddr_core[2]),
.HWDATAS (hwdata_core),
.HRDATAS (hrdata_core),
// 32-bit interface to slave
.HWDATAM (HWDATA),
.HRDATAM (HRDATA)
);
// Convert internal versions of port signals
assign HADDR = haddr_core; // Drive port with internal signal
assign HPROT = hprot_core[3:0];
assign EXREQ = hprot_core[5];
assign MEMATTR = {1'b0, hprot_core[4]};
assign hresp_core = {EXRESP, 1'b0,HRESP}; // Drive unused bit of hresp_core
endmodule
// --================================ End ==================================--
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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Simple AHB RAM behavioral model
//-----------------------------------------------------------------------------
module cmsdk_ahb_ram_beh #(
parameter AW = 16,// Address width
parameter filename = "",
parameter WS_N = 0, // First access wait state
parameter WS_S = 0) // Subsequent access wait state
(
input wire HCLK, // Clock
input wire HRESETn, // Reset
input wire HSEL, // Device select
input wire [AW-1:0] HADDR, // Address
input wire [1:0] HTRANS, // Transfer control
input wire [2:0] HSIZE, // Transfer size
input wire HWRITE, // Write control
input wire [31:0] HWDATA, // Write data
input wire HREADY, // Transfer phase done
output wire HREADYOUT, // Device ready
output wire [31:0] HRDATA, // Read data output
output wire HRESP); // Device response (always OKAY)
// Internal signals
reg [7:0] ram_data[0:((1<<AW)-1)]; // 64k byte of RAM data
wire read_valid; // Address phase read valid
wire write_valid; // Address phase write valid
reg read_enable; // Data phase read enable
reg write_enable; // Data phase write enable
reg [3:0] reg_byte_lane; // Data phase byte lane
reg [3:0] next_byte_lane; // Next state of reg_byte_lane
reg [7:0] rdata_out_0; // Read Data Output byte#0
reg [7:0] rdata_out_1; // Read Data Output byte#1
reg [7:0] rdata_out_2; // Read Data Output byte#2
reg [7:0] rdata_out_3; // Read Data Output byte#3
reg [AW-1:0] word_addr; // Word aligned address
wire [AW-1:0] nxt_word_addr; // Word aligned address
integer i; // Loop counter
// Wait state control
wire [31:0] nxt_waitstate_cnt;
reg [31:0] reg_waitstate_cnt;
wire sequential_access;
// Start of main code
// Initialize ROM
initial
begin
for (i=0;i<(1<<AW);i=i+1)
begin
ram_data[i] = 8'h00; //Initialize all data to 0
end
if (filename != "")
begin
$readmemh(filename, ram_data); // Then read in program code
end
end
// Generate read control (address phase)
assign read_valid = HSEL & HREADY & HTRANS[1] & (~HWRITE);
// Generate write control (address phase)
assign write_valid = HSEL & HREADY & HTRANS[1] & HWRITE;
// Read enable for each byte (address phase)
always @(read_valid or write_valid or HADDR or HSIZE)
begin
if (read_valid | write_valid)
begin
case (HSIZE)
0 : // Byte
begin
case (HADDR[1:0])
0: next_byte_lane = 4'b0001; // Byte 0
1: next_byte_lane = 4'b0010; // Byte 1
2: next_byte_lane = 4'b0100; // Byte 2
3: next_byte_lane = 4'b1000; // Byte 3
default:next_byte_lane = 4'b0000; // Address not valid
endcase
end
1 : // Halfword
begin
if (HADDR[1])
next_byte_lane = 4'b1100; // Upper halfword
else
next_byte_lane = 4'b0011; // Lower halfword
end
default : // Word
next_byte_lane = 4'b1111; // Whole word
endcase
end
else
next_byte_lane = 4'b0000; // Not reading
end
// Registering control signals to data phase
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
begin
reg_byte_lane <= 4'b0000;
read_enable <= 1'b0;
write_enable <= 1'b0;
word_addr <= {AW{1'b0}};
end
else if (HREADY)
begin
reg_byte_lane <= next_byte_lane;
read_enable <= read_valid;
write_enable <= write_valid;
word_addr <= nxt_word_addr;
end
end
assign nxt_word_addr = {HADDR[AW-1:2], 2'b00};
// Read operation
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[0]))
rdata_out_0 = ram_data[word_addr ];
else
rdata_out_0 = 8'h00;
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[1]))
rdata_out_1 = ram_data[word_addr+1];
else
rdata_out_1 = 8'h00;
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[2]))
rdata_out_2 = ram_data[word_addr+2];
else
rdata_out_2 = 8'h00;
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[3]))
rdata_out_3 = ram_data[word_addr+3];
else
rdata_out_3 = 8'h00;
// Registered write
always @(posedge HCLK)
begin
if (write_enable & reg_byte_lane[0])
begin
ram_data[word_addr ] = HWDATA[ 7: 0];
end
if (write_enable & reg_byte_lane[1])
begin
ram_data[word_addr+1] = HWDATA[15: 8];
end
if (write_enable & reg_byte_lane[2])
begin
ram_data[word_addr+2] = HWDATA[23:16];
end
if (write_enable & reg_byte_lane[3])
begin
ram_data[word_addr+3] = HWDATA[31:24];
end
end
// Wait state control
// Wait state generate treat access as sequential if
// HTRANS = 2'b11, or access address is in the same word,
// or if the access is in the next word
assign sequential_access = (HTRANS==2'b11) |
(HADDR[AW-1:2] == word_addr[AW-1:2]) |
(HADDR[AW-1:2] == (word_addr[AW-1:2]+1));
assign nxt_waitstate_cnt = (read_valid|write_valid) ?
((sequential_access) ? WS_S : WS_N) :
((reg_waitstate_cnt!=0) ? (reg_waitstate_cnt - 1) : 0);
// Register wait state counter
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
reg_waitstate_cnt <= 0;
else
reg_waitstate_cnt <= nxt_waitstate_cnt;
end
// Connect to top level
assign HREADYOUT = (reg_waitstate_cnt==0) ? 1'b1 : 1'b0;
assign HRESP = 1'b0; // Always response with OKAY
// Read data output
assign HRDATA = {rdata_out_3, rdata_out_2, rdata_out_1,rdata_out_0};
endmodule
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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Simple AHB slave multiplexer
//-----------------------------------------------------------------------------
// Each port can be disabled by parameter if not used.
module cmsdk_ahb_slave_mux #(
// Parameters to enable/disable ports
// By default all ports are enabled
parameter PORT0_ENABLE=1,
parameter PORT1_ENABLE=1,
parameter PORT2_ENABLE=1,
parameter PORT3_ENABLE=1,
parameter PORT4_ENABLE=1,
parameter PORT5_ENABLE=1,
parameter PORT6_ENABLE=1,
parameter PORT7_ENABLE=1,
parameter PORT8_ENABLE=1,
parameter PORT9_ENABLE=1,
// Data Bus Width
parameter DW=32
)
(
input wire HCLK, // Clock
input wire HRESETn, // Reset
input wire HREADY, // Bus ready
input wire HSEL0, // HSEL for AHB Slave #0
input wire HREADYOUT0, // HREADY for Slave connection #0
input wire HRESP0, // HRESP for slave connection #0
input wire [DW-1:0] HRDATA0, // HRDATA for slave connection #0
input wire HSEL1, // HSEL for AHB Slave #1
input wire HREADYOUT1, // HREADY for Slave connection #1
input wire HRESP1, // HRESP for slave connection #1
input wire [DW-1:0] HRDATA1, // HRDATA for slave connection #1
input wire HSEL2, // HSEL for AHB Slave #2
input wire HREADYOUT2, // HREADY for Slave connection #2
input wire HRESP2, // HRESP for slave connection #2
input wire [DW-1:0] HRDATA2, // HRDATA for slave connection #2
input wire HSEL3, // HSEL for AHB Slave #3
input wire HREADYOUT3, // HREADY for Slave connection #3
input wire HRESP3, // HRESP for slave connection #3
input wire [DW-1:0] HRDATA3, // HRDATA for slave connection #3
input wire HSEL4, // HSEL for AHB Slave #4
input wire HREADYOUT4, // HREADY for Slave connection #4
input wire HRESP4, // HRESP for slave connection #4
input wire [DW-1:0] HRDATA4, // HRDATA for slave connection #4
input wire HSEL5, // HSEL for AHB Slave #5
input wire HREADYOUT5, // HREADY for Slave connection #5
input wire HRESP5, // HRESP for slave connection #5
input wire [DW-1:0] HRDATA5, // HRDATA for slave connection #5
input wire HSEL6, // HSEL for AHB Slave #6
input wire HREADYOUT6, // HREADY for Slave connection #6
input wire HRESP6, // HRESP for slave connection #6
input wire [DW-1:0] HRDATA6, // HRDATA for slave connection #6
input wire HSEL7, // HSEL for AHB Slave #7
input wire HREADYOUT7, // HREADY for Slave connection #7
input wire HRESP7, // HRESP for slave connection #7
input wire [DW-1:0] HRDATA7, // HRDATA for slave connection #7
input wire HSEL8, // HSEL for AHB Slave #8
input wire HREADYOUT8, // HREADY for Slave connection #8
input wire HRESP8, // HRESP for slave connection #8
input wire [DW-1:0] HRDATA8, // HRDATA for slave connection #8
input wire HSEL9, // HSEL for AHB Slave #9
input wire HREADYOUT9, // HREADY for Slave connection #9
input wire HRESP9, // HRESP for slave connection #9
input wire [DW-1:0] HRDATA9, // HRDATA for slave connection #9
output wire HREADYOUT, // HREADY output to AHB master and AHB slaves
output wire HRESP, // HRESP to AHB master
output wire [DW-1:0] HRDATA // Read data to AHB master
);
wire mux_hready; // multiplexed HREADY sigal
reg [9:0] reg_hsel; // Register selection control
wire [9:0] nxt_hsel_reg; // next state for nxt_hsel_reg
assign nxt_hsel_reg[0] = HSEL0 & (PORT0_ENABLE!=0);
assign nxt_hsel_reg[1] = HSEL1 & (PORT1_ENABLE!=0);
assign nxt_hsel_reg[2] = HSEL2 & (PORT2_ENABLE!=0);
assign nxt_hsel_reg[3] = HSEL3 & (PORT3_ENABLE!=0);
assign nxt_hsel_reg[4] = HSEL4 & (PORT4_ENABLE!=0);
assign nxt_hsel_reg[5] = HSEL5 & (PORT5_ENABLE!=0);
assign nxt_hsel_reg[6] = HSEL6 & (PORT6_ENABLE!=0);
assign nxt_hsel_reg[7] = HSEL7 & (PORT7_ENABLE!=0);
assign nxt_hsel_reg[8] = HSEL8 & (PORT8_ENABLE!=0);
assign nxt_hsel_reg[9] = HSEL9 & (PORT9_ENABLE!=0);
// Registering MuxCtrl
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
reg_hsel <= {10{1'b0}};
else if (HREADY) // advance pipeline if HREADY is 1
reg_hsel <= nxt_hsel_reg;
end
assign mux_hready =
((~reg_hsel[0]) | HREADYOUT0 | (PORT0_ENABLE==0)) &
((~reg_hsel[1]) | HREADYOUT1 | (PORT1_ENABLE==0)) &
((~reg_hsel[2]) | HREADYOUT2 | (PORT2_ENABLE==0)) &
((~reg_hsel[3]) | HREADYOUT3 | (PORT3_ENABLE==0)) &
((~reg_hsel[4]) | HREADYOUT4 | (PORT4_ENABLE==0)) &
((~reg_hsel[5]) | HREADYOUT5 | (PORT5_ENABLE==0)) &
((~reg_hsel[6]) | HREADYOUT6 | (PORT6_ENABLE==0)) &
((~reg_hsel[7]) | HREADYOUT7 | (PORT7_ENABLE==0)) &
((~reg_hsel[8]) | HREADYOUT8 | (PORT8_ENABLE==0)) &
((~reg_hsel[9]) | HREADYOUT9 | (PORT9_ENABLE==0)) ;
assign HREADYOUT = mux_hready; // Connect to top level
assign HRDATA =
({DW{(reg_hsel[0] & (PORT0_ENABLE!=0))}} & HRDATA0) |
({DW{(reg_hsel[1] & (PORT1_ENABLE!=0))}} & HRDATA1) |
({DW{(reg_hsel[2] & (PORT2_ENABLE!=0))}} & HRDATA2) |
({DW{(reg_hsel[3] & (PORT3_ENABLE!=0))}} & HRDATA3) |
({DW{(reg_hsel[4] & (PORT4_ENABLE!=0))}} & HRDATA4) |
({DW{(reg_hsel[5] & (PORT5_ENABLE!=0))}} & HRDATA5) |
({DW{(reg_hsel[6] & (PORT6_ENABLE!=0))}} & HRDATA6) |
({DW{(reg_hsel[7] & (PORT7_ENABLE!=0))}} & HRDATA7) |
({DW{(reg_hsel[8] & (PORT8_ENABLE!=0))}} & HRDATA8) |
({DW{(reg_hsel[9] & (PORT9_ENABLE!=0))}} & HRDATA9) ;
assign HRESP =
(reg_hsel[0] & HRESP0 & (PORT0_ENABLE!=0)) |
(reg_hsel[1] & HRESP1 & (PORT1_ENABLE!=0)) |
(reg_hsel[2] & HRESP2 & (PORT2_ENABLE!=0)) |
(reg_hsel[3] & HRESP3 & (PORT3_ENABLE!=0)) |
(reg_hsel[4] & HRESP4 & (PORT4_ENABLE!=0)) |
(reg_hsel[5] & HRESP5 & (PORT5_ENABLE!=0)) |
(reg_hsel[6] & HRESP6 & (PORT6_ENABLE!=0)) |
(reg_hsel[7] & HRESP7 & (PORT7_ENABLE!=0)) |
(reg_hsel[8] & HRESP8 & (PORT8_ENABLE!=0)) |
(reg_hsel[9] & HRESP9 & (PORT9_ENABLE!=0)) ;
// ------------------------------------------------------------
`ifdef ARM_AHB_ASSERT_ON
// ------------------------------------------------------------
// Assertions
// ------------------------------------------------------------
`include "std_ovl_defines.h"
// When HREADYOUT is low, reg_hsel must be non-zero (Property of design)
assert_never
#(`OVL_ERROR,`OVL_ASSERT,
"reg_hsel must not be zero when HREADYOUT is low")
u_ovl_readyout_asserted_when_not_active
(.clk(HCLK), .reset_n(HRESETn),
.test_expr( (~HREADYOUT) & (reg_hsel=={10{1'b0}}))
);
// Properties of the inputs of the design
// HSEL should be one-hot
// If this OVL fires - there is an error in the design of the address decoder
assert_zero_one_hot
#(`OVL_FATAL,10,`OVL_ASSERT,
"Only one HSEL input can be activated.")
u_ovl_hsel_one_hot
(.clk(HCLK), .reset_n(HRESETn),
.test_expr({HSEL0,
HSEL1,
HSEL2,
HSEL3,
HSEL4,
HSEL5,
HSEL6,
HSEL7,
HSEL8,
HSEL9}));
// When HREADYOUT is low, HREADY should be low
assert_never
#(`OVL_ERROR,`OVL_ASSERT,
"HREADY should be low when HREADYOUT is low")
u_ovl_ready_mismatch
(.clk(HCLK), .reset_n(HRESETn),
.test_expr( (~HREADYOUT) & HREADY )
);
// Check if a disabled port is selected
// (system design error, check the verilog parameter in module instantiation)
assert_never
#(`OVL_ERROR,`OVL_ASSERT,
"A disabled port is selected")
u_ovl_disabled_port_selected
(.clk(HCLK), .reset_n(HRESETn),
.test_expr(HREADY & (
((PORT0_ENABLE==0) & HSEL0) |
((PORT1_ENABLE==0) & HSEL1) |
((PORT2_ENABLE==0) & HSEL2) |
((PORT3_ENABLE==0) & HSEL3) |
((PORT4_ENABLE==0) & HSEL4) |
((PORT5_ENABLE==0) & HSEL5) |
((PORT6_ENABLE==0) & HSEL6) |
((PORT7_ENABLE==0) & HSEL7) |
((PORT8_ENABLE==0) & HSEL8) |
((PORT9_ENABLE==0) & HSEL9)
))
);
`endif
endmodule
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//-----------------------------------------------------------------------------
// SoC Labs Basic Testbench for Top-level AHB Wrapper
// Modified from tb_frbm_example.v
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Abstract : Example for File Reader Bus Master
// Testbench for the example AHB Lite slave.
//=========================================================================--
`include "wrapper_sha256_hashing_stream.sv"
`timescale 1ns/1ps
module tb_wrapper_sha256_hashing_stream;
parameter CLK_PERIOD = 10;
parameter ADDRWIDTH = 12;
parameter InputFileName = ("../../accelerator-wrapper/simulate/stimulus/ahb_input_hash_stim.m2d");
parameter MessageTag = "FileReader:";
parameter StimArraySize = 10000;
//********************************************************************************
// Internal Wires
//********************************************************************************
// AHB Lite BUS SIGNALS
wire hready;
wire hresp;
wire [31:0] hrdata;
wire [1:0] htrans;
wire [2:0] hburst;
wire [3:0] hprot;
wire [2:0] hsize;
wire hwrite;
wire hmastlock;
wire [31:0] haddr;
wire [31:0] hwdata;
// Accelerator AHB Signals
wire hsel0;
wire hreadyout0;
wire hresp0;
wire [31:0] hrdata0;
// Default Slave AHB Signals
wire hsel1;
wire hreadyout1;
wire hresp1;
wire [31:0] hrdata1;
reg HCLK;
reg HRESETn;
//********************************************************************************
// Clock and reset generation
//********************************************************************************
initial
begin
$dumpfile("wrapper_sha256_hashing_stream.vcd");
$dumpvars(0, tb_wrapper_sha256_hashing_stream);
HRESETn = 1'b0;
HCLK = 1'b0;
# (10*CLK_PERIOD);
HRESETn = 1'b1;
end
always
begin
HCLK = #(CLK_PERIOD/2) ~HCLK;
end
//********************************************************************************
// Address decoder, need to be changed for other configuration
//********************************************************************************
// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator
// Other addresses : HSEL #1 - Default slave
assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0;
assign hsel1 = hsel0 ? 1'b0:1'b1;
//********************************************************************************
// File read bus master:
// generate AHB Master signal by reading a file which store the AHB Operations
//********************************************************************************
cmsdk_ahb_fileread_master32 #(InputFileName,
MessageTag,
StimArraySize
) u_ahb_fileread_master32 (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (hready),
.HRESP ({hresp}), //AHB Lite response to AHB response
.HRDATA (hrdata),
.EXRESP (1'b0), // Exclusive response (tie low if not used)
.HTRANS (htrans),
.HBURST (hburst),
.HPROT (hprot),
.EXREQ (), // Exclusive access request (not used)
.MEMATTR (), // Memory attribute (not used)
.HSIZE (hsize),
.HWRITE (hwrite),
.HMASTLOCK (hmastlock),
.HADDR (haddr),
.HWDATA (hwdata),
.LINENUM ()
);
//********************************************************************************
// Slave multiplexer module:
// multiplex the slave signals to master, three ports are enabled
//********************************************************************************
cmsdk_ahb_slave_mux #(
1, //PORT0_ENABLE
1, //PORT1_ENABLE
1, //PORT2_ENABLE
0, //PORT3_ENABLE
0, //PORT4_ENABLE
0, //PORT5_ENABLE
0, //PORT6_ENABLE
0, //PORT7_ENABLE
0, //PORT8_ENABLE
0 //PORT9_ENABLE
) u_ahb_slave_mux (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (hready),
.HSEL0 (hsel0), // Input Port 0
.HREADYOUT0 (hreadyout0),
.HRESP0 (hresp0),
.HRDATA0 (hrdata0),
.HSEL1 (hsel1), // Input Port 1
.HREADYOUT1 (hreadyout1),
.HRESP1 (hresp1),
.HRDATA1 (hrdata1),
.HSEL2 (1'b0), // Input Port 2
.HREADYOUT2 (),
.HRESP2 (),
.HRDATA2 (),
.HSEL3 (1'b0), // Input Port 3
.HREADYOUT3 (),
.HRESP3 (),
.HRDATA3 (),
.HSEL4 (1'b0), // Input Port 4
.HREADYOUT4 (),
.HRESP4 (),
.HRDATA4 (),
.HSEL5 (1'b0), // Input Port 5
.HREADYOUT5 (),
.HRESP5 (),
.HRDATA5 (),
.HSEL6 (1'b0), // Input Port 6
.HREADYOUT6 (),
.HRESP6 (),
.HRDATA6 (),
.HSEL7 (1'b0), // Input Port 7
.HREADYOUT7 (),
.HRESP7 (),
.HRDATA7 (),
.HSEL8 (1'b0), // Input Port 8
.HREADYOUT8 (),
.HRESP8 (),
.HRDATA8 (),
.HSEL9 (1'b0), // Input Port 9
.HREADYOUT9 (),
.HRESP9 (),
.HRDATA9 (),
.HREADYOUT (hready), // Outputs
.HRESP (hresp),
.HRDATA (hrdata)
);
//********************************************************************************
// Slave module 1: example AHB slave module
//********************************************************************************
wrapper_sha256_hashing_stream #(ADDRWIDTH
) accelerator (
.HCLK (HCLK),
.HRESETn (HRESETn),
// Input slave port: 32 bit data bus interface
.HSELS (hsel0),
.HADDRS (haddr[ADDRWIDTH-1:0]),
.HTRANSS (htrans),
.HSIZES (hsize),
.HWRITES (hwrite),
.HREADYS (hready),
.HWDATAS (hwdata),
.HREADYOUTS (hreadyout0),
.HRESPS (hresp0),
.HRDATAS (hrdata0)
);
//********************************************************************************
// Slave module 2: AHB default slave module
//********************************************************************************
cmsdk_ahb_default_slave u_ahb_default_slave(
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (hsel1),
.HTRANS (htrans),
.HREADY (hready),
.HREADYOUT (hreadyout1),
.HRESP (hresp1)
);
assign hrdata1 = {32{1'b0}}; // Default slave don't have data
endmodule
\ No newline at end of file
hdl/verif/tb_wrapper_vr_loopback.sv deleted 100644 → 0
+ 0
− 260
View file @ 89c27574
//-----------------------------------------------------------------------------
// SoC Labs Basic Testbench for Wrapper Valid-Ready Loopback Test
// Modified from tb_frbm_example.v
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Abstract : Example for File Reader Bus Master
// Testbench for the example AHB Lite slave.
//=========================================================================--
`include "cmsdk_ahb_filereadcore.v"
`include "cmsdk_ahb_fileread_funnel.v"
`include "cmsdk_ahb_fileread_master32.v"
`include "cmsdk_ahb_default_slave.v"
`include "cmsdk_ahb_slave_mux.v"
`include "wrapper_vr_loopback.sv"
`timescale 1ns/1ps
module tb_wrapper_vr_loopback;
parameter CLK_PERIOD = 10;
parameter ADDRWIDTH = 12;
// parameter InputFileName = "ahb_input_hash_stim.m2d";
parameter InputFileName = ("../stimulus/ahb_input_hash_stim.m2d");
parameter MessageTag = "FileReader:";
parameter StimArraySize = 10000;
//********************************************************************************
// Internal Wires
//********************************************************************************
// AHB Lite BUS SIGNALS
wire hready;
wire hresp;
wire [31:0] hrdata;
wire [1:0] htrans;
wire [2:0] hburst;
wire [3:0] hprot;
wire [2:0] hsize;
wire hwrite;
wire hmastlock;
wire [31:0] haddr;
wire [31:0] hwdata;
// Accelerator AHB Signals
wire hsel0;
wire hreadyout0;
wire hresp0;
wire [31:0] hrdata0;
// Default Slave AHB Signals
wire hsel1;
wire hreadyout1;
wire hresp1;
wire [31:0] hrdata1;
reg HCLK;
reg HRESETn;
//********************************************************************************
// Clock and reset generation
//********************************************************************************
initial
begin
$dumpfile("wrapper_vr_loopback.vcd");
$dumpvars(0, tb_wrapper_vr_loopback);
HRESETn = 1'b0;
HCLK = 1'b0;
# (10*CLK_PERIOD);
HRESETn = 1'b1;
end
always
begin
HCLK = #(CLK_PERIOD/2) ~HCLK;
end
//********************************************************************************
// Address decoder, need to be changed for other configuration
//********************************************************************************
// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator
// Other addresses : HSEL #1 - Default slave
assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0;
assign hsel1 = hsel0 ? 1'b0:1'b1;
//********************************************************************************
// File read bus master:
// generate AHB Master signal by reading a file which store the AHB Operations
//********************************************************************************
cmsdk_ahb_fileread_master32 #(InputFileName,
MessageTag,
StimArraySize
) u_ahb_fileread_master32 (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (hready),
.HRESP ({hresp}), //AHB Lite response to AHB response
.HRDATA (hrdata),
.EXRESP (1'b0), // Exclusive response (tie low if not used)
.HTRANS (htrans),
.HBURST (hburst),
.HPROT (hprot),
.EXREQ (), // Exclusive access request (not used)
.MEMATTR (), // Memory attribute (not used)
.HSIZE (hsize),
.HWRITE (hwrite),
.HMASTLOCK (hmastlock),
.HADDR (haddr),
.HWDATA (hwdata),
.LINENUM ()
);
//********************************************************************************
// Slave multiplexer module:
// multiplex the slave signals to master, three ports are enabled
//********************************************************************************
cmsdk_ahb_slave_mux #(
1, //PORT0_ENABLE
1, //PORT1_ENABLE
1, //PORT2_ENABLE
0, //PORT3_ENABLE
0, //PORT4_ENABLE
0, //PORT5_ENABLE
0, //PORT6_ENABLE
0, //PORT7_ENABLE
0, //PORT8_ENABLE
0 //PORT9_ENABLE
) u_ahb_slave_mux (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (hready),
.HSEL0 (hsel0), // Input Port 0
.HREADYOUT0 (hreadyout0),
.HRESP0 (hresp0),
.HRDATA0 (hrdata0),
.HSEL1 (hsel1), // Input Port 1
.HREADYOUT1 (hreadyout1),
.HRESP1 (hresp1),
.HRDATA1 (hrdata1),
.HSEL2 (1'b0), // Input Port 2
.HREADYOUT2 (),
.HRESP2 (),
.HRDATA2 (),
.HSEL3 (1'b0), // Input Port 3
.HREADYOUT3 (),
.HRESP3 (),
.HRDATA3 (),
.HSEL4 (1'b0), // Input Port 4
.HREADYOUT4 (),
.HRESP4 (),
.HRDATA4 (),
.HSEL5 (1'b0), // Input Port 5
.HREADYOUT5 (),
.HRESP5 (),
.HRDATA5 (),
.HSEL6 (1'b0), // Input Port 6
.HREADYOUT6 (),
.HRESP6 (),
.HRDATA6 (),
.HSEL7 (1'b0), // Input Port 7
.HREADYOUT7 (),
.HRESP7 (),
.HRDATA7 (),
.HSEL8 (1'b0), // Input Port 8
.HREADYOUT8 (),
.HRESP8 (),
.HRDATA8 (),
.HSEL9 (1'b0), // Input Port 9
.HREADYOUT9 (),
.HRESP9 (),
.HRDATA9 (),
.HREADYOUT (hready), // Outputs
.HRESP (hresp),
.HRDATA (hrdata)
);
//********************************************************************************
// Slave module 1: example AHB slave module
//********************************************************************************
wrapper_vr_loopback #(ADDRWIDTH
) accelerator (
.HCLK (HCLK),
.HRESETn (HRESETn),
// Input slave port: 32 bit data bus interface
.HSELS (hsel0),
.HADDRS (haddr[ADDRWIDTH-1:0]),
.HTRANSS (htrans),
.HSIZES (hsize),
.HWRITES (hwrite),
.HREADYS (hready),
.HWDATAS (hwdata),
.HREADYOUTS (hreadyout0),
.HRESPS (hresp0),
.HRDATAS (hrdata0)
);
//********************************************************************************
// Slave module 2: AHB default slave module
//********************************************************************************
cmsdk_ahb_default_slave u_ahb_default_slave(
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (hsel1),
.HTRANS (htrans),
.HREADY (hready),
.HREADYOUT (hreadyout1),
.HRESP (hresp1)
);
assign hrdata1 = {32{1'b0}}; // Default slave don't have data
endmodule
\ No newline at end of file
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