diff --git a/README.md b/README.md
index 1d723ec762a79686650528e9d79277681f3d2c84..b991a828aabd9c12444de13b6c9a8fadbf039d66 100644
--- a/README.md
+++ b/README.md
@@ -1,9 +1,3 @@
# SoC Labs Accelerator Wrapper
-Tests
-This sample project shows how a project in GitLab looks for demonstration purposes. It contains issues, merge requests and Markdown files in many branches,
-named and filled with lorem ipsum.
-
-You can look around to get an idea how to structure your project and, when done, you can safely delete this project.
-
-[Learn more about creating GitLab projects.](https://docs.gitlab.com/ee/gitlab-basics/create-project.html)
+This Repo Contains Accelerator Wrapper IP which should be used at the top-level repository to stitch your accelerator together with.
diff --git a/flist/ahb_ip.flist b/flist/ahb_ip.flist
deleted file mode 100644
index 693b870c766dd2cbdac382f038435ee216a7bef9..0000000000000000000000000000000000000000
--- a/flist/ahb_ip.flist
+++ /dev/null
@@ -1,28 +0,0 @@
-//-----------------------------------------------------------------------------
-// Accelerator Wrapper CMSDK Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Accelerator CMSDK Wrapper Components
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= Accelerator Module search path =============
--y $(ACC_WRAPPER_DIR)/hdl/verif/
--y $(ACC_WRAPPER_DIR)/hdl/verif/cmsdk
-+incdir+$(ACC_WRAPPER_DIR)/hdl/verif/
-+incdir+$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/
-
-$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_filereadcore.v
-$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_fileread_funnel.v
-$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_fileread_master32.v
-$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_default_slave.v
-$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_slave_mux.v
\ No newline at end of file
diff --git a/flist/accelerator_wrapper.flist b/flist/wrapper_ip.flist
similarity index 83%
rename from flist/accelerator_wrapper.flist
rename to flist/wrapper_ip.flist
index 13231946466cb221a62ea30fddc0a9f6632b1c00..94c2907d7c62fe3dd3ff0c2d8cb68932ce8d87e3 100644
--- a/flist/accelerator_wrapper.flist
+++ b/flist/wrapper_ip.flist
@@ -9,7 +9,7 @@
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Accelerator Wrapper example
+// Abstract : Verilog Command File for Accelerator Wrapper IP
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
@@ -20,7 +20,6 @@
+incdir+$(ACC_WRAPPER_DIR)/hdl/src/
$(ACC_WRAPPER_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
-$(ACC_WRAPPER_DIR)/hdl/src/wrapper_ahb_to_vr_interface.sv
+$(ACC_WRAPPER_DIR)/hdl/src/wrapper_ahb_vr_interface.sv
$(ACC_WRAPPER_DIR)/hdl/src/wrapper_packet_construct.sv
$(ACC_WRAPPER_DIR)/hdl/src/wrapper_packet_deconstruct.sv
-$(ACC_WRAPPER_DIR)/hdl/src/wrapper_sha256_hashing_stream.sv
\ No newline at end of file
diff --git a/hdl/.DS_Store b/hdl/.DS_Store
index 7b2e008b137c260776ee8d5c120f761ad9efbe4e..5008ddfcf53c02e82d7eee2e57c38e5672ef89f6 100644
Binary files a/hdl/.DS_Store and b/hdl/.DS_Store differ
diff --git a/hdl/src/wrapper_ahb_to_vr_interface.sv b/hdl/src/wrapper_ahb_vr_interface.sv
similarity index 99%
rename from hdl/src/wrapper_ahb_to_vr_interface.sv
rename to hdl/src/wrapper_ahb_vr_interface.sv
index 71e2f6e875e425007f25bef9a4508515fd0fd8be..00595d37518f3c97f2a681d1472bea6591fa4abd 100644
--- a/hdl/src/wrapper_ahb_to_vr_interface.sv
+++ b/hdl/src/wrapper_ahb_vr_interface.sv
@@ -35,7 +35,7 @@
// Abstract : AHB-lite example slave interface module. Transfer AHB-Lite BUS protocol to
// simple register read write protocol
//-----------------------------------------------------------------------------
-module wrapper_ahb_to_vr_interface #(
+module wrapper_ahb_vr_interface #(
//parameter for address width
parameter ADDRWIDTH=12)
(
diff --git a/hdl/src/wrapper_sha256_hashing_stream.sv b/hdl/src/wrapper_sha256_hashing_stream.sv
deleted file mode 100644
index 81ff2a9d27536140b1e3a1160c0cbee344b42c9d..0000000000000000000000000000000000000000
--- a/hdl/src/wrapper_sha256_hashing_stream.sv
+++ /dev/null
@@ -1,235 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Accelerator Wrapper for Hashing Stream
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : AHB-lite example slave, support 4 32-bit register read and write,
-// each register can be accessed by byte, half word or word.
-// The example slave always output ready and OKAY response to the master
-//-----------------------------------------------------------------------------
-
-module wrapper_sha256_hashing_stream #(
- parameter ADDRWIDTH=12
- ) (
- input logic HCLK, // Clock
- input logic HRESETn, // Reset
-
- // AHB connection to Initiator
- input logic HSELS,
- input logic [ADDRWIDTH-1:0] HADDRS,
- input logic [1:0] HTRANSS,
- input logic [2:0] HSIZES,
- input logic HWRITES,
- input logic HREADYS,
- input logic [31:0] HWDATAS,
-
- output logic HREADYOUTS,
- output logic HRESPS,
- output logic [31:0] HRDATAS
- );
-
- // ----------------------------------------
- // Internal wires declarations
-
- // Register module interface signals
- logic [ADDRWIDTH-1:0] in_buf_addr;
- logic in_buf_read_en;
- logic in_buf_write_en;
- logic [3:0] in_buf_byte_strobe;
- logic [31:0] in_buf_wdata;
- logic [31:0] in_buf_rdata;
-
- // Input Port Wire Declarations
- logic [ADDRWIDTH-2:0] input_addr;
- logic input_read_en;
- logic input_write_en;
- logic [3:0] input_byte_strobe;
- logic [31:0] input_wdata;
- logic [31:0] input_rdata;
- logic input_wready;
- logic input_rready;
-
- // Output Port Wire Declarations
- logic [ADDRWIDTH-2:0] output_addr;
- logic output_read_en;
- logic output_write_en;
- logic [3:0] output_byte_strobe;
- logic [31:0] output_wdata;
- logic [31:0] output_rdata;
- logic output_wready;
- logic output_rready;
-
- // Internal Wiring
- // Input Packet Wires
- logic [511:0] in_packet;
- logic in_packet_last;
- logic in_packet_valid;
- logic in_packet_ready;
-
- // Output Packet Wires
- logic [255:0] out_packet;
- logic out_packet_last;
- logic out_packet_valid;
- logic out_packet_ready;
-
- // Configuration Tie Off
- logic [63:0] cfg_size;
- logic [1:0] cfg_scheme;
- logic cfg_last;
- logic cfg_valid;
- logic cfg_ready;
-
- assign cfg_size = 64'd512;
- assign cfg_scheme = 2'd0;
- assign cfg_last = 1'b1;
- assign cfg_valid = 1'b1;
-
- //-----------------------------------------------------------
- // Module logic start
- //----------------------------------------------------------
-
- // Interface block to convert AHB transfers to Register transfers to engine input/output channels
- // engine Input/Output Channels
- wrapper_ahb_to_vr_interface #(
- ADDRWIDTH
- ) u_wrapper_ahb_interface (
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .hsels (HSELS),
- .haddrs (HADDRS),
- .htranss (HTRANSS),
- .hsizes (HSIZES),
- .hwrites (HWRITES),
- .hreadys (HREADYS),
- .hwdatas (HWDATAS),
-
- .hreadyouts (HREADYOUTS),
- .hresps (HRESPS),
- .hrdatas (HRDATAS),
-
- // Register interface - Accelerator Engine Input
- .input_addr (input_addr),
- .input_read_en (input_read_en),
- .input_write_en (input_write_en),
- .input_byte_strobe (input_byte_strobe),
- .input_wdata (input_wdata),
- .input_rdata (input_rdata),
- .input_wready (input_wready),
- .input_rready (input_rready),
-
- // Register interface - Accelerator Engine Output
- .output_addr (output_addr),
- .output_read_en (output_read_en),
- .output_write_en (output_write_en),
- .output_byte_strobe (output_byte_strobe),
- .output_wdata (output_wdata),
- .output_rdata (output_rdata),
- .output_wready (output_wready),
- .output_rready (output_rready)
- );
-
- wrapper_packet_construct #(
- (ADDRWIDTH - 1), // Only half address map allocated to this device
- 512 // Packet Width
- ) u_wrapper_packet_construct (
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // Register interface
- .addr (input_addr),
- .read_en (input_read_en),
- .write_en (input_write_en),
- .byte_strobe (input_byte_strobe),
- .wdata (input_wdata),
- .rdata (input_rdata),
- .wready (input_wready),
- .rready (input_rready),
-
- // Valid/Ready Interface
- .packet_data (in_packet),
- .packet_data_last (in_packet_last),
- .packet_data_valid (in_packet_valid),
- .packet_data_ready (in_packet_ready)
- );
-
- sha256_hashing_stream u_sha256_hashing_stream (
- .clk (HCLK),
- .nrst (HRESETn),
- .en (1'b1),
- .sync_rst (1'b0),
-
- // Data in Channel
- .data_in (in_packet),
- .data_in_valid (in_packet_valid),
- .data_in_ready (in_packet_ready),
- .data_in_last (in_packet_last),
-
- // Config In Channel
- .cfg_size (cfg_size),
- .cfg_scheme (cfg_scheme),
- .cfg_last (cfg_last),
- .cfg_valid (cfg_valid),
- .cfg_ready (cfg_ready),
-
- // Data Out Channel
- .data_out (out_packet),
- .data_out_last (out_packet_last),
- .data_out_valid (out_packet_valid),
- .data_out_ready (out_packet_ready)
- );
-
- wrapper_packet_deconstruct #(
- (ADDRWIDTH - 1), // Only half address map allocated to this device
- 256 // Ouptut Packet WIdth
- ) u_wrapper_packet_deconstruct (
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // Register interface
- .addr (output_addr),
- .read_en (output_read_en),
- .write_en (output_write_en),
- .byte_strobe (output_byte_strobe),
- .wdata (output_wdata),
- .rdata (output_rdata),
- .wready (output_wready),
- .rready (output_rready),
-
- // Valid/Ready Interface
- .packet_data (out_packet),
- .packet_data_last (out_packet_last),
- .packet_data_valid (out_packet_valid),
- .packet_data_ready (out_packet_ready)
- );
-
-endmodule
\ No newline at end of file
diff --git a/hdl/src/wrapper_vr_loopback.sv b/hdl/src/wrapper_vr_loopback.sv
deleted file mode 100644
index 49bf64eef7919e4c95ada1d386e95fa0cf73e208..0000000000000000000000000000000000000000
--- a/hdl/src/wrapper_vr_loopback.sv
+++ /dev/null
@@ -1,251 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Wrapper Source
-// - Valid-Ready Loopback example connecting packet constructor to deconstructor
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : AHB-lite example slave, support 4 32-bit register read and write,
-// each register can be accessed by byte, half word or word.
-// The example slave always output ready and OKAY response to the master
-//-----------------------------------------------------------------------------
-`timescale 1ns/1ns
-`include "wrapper_packet_construct.sv"
-`include "wrapper_packet_deconstruct.sv"
-`include "wrapper_ahb_interface.sv"
-
-module wrapper_vr_loopback #(
- parameter ADDRWIDTH=12 // Peripheral Address Width
- )(
- input logic HCLK, // Clock
- input logic HRESETn, // Reset
-
- // AHB connection to Initiator
- input logic HSELS,
- input logic [ADDRWIDTH-1:0] HADDRS,
- input logic [1:0] HTRANSS,
- input logic [2:0] HSIZES,
- input logic HWRITES,
- input logic HREADYS,
- input logic [31:0] HWDATAS,
-
- output logic HREADYOUTS,
- output logic HRESPS,
- output logic [31:0] HRDATAS
- );
-
-
- // ----------------------------------------
- // Internal wires declarations
-
- // Register module interface signals
- logic [ADDRWIDTH-1:0] in_buf_addr;
- logic in_buf_read_en;
- logic in_buf_write_en;
- logic [3:0] in_buf_byte_strobe;
- logic [31:0] in_buf_wdata;
- logic [31:0] in_buf_rdata;
-
- // Input Port Wire Declarations
- logic [ADDRWIDTH-2:0] input_addr;
- logic input_read_en;
- logic input_write_en;
- logic [3:0] input_byte_strobe;
- logic [31:0] input_wdata;
- logic [31:0] input_rdata;
- logic input_wready;
- logic input_rready;
-
- // Output Port Wire Declarations
- logic [ADDRWIDTH-2:0] output_addr;
- logic output_read_en;
- logic output_write_en;
- logic [3:0] output_byte_strobe;
- logic [31:0] output_wdata;
- logic [31:0] output_rdata;
- logic output_wready;
- logic output_rready;
-
- // Internal Wiring
- logic [511:0] packet;
- logic packet_last;
- logic packet_valid;
- logic packet_ready;
-
- //-----------------------------------------------------------
- // Module logic start
- //----------------------------------------------------------
-
- // Interface block to convert AHB transfers to Register transfers to engine input/output channels
- // engine Input/Output Channels
- wrapper_ahb_to_vr_interface #(
- ADDRWIDTH
- ) u_wrapper_ahb_interface (
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .hsels (HSELS),
- .haddrs (HADDRS),
- .htranss (HTRANSS),
- .hsizes (HSIZES),
- .hwrites (HWRITES),
- .hreadys (HREADYS),
- .hwdatas (HWDATAS),
-
- .hreadyouts (HREADYOUTS),
- .hresps (HRESPS),
- .hrdatas (HRDATAS),
-
- // Register interface - Accelerator Engine Input
- .input_addr (input_addr),
- .input_read_en (input_read_en),
- .input_write_en (input_write_en),
- .input_byte_strobe (input_byte_strobe),
- .input_wdata (input_wdata),
- .input_rdata (input_rdata),
- .input_wready (input_wready),
- .input_rready (input_rready),
-
- // Register interface - Accelerator Engine Output
- .output_addr (output_addr),
- .output_read_en (output_read_en),
- .output_write_en (output_write_en),
- .output_byte_strobe (output_byte_strobe),
- .output_wdata (output_wdata),
- .output_rdata (output_rdata),
- .output_wready (output_wready),
- .output_rready (output_rready)
- );
-
- wrapper_packet_construct #(
- (ADDRWIDTH - 1), // Only half address map allocated to this device
- 512 // Packet Width
- ) u_wrapper_packet_construct (
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // Register interface
- .addr (input_addr),
- .read_en (input_read_en),
- .write_en (input_write_en),
- .byte_strobe (input_byte_strobe),
- .wdata (input_wdata),
- .rdata (input_rdata),
- .wready (input_wready),
- .rready (input_rready),
-
- // Valid/Ready Interface
- .packet_data (packet),
- .packet_data_last (packet_last),
- .packet_data_valid (packet_valid),
- .packet_data_ready (packet_ready)
- );
-
- wrapper_packet_deconstruct #(
- (ADDRWIDTH - 1), // Only half address map allocated to this device
- 512 // Ouptut Packet WIdth
- ) u_wrapper_packet_deconstruct (
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // Register interface
- .addr (output_addr),
- .read_en (output_read_en),
- .write_en (output_write_en),
- .byte_strobe (output_byte_strobe),
- .wdata (output_wdata),
- .rdata (output_rdata),
- .wready (output_wready),
- .rready (output_rready),
-
- // Valid/Ready Interface
- .packet_data (packet),
- .packet_data_last (packet_last),
- .packet_data_valid (packet_valid),
- .packet_data_ready (packet_ready)
- );
-
- //-----------------------------------------------------------
- //Module logic end
- //----------------------------------------------------------
-
-`ifdef ARM_AHB_ASSERT_ON
-
- `include "std_ovl_defines.h"
- // ------------------------------------------------------------
- // Assertions
- // ------------------------------------------------------------
-
- logic ovl_trans_req = HREADYS & HSELS & HTRANSS[1];
-
- // Check the reg_write_en signal generated
- assert_next
- #(`OVL_ERROR, 1,1,0,
- `OVL_ASSERT,
- "Error! register write signal was not generated! "
- )
- u_ovl_ahb_eg_slave_reg_write
- (.clk ( HCLK ),
- .reset_n (HRESETn),
- .start_event ((ovl_trans_req & HWRITES)),
- .test_expr (reg_write_en == 1'b1)
- );
-
-
- // Check the reg_read_en signal generated
- assert_next
- #(`OVL_ERROR, 1,1,0,
- `OVL_ASSERT,
- "Error! register read signal was not generated! "
- )
- u_ovl_ahb_eg_slave_reg_read
- (.clk ( HCLK ),
- .reset_n (HRESETn),
- .start_event ((ovl_trans_req & (~HWRITES))),
- .test_expr (reg_read_en == 1'b1)
- );
-
-
-
- // Check register read and write operation won't assert at the same cycle
- assert_never
- #(`OVL_ERROR,
- `OVL_ASSERT,
- "Error! register read and write active at the same cycle!")
- u_ovl_ahb_eg_slave_rd_wr_illegal
- (.clk(HCLK),
- .reset_n(HRESETn),
- .test_expr((reg_write_en & reg_read_en))
- );
-
-`endif
-
-endmodule
\ No newline at end of file
diff --git a/hdl/verif/.DS_Store b/hdl/verif/.DS_Store
deleted file mode 100644
index 5008ddfcf53c02e82d7eee2e57c38e5672ef89f6..0000000000000000000000000000000000000000
Binary files a/hdl/verif/.DS_Store and /dev/null differ
diff --git a/hdl/verif/cmsdk/cmsdk_ahb_default_slave.v b/hdl/verif/cmsdk/cmsdk_ahb_default_slave.v
deleted file mode 100644
index 39b45ac94d7b8f416131fdcd924aa20e96dfc0c9..0000000000000000000000000000000000000000
--- a/hdl/verif/cmsdk/cmsdk_ahb_default_slave.v
+++ /dev/null
@@ -1,141 +0,0 @@
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : AHB-Lite Default Slave
-//-----------------------------------------------------------------------------
-//
-// Returns an error response when selected for a transfer
-//
-
-module cmsdk_ahb_default_slave (
- // Inputs
- input wire HCLK, // Clock
- input wire HRESETn, // Reset
- input wire HSEL, // Slave select
- input wire [1:0] HTRANS, // Transfer type
- input wire HREADY, // System ready
-
- // Outputs
- output wire HREADYOUT, // Slave ready
- output wire HRESP); // Slave response
-
-//
-// Start of main code
-//
-
-// Internal signals
-wire trans_req; // Transfer Request
-reg [1:0] resp_state; // Current FSM state for two-cycle error response
-wire [1:0] next_state; // Next FSM state
-
-// Transfer address phase completes
-assign trans_req = HSEL & HTRANS[1] & HREADY;
-
-// Generate next state for the FSM.
-// Bit 0 is connected to HREADYOUT and bit 1 is connected to HRESP,
-// so the state encodings are:
-// 01 - Idle
-// 10 - 1st cycle of error response
-// 11 - 2nd cycle of error response
-assign next_state = { trans_req | (~resp_state[0]),
- ~trans_req };
-
-// Registering FSM state
-always @(posedge HCLK or negedge HRESETn)
- if (~HRESETn)
- resp_state <= 2'b01; // ensure HREADYOUT is HIGH at reset
- else
- resp_state <= next_state;
-
-// Connect to output
-assign HREADYOUT = resp_state[0];
-assign HRESP = resp_state[1];
-
-`ifdef ARM_AHB_ASSERT_ON
-
- // ------------------------------------------------------------
- // Assertions
- // ------------------------------------------------------------
- `include "std_ovl_defines.h"
- reg ovl_last_hreadyout;
- reg ovl_last_hsel;
- reg [1:0] ovl_last_htrans;
- reg ovl_last_hready;
-
- always @(posedge HCLK or negedge HRESETn)
- begin
- if (~HRESETn)
- begin
- ovl_last_hreadyout <= 1'b1;
- ovl_last_hsel <= 1'b0;
- ovl_last_htrans <= 2'b00;
- ovl_last_hready <= 1'b1;
- end
- else
- begin
- ovl_last_hreadyout <= HREADYOUT;
- ovl_last_hsel <= HSEL;
- ovl_last_htrans <= HTRANS;
- ovl_last_hready <= HREADY;
- end
- end
-
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "If HREADYOUT is 0, HRESP must be high")
- u_ovl_error_response_check_1
- (.clk(HCLK), .reset_n(HRESETn),
- .antecedent_expr(~HREADYOUT),
- .consequent_expr(HRESP)
- );
-
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "If in last cycle HREADYOUT is 0, this cycle both HRESP and HREADYOUT")
- u_ovl_error_response_check_2
- (.clk(HCLK), .reset_n(HRESETn),
- .antecedent_expr(~ovl_last_hreadyout),
- .consequent_expr(HRESP & HREADYOUT)
- );
-
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "If device is not selected, or if transfer is idle/busy, response must be OKAY")
- u_ovl_error_fault_check_1
- (.clk(HCLK), .reset_n(HRESETn),
- .antecedent_expr(~(ovl_last_hsel & ovl_last_htrans[1]) & ovl_last_hready),
- .consequent_expr((~HRESP) & HREADYOUT)
- );
-
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "If device is selected, and if transfer is nseq/seq, response must be ERROR")
- u_ovl_error_fault_check_2
- (.clk(HCLK), .reset_n(HRESETn),
- .antecedent_expr(ovl_last_hsel & ovl_last_htrans[1] & ovl_last_hready),
- .consequent_expr(HRESP & (~HREADYOUT))
- );
-
-`endif
-
-endmodule
diff --git a/hdl/verif/cmsdk/cmsdk_ahb_fileread_funnel.v b/hdl/verif/cmsdk/cmsdk_ahb_fileread_funnel.v
deleted file mode 100644
index 35bc30f7f29f202bc5ce3e0a47c73273808b7040..0000000000000000000000000000000000000000
--- a/hdl/verif/cmsdk/cmsdk_ahb_fileread_funnel.v
+++ /dev/null
@@ -1,90 +0,0 @@
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Convert 64-bit bus from ahb_fileread_core to 32-bit
-//-----------------------------------------------------------------------------
-// ----------------------------------------------------------------------------
-// Purpose : A data bus multiplexor, used to connect a 32 bit slave
-// to a 64 bit bus.
-// Supports transfers up to 32 bit in size.
-// --========================================================================--
-
-module cmsdk_ahb_fileread_funnel (
- // Clock and Reset
- input wire HCLK,
- input wire HRESETn,
- // Interface to AHB
- input wire HADDR2S,
- input wire [63:0] HWDATAS,
- input wire HREADYS,
- output wire [63:0] HRDATAS,
- // Interface to slave
- output reg [31:0] HWDATAM,
- input wire [31:0] HRDATAM);
-
-// -----------------------------------------------------------------------------
-// Signal Declarations
-// -----------------------------------------------------------------------------
-
-reg haddr2s_reg; // Delayed version of address bit2
-
-// =============================================================================
-// Beginning of main verilog code
-// =============================================================================
-
-//------------------------------------------------------------------------------
-// Generate Delayed version of HADDR2S
-//------------------------------------------------------------------------------
-always@(posedge HCLK or negedge HRESETn)
- begin : p_haddr2s_reg
- if (HRESETn == 1'b0)
- haddr2s_reg <= 1'b0;
- else
- begin
- if (HREADYS == 1'b1)
- haddr2s_reg <= HADDR2S;
- end
- end // block: p_haddr2s_reg
-
-// -----------------------------------------------------------------------------
-// Write Data MUX
-// -----------------------------------------------------------------------------
-// Note: To support Big-Endian systems the polarity of the HWDATAM MUX should be
-// reversed.
-
-always@(haddr2s_reg or HWDATAS)
- begin : p_write_mux
- if (haddr2s_reg == 1'b0)
- HWDATAM = HWDATAS[31:0];
- else
- HWDATAM = HWDATAS[63:32];
- end // block: p_write_mux
-
-// -----------------------------------------------------------------------------
-// Read Data bus
-// -----------------------------------------------------------------------------
- assign HRDATAS = {HRDATAM,HRDATAM};
-
-
-endmodule
-// --================================= End ===================================--
diff --git a/hdl/verif/cmsdk/cmsdk_ahb_fileread_master32.v b/hdl/verif/cmsdk/cmsdk_ahb_fileread_master32.v
deleted file mode 100644
index b3fbecaba20d10d309d7e27b9b95fe87a4b7d513..0000000000000000000000000000000000000000
--- a/hdl/verif/cmsdk/cmsdk_ahb_fileread_master32.v
+++ /dev/null
@@ -1,134 +0,0 @@
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : 32-bit AHB File Reader Bus Master
-//-----------------------------------------------------------------------------
-// ----------------------------------------------------------------------------
-// Purpose : This entity ties together the sub blocks that
-// form the 32-bit File Reader Bus Master, namely an
-// AHB-Lite File Reader Core and a bus funnel .
-// --========================================================================--
-// Note
-// This top level file converts AHB Lite extension
-// signals in ARM1136 to sideband signals used in
-// Cortex-M3/M4
-// --========================================================================--
-
-module cmsdk_ahb_fileread_master32 #(
-
- parameter InputFileName = "filestim.m2d", // stimulus data file name
- parameter MessageTag = "FileReader:", // tag on each FileReader message
- parameter StimArraySize = 5000) // stimulus data array size:
- // should be large enough to hold
- // entire stimulus data file
- (
- // system ports
- input wire HCLK, // system clock
- input wire HRESETn, // system reset
-
- // AHB ports
- input wire HREADY, // slave ready signal
- input wire HRESP, // slave response bus
- input wire [31:0] HRDATA, // data, slave to master
- input wire EXRESP, // Exclusive response (tie low if not used)
-
- output wire [1:0] HTRANS, // transfer type
- output wire [2:0] HBURST, // burst type
- output wire [3:0] HPROT, // transfer protection
- output wire EXREQ, // Exclusive access request
- output wire [1:0] MEMATTR, // Memory attribute
- output wire [2:0] HSIZE, // transfer size
- output wire HWRITE, // transfer direction
- output wire HMASTLOCK, // transfer is locked
- output wire [31:0] HADDR, // transfer address
- output wire [31:0] HWDATA, // data, master to slave
-
- output wire [31:0] LINENUM); // line number in stimulus file
-
- // Internal AHB-Lite Bus Signals
- wire [2:0] hresp_core; // slave response
- wire [63:0] hrdata_core; // data from slave to master
- wire [31:0] haddr_core; // transfer address
- wire [63:0] hwdata_core; // data from master to slave
- wire [5:0] hprot_core; // transfer protection
-
-//------------------------------------------------------------------------------
-// structural
-//------------------------------------------------------------------------------
-
-// Instance of AHB-Lite File Reader connected to internal AHB-Lite system
- cmsdk_ahb_filereadcore
- #(.input_filename(InputFileName),
- .message_tag(MessageTag),
- .stim_array_size(StimArraySize))
- u_ahb_filereadcore (
-
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- .HREADY (HREADY),
- .HRESP (hresp_core),
- .HRDATA (hrdata_core),
-
- .HTRANS (HTRANS),
- .HBURST (HBURST),
- .HPROT (hprot_core),
- .HSIZE (HSIZE),
- .HWRITE (HWRITE),
- .HMASTLOCK (HMASTLOCK),
- .HADDR (haddr_core),
- .HWDATA (hwdata_core),
- .HUNALIGN (),
- .HBSTRB (),
- .LINENUM (LINENUM)
- );
-
- // Instance of a Funnel to translate the 64-bit AHB-Lite data bus to 32-bit.
- cmsdk_ahb_fileread_funnel u_ahb_fileread_funnel (
-
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- // 64-bit interface to AHB
- .HREADYS (HREADY),
- .HADDR2S (haddr_core[2]),
- .HWDATAS (hwdata_core),
- .HRDATAS (hrdata_core),
-
- // 32-bit interface to slave
- .HWDATAM (HWDATA),
- .HRDATAM (HRDATA)
- );
-
-
- // Convert internal versions of port signals
- assign HADDR = haddr_core; // Drive port with internal signal
- assign HPROT = hprot_core[3:0];
- assign EXREQ = hprot_core[5];
- assign MEMATTR = {1'b0, hprot_core[4]};
-
- assign hresp_core = {EXRESP, 1'b0,HRESP}; // Drive unused bit of hresp_core
-
-endmodule
-
-// --================================ End ==================================--
diff --git a/hdl/verif/cmsdk/cmsdk_ahb_filereadcore.v b/hdl/verif/cmsdk/cmsdk_ahb_filereadcore.v
deleted file mode 100644
index 91855da1a4554891d2b62eab0bb1c39d4c3359a5..0000000000000000000000000000000000000000
--- a/hdl/verif/cmsdk/cmsdk_ahb_filereadcore.v
+++ /dev/null
@@ -1,1488 +0,0 @@
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Core module for AHB Lite File Reader Bus Master
-//-----------------------------------------------------------------------------
-// ---------------------------------------------------------------------------
-// Purpose : The AHB-Lite file reader bus master reads in a file
-// and decodes it into AHB-Lite (with ARM11 extensions)
-// bus transfers.
-// --=======================================================================--
-
-module cmsdk_ahb_filereadcore #(
- // Parameters
- parameter input_filename = "filestim.m2d", // stimulus data file name
- parameter message_tag = "FileReader:", // tag on each FileReader message
- parameter stim_array_size = 5000) // array size, should be large enough to hold
- // entire stimulus data file
- (
- input wire HCLK, // system clock
- input wire HRESETn, // system reset
-
- input wire HREADY, // slave ready signal
- input wire [2:0] HRESP, // slave response (tie HRESP[2] low for non-ARM11)
- input wire [63:0] HRDATA, // data from slave to master
- output wire [1:0] HTRANS, // transfer type
- output wire [2:0] HBURST, // burst type
- output wire [5:0] HPROT, // protection (HPROT[5:4] unconnected for non-ARM11)
- output wire [2:0] HSIZE, // transfer size
- output wire HWRITE, // transfer direction
- output wire HMASTLOCK, // transfer is a locked transfer
- output wire [31:0] HADDR, // transfer address
- output wire [63:0] HWDATA, // data from master to slave
- output wire HUNALIGN, // transfer is unaligned (unconnected for non-ARM11)
- output wire [7:0] HBSTRB, // byte lane strobes (unconnected for non-ARM11)
-
- output wire [31:0] LINENUM); // Line number in stimulus file
-
- //----------------------------------------------------------------------------
- // Constant declarations
- //----------------------------------------------------------------------------
-
- `define ARM_FRBM_UNDEF8 8'hx
- `define ARM_FRBM_LOW32 {32{1'b0}}
-
- // Sign-on banner
- `define ARM_FRBM_SIGN_ON_MSG1 " ************************************************"
- `define ARM_FRBM_SIGN_ON_MSG2 " **** ARM AMBA Design Kit File Reader Master"
- `define ARM_FRBM_SIGN_ON_MSG3 " **** (C) ARM Limited 2000-2002"
- `define ARM_FRBM_SIGN_ON_MSG4 " ************************************************"
-
- // Information message
- `define ARM_FRBM_OPENFILE_MSG "%d %s Reading stimulus file %s"
-
- // Error messages
- `define ARM_FRBM_SLAVE_ERR_MSG1 "%d %s #ERROR# Expected Okay response was not received from Slave."
- `define ARM_FRBM_SLAVE_ERR_MSG2 "%d %s #ERROR# Expected Error response was not received from Slave."
- `define ARM_FRBM_SLAVE_XFAIL_MSG1 "%d %s #ERROR# Slave responded with an unexpected XFAIL."
- `define ARM_FRBM_SLAVE_XFAIL_MSG2 "%d %s #ERROR# Expected XFAIL response was not received from Slave."
- `define ARM_FRBM_DATA_ERR_MSG "%d %s #ERROR# Data received did not match expectation."
- `define ARM_FRBM_POLL_ERR_MSG "%d %s #ERROR# Poll command timed out after %d repeats."
- `define ARM_FRBM_CMD_MSG "%d %s #ERROR# Unknown command value in file."
-
-
- `define ARM_FRBM_ADDRESS_MSG " Address = %h"
- `define ARM_FRBM_ACTUAL_DATA " Actual data = %h"
- `define ARM_FRBM_EXPECTED_DATA " Expected data = %h"
- `define ARM_FRBM_DATA_MASK " Mask = %h"
- `define ARM_FRBM_LINE_NUM " Stimulus Line: %d"
-
- // Inent messages because of the length of the time variable
- `define ARM_FRBM_INDENT " "
-
- // End of Simulation Summary messages
- `define ARM_FRBM_QUIT_MSG "Simulation Quit requested."
- `define ARM_FRBM_END_MSG "Stimulus completed."
-
- `define ARM_FRBM_SUMMARY_HEADER " ******* SIMULATION SUMMARY *******"
- `define ARM_FRBM_SUMMARY_FOOTER " **********************************"
- `define ARM_FRBM_SUMMARY_DATA " ** Data Mismatches :%d"
- `define ARM_FRBM_SUMMARY_POLL " ** Poll timeouts :%d"
- `define ARM_FRBM_SUMMARY_SLAVE " ** Response Mismatches :%d"
-
-
- // HTRANS signal encoding
- `define ARM_FRBM_TRN_IDLE 2'b00 // Idle transfer
- `define ARM_FRBM_TRN_BUSY 2'b01 // Busy transfer
- `define ARM_FRBM_TRN_NONSEQ 2'b10 // Non-sequential
- `define ARM_FRBM_TRN_SEQ 2'b11 // Sequential
-
- // HSIZE signal encoding
- `define ARM_FRBM_SZ_BYTE 3'b000 // 8-bit access
- `define ARM_FRBM_SZ_HALF 3'b001 // 16-bit access
- `define ARM_FRBM_SZ_WORD 3'b010 // 32-bit access
- `define ARM_FRBM_SZ_DWORD 3'b011 // 64-bit access
-
- // HBURST signal encoding
- `define ARM_FRBM_BUR_SINGLE 3'b000 // Single
- `define ARM_FRBM_BUR_INCR 3'b001 // Incrementing
- `define ARM_FRBM_BUR_WRAP4 3'b010 // 4-beat wrap
- `define ARM_FRBM_BUR_INCR4 3'b011 // 4-beat incr
- `define ARM_FRBM_BUR_WRAP8 3'b100 // 8-beat wrap
- `define ARM_FRBM_BUR_INCR8 3'b101 // 8-beat incr
- `define ARM_FRBM_BUR_WRAP16 3'b110 // 16-beat wrap
- `define ARM_FRBM_BUR_INCR16 3'b111 // 16-beat incr
-
- // HRESP signal encoding
- `define ARM_FRBM_RSP_OKAY 3'b000 // Okay response
- `define ARM_FRBM_RSP_ERROR 3'b001 // Error response
- `define ARM_FRBM_RSP_RETRY 3'b010 // Retry response
- `define ARM_FRBM_RSP_SPLIT 3'b011 // Split response
- `define ARM_FRBM_RSP_XFAIL 3'b100 // XFail response
-
- // Wrap boundary limits
- `define ARM_FRBM_NOBOUND 3'b000
- `define ARM_FRBM_BOUND4 3'b001
- `define ARM_FRBM_BOUND8 3'b010
- `define ARM_FRBM_BOUND16 3'b011
- `define ARM_FRBM_BOUND32 3'b100
- `define ARM_FRBM_BOUND64 3'b101
- `define ARM_FRBM_BOUND128 3'b110
-
- // Commands
- `define ARM_FRBM_CMD_WRITE 8'b00000000
- `define ARM_FRBM_CMD_READ 8'b00010000
- `define ARM_FRBM_CMD_SEQ 8'b00100000
- `define ARM_FRBM_CMD_BUSY 8'b00110000
- `define ARM_FRBM_CMD_IDLE 8'b01000000
- `define ARM_FRBM_CMD_POLL 8'b01010000
- `define ARM_FRBM_CMD_LOOP 8'b01100000
- `define ARM_FRBM_CMD_COMM 8'b01110000
- `define ARM_FRBM_CMD_QUIT 8'b10000000
-
- // Poll command states
- `define ARM_FRBM_ST_NO_POLL 2'b00
- `define ARM_FRBM_ST_POLL_READ 2'b01
- `define ARM_FRBM_ST_POLL_TEST 2'b10
-
- // Error responses
- `define ARM_FRBM_ERR_OKAY 2'b00
- `define ARM_FRBM_ERR_CONT 2'b01
- `define ARM_FRBM_ERR_CANC 2'b10
- `define ARM_FRBM_ERR_XFAIL 2'b11
-
-//---------------------------------------------------------------------------
-// Signal declarations
-//---------------------------------------------------------------------------
-
- // File read control
- wire rd_next;
-
- // Signals from file data
- reg [7:0] vec_cmd; // command
- reg [31:0] vec_addr;
- reg [63:0] vec_data;
- reg [63:0] vec_data_mask;
- reg [2:0] vec_burst;
- reg [2:0] vec_size;
- reg vec_lock;
- reg [5:0] vec_prot;
- reg vec_dir;
- reg [1:0] err_resp;
- reg wait_rdy;
- reg [7:0] vec_bstrb;
- reg unalign;
- reg use_bstrb_flag;
-
- // Registered signals
- reg [7:0] cmd_reg;
- reg [63:0] data_reg;
- reg [63:0] mask_reg;
- reg [2:0] size_reg;
- reg [1:0] err_resp_reg;
-
- // Address calculation signals
- wire non_zero;
- reg [3:0] add_value;
- reg [2:0] align_mask;
- reg [2:0] boundary;
- wire [31:0] incr_addr;
- reg [31:0] wrapped_addr;
- wire [31:0] aligned_addr;
- wire [2:0] aligned_addr_l;
-
- // Error signal
- wire data_err;
-
- // Internal signals
- wire [31:0] i_haddr;
- wire [63:0] i_hwdata;
- reg [1:0] i_htrans;
- wire i_hwrite;
- reg [7:0] i_hbstrb;
-
- // Registered internal signals
- reg [31:0] haddr_reg;
- reg [63:0] hwdata_reg;
- reg [1:0] htrans_reg;
- reg hwrite_reg;
-
- // Poll command state machine
- reg [1:0] next_poll_state;
- reg [1:0] poll_state;
-
- // Compared read data
- wire [63:0] mask;
- wire [63:0] bstrb_mask;
- reg [63:0] data_compare;
-
- // Poll timeout signals
- reg [31:0] timeout; // timeout value for poll
- reg [31:0] timeout_reg; // registered timeout value
- reg [31:0] poll_count; // poll counter
- reg [31:0] next_poll_count; // next poll count
-
-//------------------------------------------------------------------------------
-// START OF BEHAVIOURAL CODE
-//------------------------------------------------------------------------------
-
- // Stimulus reading signals
- reg [31:0] file_array [0:stim_array_size]; // stimulus file data
- reg [31:0] file_array_tmp; // current value in stimulus file
- integer array_ptr; // pointer to stimulus file data
-
- integer stim_line_num; // input stimulus line number counter
- integer stim_line_reg; // stim line counter registered into data phase
-
- // Stimulus end signals
- reg stim_end; // signals end of input stimulus file
- reg stim_end_data; // stim_end registered into data phase
- reg stim_end_data_reg; // registered stim_end_data
-
- reg skip_seq; // signals to skip end of sequence upon Error
-
- reg banner_done; // true if sign-on banner has been displayed
-
- // Error counters for end of simulation summary
- integer data_err_cnt; // read data errors
- integer slave_resp_cnt; // unexpected slave ERROR responses
- integer poll_err_cnt; // Poll timeouts
-
- reg [7:0] comm_words_hex [0:79]; // comment array
- reg [4:0] comm_word_num; // number of words in comment command
-
-
-//------------------------------------------------------------------------------
-// Print Comment command string to simulation window
-//------------------------------------------------------------------------------
-// The fileconv script converts the comment into ASCII hex values this
-// task prints the string from the comm_words_hex array.
-
- task tsk_simulation_comment; // no input or return values
- integer c_index; // character index
- begin
- $write ("%d %s ", $time, message_tag);
-
- // loop through the characters in the array and print
- for (c_index = 0; c_index < (comm_word_num*4); c_index = c_index + 1)
-
- // do not print ASCII NULL character
- if (comm_words_hex[c_index] !== 8'b00000000)
-
- // print each character
- $write("%s", comm_words_hex[c_index]);
-
- // end the line
- $display("");
- end
- endtask
-
-//----------------------------------------------------------------------------
-// Open Command File
-//----------------------------------------------------------------------------
-// Reads the command file into an array. This process is only executed once.
- initial
- begin : p_open_file_bhav
-
- // report the stimulus file name to the simulation environment
- $display (`ARM_FRBM_OPENFILE_MSG, $time, message_tag, input_filename);
- $readmemh(input_filename, file_array);
- end
-
-
-//------------------------------------------------------------------------------
-// Sign-on banner
-//------------------------------------------------------------------------------
-// Writes a message to the simulation environment on exit from reset.
- always @ (posedge HCLK or negedge HRESETn)
- begin : p_banner_bhav
- if (HRESETn !== 1'b1)
- banner_done <= 1'b0;
- else
- if (banner_done !== 1'b1)
- begin
- banner_done <= 1'b1;
- $display ("%d %s", $time, message_tag);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_SIGN_ON_MSG1);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_SIGN_ON_MSG2);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_SIGN_ON_MSG3);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_SIGN_ON_MSG4);
- end
- end
-//------------------------------------------------------------------------------
-// Report errors to simulation environment
-//------------------------------------------------------------------------------
-// This process responds to error signals with an acknowledge signal and
-// reports the error to the simulation environment
-
- always @ (posedge HCLK or negedge HRESETn)
- begin : p_report_errors_bhav
- if (HRESETn !== 1'b1)
- begin
- data_err_cnt = 0;
- slave_resp_cnt = 0;
- poll_err_cnt = 0;
- end
- else
- if ((HREADY === 1'b1) && (skip_seq !== 1'b1)) // transfer complete
-
- // report an unexpected XFAIL response from slave
- // (XFAIL response checking has higher priority than ERROR reponse)
- if ((HRESP === `ARM_FRBM_RSP_XFAIL) && (err_resp_reg !== `ARM_FRBM_ERR_XFAIL))
- begin
- $display (`ARM_FRBM_SLAVE_XFAIL_MSG1, $time, message_tag);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_LINE_NUM, stim_line_reg);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_ADDRESS_MSG, haddr_reg);
- slave_resp_cnt = slave_resp_cnt + 1; // increment slave error counter
- end
-
- // report expected XFAIL response missing from slave
- else if ((HRESP !== `ARM_FRBM_RSP_XFAIL) && (err_resp_reg === `ARM_FRBM_ERR_XFAIL))
- begin
- $display (`ARM_FRBM_SLAVE_XFAIL_MSG2, $time, message_tag);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_LINE_NUM, stim_line_reg);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_ADDRESS_MSG, haddr_reg);
- slave_resp_cnt = slave_resp_cnt + 1; // increment slave error counter
- end
-
- // report an unexpected error response from slave
- else if ((HRESP !== `ARM_FRBM_RSP_OKAY) && (err_resp_reg === `ARM_FRBM_ERR_OKAY))
- begin
- $display (`ARM_FRBM_SLAVE_ERR_MSG1, $time, message_tag);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_LINE_NUM, stim_line_reg);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_ADDRESS_MSG, haddr_reg);
- slave_resp_cnt = slave_resp_cnt + 1; // increment slave error counter
- end
-
- // report expected error response missing from slave
- else if ((HRESP !== `ARM_FRBM_RSP_ERROR) &&
- ((err_resp_reg === `ARM_FRBM_ERR_CONT) || (err_resp_reg === `ARM_FRBM_ERR_CANC)))
- begin
- $display (`ARM_FRBM_SLAVE_ERR_MSG2, $time, message_tag);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_LINE_NUM, stim_line_reg);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_ADDRESS_MSG, haddr_reg);
- slave_resp_cnt = slave_resp_cnt + 1; // increment slave error counter
- end
-
- // report poll timeout error
- else if ( (data_err === 1'b1) && (poll_count === 32'h00000001))
- begin
- $display (`ARM_FRBM_POLL_ERR_MSG, $time, message_tag, timeout_reg);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_LINE_NUM, stim_line_reg);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_ADDRESS_MSG, haddr_reg);
-
-
- if (size_reg === `ARM_FRBM_SZ_DWORD) // 64 bit transfer
- begin
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_ACTUAL_DATA, HRDATA[63:0]);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_EXPECTED_DATA, data_reg[63:0]);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_DATA_MASK, mask_reg[63:0]);
- end
- else if (haddr_reg[2] === 1'b1) // less than 64 bit transfer
- begin // display high word
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_ACTUAL_DATA, HRDATA[63:32]);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_EXPECTED_DATA, data_reg[63:32]);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_DATA_MASK, mask_reg[63:32]);
- end
- else // display low word
- begin
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_ACTUAL_DATA, HRDATA[31:0]);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_EXPECTED_DATA, data_reg[31:0]);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_DATA_MASK, mask_reg[31:0]);
- end
-
- poll_err_cnt = poll_err_cnt + 1; // increment poll error counter
- end // if (data_err === 1'b1 && poll_count === 32'h00000001)
-
- // report data error
- else if ((data_err === 1'b1) && (poll_state === `ARM_FRBM_ST_NO_POLL))
- begin
- $display (`ARM_FRBM_DATA_ERR_MSG, $time, message_tag);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_LINE_NUM, stim_line_reg);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_ADDRESS_MSG, haddr_reg);
-
-
- if (size_reg === `ARM_FRBM_SZ_DWORD) // 64 bit transfer
- begin
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_ACTUAL_DATA, HRDATA[63:0]);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_EXPECTED_DATA, data_reg[63:0]);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_DATA_MASK, mask_reg[63:0]);
- end
- else if (haddr_reg[2] === 1'b1) // less than 64 bit transfer
- begin // display high word
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_ACTUAL_DATA, HRDATA[63:32]);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_EXPECTED_DATA, data_reg[63:32]);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_DATA_MASK, mask_reg[63:32]);
- end
- else // display low word
- begin
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_ACTUAL_DATA, HRDATA[31:0]);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_EXPECTED_DATA, data_reg[31:0]);
- $write (`ARM_FRBM_INDENT);
- $display (`ARM_FRBM_DATA_MASK, mask_reg[31:0]);
- end
-
- data_err_cnt = data_err_cnt + 1; // increment data error counter
- end // if (data_err === 1'b1 && poll_state === `ARM_FRBM_ST_NO_POLL)
- end // block: p_report_errors_bhav
-
-//------------------------------------------------------------------------------
-// Read Command
-//------------------------------------------------------------------------------
-// Reads next command from the array, if the previous one has completed,
-// indicated by rd_next. If a looped command is being executed, then the
-// command is not updated, if no more commands are available in the stimulus,
-// default signal values are used.
-// Control information that must be preserved is registered by this procedure.
-
- always @ (posedge HCLK or negedge HRESETn)
- begin : p_cmd_read_bhav
-
- reg use_bstrb_tmp; // flag indicates that Bstrb should be read
- // from stimulus file
- integer stim_line_tmp; // temporary stimulus line counter
- reg [31:0] loop_number; // count looping commands
- integer i; // loop counter
-
- if (HRESETn !== 1'b1)
- begin
- // signal reset values
- vec_cmd <= `ARM_FRBM_CMD_IDLE;
- vec_addr <= {32{1'b0}};
- vec_data <= {64{1'b0}};
- vec_data_mask <= {64{1'b1}};
- vec_size <= `ARM_FRBM_SZ_BYTE;
- vec_burst <= `ARM_FRBM_BUR_SINGLE;
- vec_prot <= 6'b000000;
- vec_dir <= 1'b0;
- vec_lock <= 1'b0;
- wait_rdy <= 1'b0;
- vec_bstrb <= 8'b00000000;
- use_bstrb_flag <= 1'b1;
- unalign <= 1'b0;
-
- err_resp <= 2'b00;
- skip_seq <= 1'b0;
- stim_end <= 1'b0;
-
- loop_number = {32{1'b0}};
- timeout <= {32{1'b0}};
- stim_line_num <= 0;
- stim_line_tmp = 0;
-
- array_ptr = 1'b0; // Go to beginning of command array
- file_array_tmp = {32{1'b0}};
- end // if (HRESETn !== 1'b1)
- else // HCLK rising edge
- begin
-
- skip_seq <= 1'b0; // sequence skip complete
-
- // copy signal values into variables
- stim_line_tmp = stim_line_num;
- use_bstrb_tmp = use_bstrb_flag;
-
- if (rd_next === 1'b1) // ready for next command
- begin
-
- // If ErrCanc is set, an error received and no new burst
- // starting, skip the remaining SEQ, BUSY and Comment commands
- // in this burst.
- if ((HRESP === `ARM_FRBM_RSP_ERROR) &&
- (HREADY === 1'b1) &&
- (err_resp_reg === `ARM_FRBM_ERR_CANC) &&
- ((vec_cmd === `ARM_FRBM_CMD_SEQ) || (vec_cmd === `ARM_FRBM_CMD_BUSY)))
- begin
-
- skip_seq <= 1'b1; // signals that sequence is being skipped
-
- // cancel current looping command
- loop_number = {32{1'b0}};
-
- file_array_tmp = file_array [array_ptr];
-
- // skip all commands in the current burst
- while ((file_array_tmp [31:24] === `ARM_FRBM_CMD_SEQ) ||
- (file_array_tmp [31:24] === `ARM_FRBM_CMD_BUSY) ||
- (file_array_tmp [31:24] === `ARM_FRBM_CMD_LOOP) ||
- (file_array_tmp [31:24] === `ARM_FRBM_CMD_COMM))
- begin
-
- // increment stimulus line counter
- stim_line_tmp = stim_line_tmp + file_array_tmp [5:0];
-
- if (file_array_tmp [31:24] === `ARM_FRBM_CMD_SEQ) // skip SEQ
- if (file_array_tmp [6] === 1'b1)
- // skip Bstrb field if present
- array_ptr = array_ptr + 6;
- else
- array_ptr = array_ptr + 5;
-
- else if (file_array_tmp [31:24] === `ARM_FRBM_CMD_BUSY) // skip BUSY
- if (file_array_tmp [6] === 1'b1)
- // skip Bstrb field if present
- array_ptr = array_ptr + 2;
- else
- array_ptr = array_ptr + 1;
-
- else if (file_array_tmp [31:24] === `ARM_FRBM_CMD_LOOP) // skip LOOP
- array_ptr = array_ptr + 2;
-
- else
- begin // skip Comment command
- array_ptr = array_ptr + 1;
- file_array_tmp = file_array [array_ptr];
- array_ptr = array_ptr + file_array_tmp [4:0];
- array_ptr = array_ptr + 1;
- end
-
- // Read a fresh word from the stimulus array
- file_array_tmp = file_array [array_ptr];
-
- end // while loop
- end // if (HRESP...
-
- // Read a fresh word from the stimulus array
- file_array_tmp = file_array [array_ptr];
-
- // Comment command prints a string to the simulation window in
- // zero simulation time.
- while ((file_array_tmp [31:24] === `ARM_FRBM_CMD_COMM) && // comment cmd
- (loop_number === `ARM_FRBM_LOW32)) // current command not looping
- begin
-
- // increment stimulus line counter
- stim_line_tmp = stim_line_tmp + file_array_tmp [5:0];
-
- array_ptr = array_ptr + 1;
-
- // get number of words
- file_array_tmp = file_array [array_ptr];
- comm_word_num = file_array_tmp [4:0];
-
- array_ptr = array_ptr + 1;
- file_array_tmp = file_array [array_ptr];
-
- // read in lines occupied by comment data
- for (i = 0; i < comm_word_num; i = i + 1)
- begin
- // store each character individually
- comm_words_hex[((i * 4) + 0)] = file_array_tmp [31:24];
- comm_words_hex[((i * 4) + 1)] = file_array_tmp [23:16];
- comm_words_hex[((i * 4) + 2)] = file_array_tmp [15:8];
- comm_words_hex[((i * 4) + 3)] = file_array_tmp [7:0];
-
- array_ptr = array_ptr + 1;
- file_array_tmp = file_array [array_ptr];
- end
-
- // call task to display the comment
- tsk_simulation_comment;
-
- end // while loop
-
- if (loop_number !== `ARM_FRBM_LOW32)
- // A command is currently looping
- loop_number = (loop_number - 1'b1);
-
-
- else
-
- begin
-
- file_array_tmp = file_array [array_ptr];
-
- case (file_array_tmp [31:24])
-
- `ARM_FRBM_CMD_WRITE : begin
- // Get each write command field
- vec_cmd <= file_array_tmp [31:24];
- vec_size <= file_array_tmp [23:21];
- vec_burst <= file_array_tmp [20:18];
- vec_prot <= file_array_tmp [17:12];
- vec_lock <= file_array_tmp [11];
- err_resp <= file_array_tmp [9:8];
- unalign <= file_array_tmp [7];
- use_bstrb_tmp = file_array_tmp [6];
- stim_line_tmp = stim_line_tmp + file_array_tmp [5:0];
- array_ptr = array_ptr + 1;
- vec_addr <= file_array [array_ptr];
- array_ptr = array_ptr + 1;
- vec_data [63:32] <= file_array [array_ptr];
- array_ptr = array_ptr + 1;
- vec_data [31:0] <= file_array [array_ptr];
- array_ptr = array_ptr + 1;
- // Bstrb field is present if use_bstrb_tmp is set
- if (use_bstrb_tmp === 1'b1) begin
- file_array_tmp = file_array [array_ptr];
- vec_bstrb <= file_array_tmp [7:0];
- array_ptr = array_ptr + 1;
- end
-
- end // case: `ARM_FRBM_CMD_WRITE
-
- `ARM_FRBM_CMD_READ : begin
- vec_cmd <= file_array_tmp [31:24];
- vec_size <= file_array_tmp [23:21];
- vec_burst <= file_array_tmp [20:18];
- vec_prot <= file_array_tmp [17:12];
- vec_lock <= file_array_tmp [11];
- err_resp <= file_array_tmp [9:8];
- unalign <= file_array_tmp [7];
- use_bstrb_tmp = file_array_tmp [6];
- stim_line_tmp = stim_line_tmp + file_array_tmp [5:0];
- array_ptr = array_ptr + 1;
- vec_addr <= file_array [array_ptr];
- array_ptr = array_ptr + 1;
- vec_data [63:32] <= file_array [array_ptr];
- array_ptr = (array_ptr + 1);
- vec_data [31:0] <= file_array [array_ptr];
- array_ptr = (array_ptr + 1);
- vec_data_mask [63:32] <= file_array [array_ptr];
- array_ptr = (array_ptr + 1);
- vec_data_mask [31:0] <= file_array [array_ptr];
- array_ptr = (array_ptr + 1);
- // Bstrb field is present if use_bstrb_tmp is set
- if (use_bstrb_tmp === 1'b1) begin
- file_array_tmp = file_array [array_ptr];
- vec_bstrb <= file_array_tmp [7:0];
- array_ptr = (array_ptr + 1);
- end
- end // case: `ARM_FRBM_CMD_READ
-
- `ARM_FRBM_CMD_SEQ : begin
- // Get each sequential command field
- vec_cmd <= file_array_tmp [31:24];
- err_resp <= file_array_tmp [9:8];
- use_bstrb_tmp = file_array_tmp [6];
- stim_line_tmp = stim_line_tmp + file_array_tmp [5:0];
- array_ptr = array_ptr + 1;
- vec_data [63:32] <= file_array [array_ptr];
- array_ptr = array_ptr + 1;
- vec_data [31:0] <= file_array [array_ptr];
- array_ptr = array_ptr + 1;
- vec_data_mask [63:32] <= file_array [array_ptr];
- array_ptr = array_ptr + 1;
- vec_data_mask [31:0] <= file_array [array_ptr];
- array_ptr = array_ptr + 1;
- // Bstrb field is present if use_bstrb_tmp is set
- if (use_bstrb_tmp === 1'b1) begin
- file_array_tmp = file_array [array_ptr];
- vec_bstrb <= file_array_tmp [7:0];
- array_ptr = array_ptr + 1;
- end
- end // case: `ARM_FRBM_CMD_SEQ
-
- `ARM_FRBM_CMD_BUSY : begin
- // Set busy command field
- vec_cmd <= file_array_tmp [31:24];
- wait_rdy <= file_array_tmp [8];
- use_bstrb_tmp = file_array_tmp [6];
- stim_line_tmp = stim_line_tmp + file_array_tmp [5:0];
- err_resp <= `ARM_FRBM_ERR_OKAY;
- array_ptr = array_ptr + 1;
- // Bstrb field is present if use_bstrb_tmp is set
- if (use_bstrb_tmp === 1'b1) begin
- file_array_tmp = file_array [array_ptr];
- vec_bstrb <= file_array_tmp [7:0];
- array_ptr = (array_ptr + 1);
- end
- end // case: `ARM_FRBM_CMD_BUSY
-
- `ARM_FRBM_CMD_IDLE : begin
- // Get each idle command field
- vec_cmd <= file_array_tmp [31:24];
- vec_size <= file_array_tmp [23:21];
- vec_burst <= file_array_tmp [20:18];
- vec_prot <= file_array_tmp [17:12];
- vec_lock <= file_array_tmp [11];
- vec_dir <= file_array_tmp [10];
- wait_rdy <= file_array_tmp [8];
- unalign <= file_array_tmp [7];
- use_bstrb_tmp = file_array_tmp [6];
- err_resp <= `ARM_FRBM_ERR_OKAY;
- stim_line_tmp = stim_line_tmp + file_array_tmp [5:0];
- array_ptr = array_ptr + 1;
- vec_addr <= file_array [array_ptr];
- array_ptr = array_ptr + 1;
- // Bstrb field is present if use_bstrb_tmp is set
- if (use_bstrb_tmp === 1'b1) begin
- file_array_tmp = file_array [array_ptr];
- vec_bstrb <= file_array_tmp [7:0];
- array_ptr = array_ptr + 1;
- end
- end // case: `ARM_FRBM_CMD_IDLE
-
- `ARM_FRBM_CMD_POLL : begin
- // Get each poll command field
- vec_cmd <= file_array_tmp [31:24];
- vec_size <= file_array_tmp [23:21];
- vec_burst <= file_array_tmp [20:18];
- vec_prot <= file_array_tmp [17:12];
- unalign <= file_array_tmp [7];
- use_bstrb_tmp = file_array_tmp [6];
- stim_line_tmp = stim_line_tmp + file_array_tmp [5:0];
- vec_lock <= 1'b0 ;
- err_resp <= `ARM_FRBM_ERR_OKAY;// Poll doesn't support ERROR field
- array_ptr = array_ptr + 1;
- file_array_tmp = file_array [array_ptr];
- timeout <= file_array_tmp [31:0]; // Poll timeout value
- array_ptr = array_ptr + 1;
- vec_addr <= file_array [array_ptr];
- array_ptr = array_ptr + 1;
- vec_data [63:32] <= file_array [array_ptr];
- array_ptr = array_ptr + 1;
- vec_data [31:0] <= file_array [array_ptr];
- array_ptr = array_ptr + 1;
- vec_data_mask [63:32] <= file_array [array_ptr];
- array_ptr = array_ptr + 1;
- vec_data_mask [31:0] <= file_array [array_ptr];
- array_ptr = array_ptr + 1;
- // Bstrb field is present if use_bstrb_tmp is set
- if (use_bstrb_tmp === 1'b1) begin
- file_array_tmp = file_array [array_ptr];
- vec_bstrb <= file_array_tmp [7:0];
- array_ptr = (array_ptr + 1);
- end
- end // case: `ARM_FRBM_CMD_POLL
-
- `ARM_FRBM_CMD_LOOP : begin
- // Loops are counted from n to 0 so the loop number is
- // reduced by 1.
- stim_line_tmp = stim_line_tmp + file_array_tmp [5:0];
- array_ptr = array_ptr + 1;
- file_array_tmp = file_array [array_ptr];
- loop_number = (file_array_tmp [31:0] - 1'b1);
- array_ptr = array_ptr + 1;
- end // case: `ARM_FRBM_CMD_LOOP
-
- `ARM_FRBM_CMD_QUIT : begin
- // Exit simulation and print error summary
- vec_cmd <= file_array_tmp [31:24];
- vec_addr <= {32{1'b0}};
- vec_data <= {64{1'b0}};
- vec_data_mask <= {64{1'b1}};
- vec_size <= `ARM_FRBM_SZ_BYTE;
- vec_burst <= `ARM_FRBM_BUR_SINGLE;
- vec_prot <= 6'b000000;
- vec_dir <= 1'b0;
- vec_lock <= 1'b0;
- wait_rdy <= 1'b0;
- vec_bstrb <= 8'b00000000;
- unalign <= 1'b0;
- err_resp <= `ARM_FRBM_ERR_OKAY;
- use_bstrb_tmp = 1;
- stim_line_tmp = stim_line_tmp + file_array_tmp [5:0];
- end
-
- `ARM_FRBM_UNDEF8 : begin
- // Set defaults as file stimulus exhausted
- vec_cmd <= `ARM_FRBM_CMD_IDLE;
- vec_addr <= {32{1'b0}};
- vec_data <= {64{1'b0}};
- vec_data_mask <= {64{1'b1}};
- vec_size <= `ARM_FRBM_SZ_BYTE;
- vec_burst <= `ARM_FRBM_BUR_SINGLE;
- vec_prot <= 6'b000000;
- vec_dir <= 1'b0;
- vec_lock <= 1'b0;
- wait_rdy <= 1'b0;
- vec_bstrb <= 8'b00000000;
- unalign <= 1'b0;
- use_bstrb_tmp = 1;
- err_resp <= `ARM_FRBM_ERR_OKAY;
- stim_end <= 1'b1; // set end of stimulus flag
- end
-
- default : begin
- $display (`ARM_FRBM_CMD_MSG, $time, message_tag);
- $stop; // stop the simulation
- end
-
- endcase // case(file_array_tmp [2:0])
-
- stim_line_num <= stim_line_tmp; // update stimulus line counter
-
- end // else: !if(loop_number !== 32'h00000000)
-
- use_bstrb_flag <= use_bstrb_tmp; // update Use Bstrb Flag
-
- end // rd_next = '1'
- end // else: if (HRESETn !== 1'b1)
- end // always begin
-
-//------------------------------------------------------------------------------
-// Quit simulation if found Q command in stimulus file
-//------------------------------------------------------------------------------
-
- always @ (posedge HCLK)
- begin : p_simulation_end
- if ( (cmd_reg === `ARM_FRBM_CMD_QUIT) ||
- ((stim_end_data === 1'b1) && (stim_end_data_reg === 1'b0))
- )
- begin
- // stimulus just exhausted
- $display ("");
- $write ("%d %s ", $time, message_tag);
-
- if (cmd_reg === `ARM_FRBM_CMD_QUIT)
- // simulation ended by Quit command
- $display (`ARM_FRBM_QUIT_MSG);
- else
- // simulation ended by completion of stimulus
- $display (`ARM_FRBM_END_MSG);
-
- // write summary info
- $display ("");
- $display (`ARM_FRBM_SUMMARY_HEADER);
- $display (`ARM_FRBM_SUMMARY_DATA, data_err_cnt);
- $display (`ARM_FRBM_SUMMARY_SLAVE, slave_resp_cnt);
- $display (`ARM_FRBM_SUMMARY_POLL, poll_err_cnt);
- $display (`ARM_FRBM_SUMMARY_FOOTER);
- $display ("");
-
- // if simulation ended by Quit command then halt simulation
- if ( cmd_reg ===`ARM_FRBM_CMD_QUIT )
- begin
- $display (" Simulation Ended.");
- $finish;
- end
- end // if begin
- end // always begin
-
-//---------------------------------------------------------------------------
-// END OF BEHAVIOURAL CODE
-//---------------------------------------------------------------------------
-
-//---------------------------------------------------------------------------
-// Register Current Command
-//---------------------------------------------------------------------------
-// The current command is registered when a new command is read from the file
-
- always @ (posedge HCLK or negedge HRESETn)
- begin : p_reg_file_seq
- if (HRESETn !== 1'b1)
- begin
- cmd_reg <= 8'b00000000;
- data_reg <= {64{1'b0}};
- mask_reg <= {64{1'b0}};
- size_reg <= 3'b000;
- err_resp_reg <= 2'b00;
- stim_end_data <= 1'b0;
- stim_line_reg <= 0;
- timeout_reg <= {32{1'b0}};
- end // if (HRESETn !== 1'b1)
- else
- if (HREADY === 1'b1)
- begin
- cmd_reg <= vec_cmd;
- data_reg <= vec_data;
- mask_reg <= mask;
- size_reg <= vec_size;
- err_resp_reg <= err_resp;
- stim_end_data <= stim_end;
- stim_line_reg <= stim_line_num;
- timeout_reg <= timeout;
- end // if (HREADY === 1'b1)
- end // block: p_reg_file_seq
-
-
-//---------------------------------------------------------------------------
-// Register Stimulus End Flag
-//---------------------------------------------------------------------------
-// Stimulus End Flag is registered so that the summary information is only
-// displayed once.
-
- always @ (posedge HCLK or negedge HRESETn)
- begin : p_stim_end_reg
- if (HRESETn !== 1'b1)
- stim_end_data_reg <= 1'b0;
- else
- stim_end_data_reg <= stim_end_data;
- end
-
-//---------------------------------------------------------------------------
-// Register Output values
-//---------------------------------------------------------------------------
-// The output address, write signal and transfer type are registered when
-// HREADY is asserted.
-
- always @ (posedge HCLK or negedge HRESETn)
- begin : p_reg_outputs_seq
- if (HRESETn !== 1'b1)
- begin
- haddr_reg <= {32{1'b0}};
- htrans_reg <= {2{1'b0}};
- hwrite_reg <= 1'b0;
- end
- else
- if (HREADY === 1'b1)
- begin
- htrans_reg <= i_htrans;
- haddr_reg <= i_haddr;
- hwrite_reg <= i_hwrite;
- end // if (HREADY)
- end // block: p_reg_outputs_seq
-
-
-//------------------------------------------------------------------------------
-// Mask used for rounding down address before incrementing
-//------------------------------------------------------------------------------
- always @ (vec_size)
- begin : p_align_mask_comb
- case (vec_size )
- `ARM_FRBM_SZ_BYTE : align_mask = 3'b111;
- `ARM_FRBM_SZ_HALF : align_mask = 3'b110;
- `ARM_FRBM_SZ_WORD : align_mask = 3'b100;
- `ARM_FRBM_SZ_DWORD : align_mask = 3'b000;
- default : align_mask = 3'b111;
- endcase
- end
-
-
-//------------------------------------------------------------------------------
-// Calculate aligned address
-//------------------------------------------------------------------------------
-// Base of incremented address is calculated by rounding down initial address
-// to boundary of transfer (container) size.
-
- assign aligned_addr_l = (haddr_reg [2:0] & align_mask);
- assign aligned_addr = {haddr_reg [31:3], aligned_addr_l};
-
-
-//---------------------------------------------------------------------------
-// Determine add_value and calculate address
-//---------------------------------------------------------------------------
-
-// The value to be added to the address is based on the current command, the
-// previous command and the width of the data.
-//
-// The address should be incremented when:
-// HTRANS is sequential or busy and previous vec_cmd is sequential or read
-// or write (NONSEQ).
-
- assign non_zero = (((vec_cmd === `ARM_FRBM_CMD_SEQ) && (cmd_reg === `ARM_FRBM_CMD_SEQ)) ||
- ((vec_cmd === `ARM_FRBM_CMD_SEQ) && (cmd_reg === `ARM_FRBM_CMD_WRITE)) ||
- ((vec_cmd === `ARM_FRBM_CMD_SEQ) && (cmd_reg === `ARM_FRBM_CMD_READ)) ||
- ((vec_cmd === `ARM_FRBM_CMD_BUSY) && (cmd_reg === `ARM_FRBM_CMD_SEQ)) ||
- ((vec_cmd === `ARM_FRBM_CMD_BUSY) && (cmd_reg === `ARM_FRBM_CMD_WRITE)) ||
- ((vec_cmd === `ARM_FRBM_CMD_BUSY) && (cmd_reg === `ARM_FRBM_CMD_READ))) ? 1'b1
- : 1'b0;
-
- always @ (vec_size or non_zero)
- begin : p_calc_add_value_comb
- if (non_zero === 1'b1)
- begin
- case (vec_size)
- `ARM_FRBM_SZ_BYTE : add_value = 4'b0001;
- `ARM_FRBM_SZ_HALF : add_value = 4'b0010;
- `ARM_FRBM_SZ_WORD : add_value = 4'b0100;
- `ARM_FRBM_SZ_DWORD: add_value = 4'b1000;
- default : add_value = 4'b0000;
- endcase // case(vec_size)
- end // if non_zero
- else
- add_value = 4'b0000;
- end // block: p_calc_add_value_comb
-
-//---------------------------------------------------------------------------
-// Calculate new address value
-//---------------------------------------------------------------------------
-// A 10-bit incrementer is not used, so that bursts >1k bytes may be tested
-
- // Pad AddValue to 32 bits
- assign incr_addr = aligned_addr + { {28{1'b0}}, add_value };
-
-//---------------------------------------------------------------------------
-// Trap wrapping burst boundaries
-//---------------------------------------------------------------------------
-
-// When the burst is a wrapping burst the calculated address must not cross
-// the boundary (size(bytes) x beats in burst).
-// The boundary value is set based on the Burst and Size values
-
- always @ (vec_size or vec_burst)
- begin : p_boundary_value_comb
- case (vec_size)
-
- `ARM_FRBM_SZ_BYTE :
- case (vec_burst)
- `ARM_FRBM_BUR_WRAP4 : boundary = `ARM_FRBM_BOUND4;
- `ARM_FRBM_BUR_WRAP8 : boundary = `ARM_FRBM_BOUND8;
- `ARM_FRBM_BUR_WRAP16 : boundary = `ARM_FRBM_BOUND16;
- `ARM_FRBM_BUR_SINGLE,
- `ARM_FRBM_BUR_INCR,
- `ARM_FRBM_BUR_INCR4,
- `ARM_FRBM_BUR_INCR8,
- `ARM_FRBM_BUR_INCR16 : boundary = `ARM_FRBM_NOBOUND;
- default : boundary = `ARM_FRBM_NOBOUND;
- endcase // case (vec_burst)
-
- `ARM_FRBM_SZ_HALF :
- case (vec_burst)
- `ARM_FRBM_BUR_WRAP4 : boundary = `ARM_FRBM_BOUND8;
- `ARM_FRBM_BUR_WRAP8 : boundary = `ARM_FRBM_BOUND16;
- `ARM_FRBM_BUR_WRAP16 : boundary = `ARM_FRBM_BOUND32;
- `ARM_FRBM_BUR_SINGLE,
- `ARM_FRBM_BUR_INCR,
- `ARM_FRBM_BUR_INCR4,
- `ARM_FRBM_BUR_INCR8,
- `ARM_FRBM_BUR_INCR16 : boundary = `ARM_FRBM_NOBOUND;
- default : boundary = `ARM_FRBM_NOBOUND;
- endcase // case (vec_burst)
-
- `ARM_FRBM_SZ_WORD :
- case (vec_burst)
- `ARM_FRBM_BUR_WRAP4 : boundary = `ARM_FRBM_BOUND16;
- `ARM_FRBM_BUR_WRAP8 : boundary = `ARM_FRBM_BOUND32;
- `ARM_FRBM_BUR_WRAP16 : boundary = `ARM_FRBM_BOUND64;
- `ARM_FRBM_BUR_SINGLE,
- `ARM_FRBM_BUR_INCR,
- `ARM_FRBM_BUR_INCR4,
- `ARM_FRBM_BUR_INCR8,
- `ARM_FRBM_BUR_INCR16 : boundary = `ARM_FRBM_NOBOUND;
- default : boundary = `ARM_FRBM_NOBOUND;
- endcase // case (vec_burst)
-
- `ARM_FRBM_SZ_DWORD :
- case (vec_burst)
- `ARM_FRBM_BUR_WRAP4 : boundary = `ARM_FRBM_BOUND32;
- `ARM_FRBM_BUR_WRAP8 : boundary = `ARM_FRBM_BOUND64;
- `ARM_FRBM_BUR_WRAP16 : boundary = `ARM_FRBM_BOUND128;
- `ARM_FRBM_BUR_SINGLE,
- `ARM_FRBM_BUR_INCR,
- `ARM_FRBM_BUR_INCR4,
- `ARM_FRBM_BUR_INCR8,
- `ARM_FRBM_BUR_INCR16 : boundary = `ARM_FRBM_NOBOUND;
- default : boundary = `ARM_FRBM_NOBOUND;
- endcase // case (vec_burst)
-
- default : boundary = `ARM_FRBM_NOBOUND;
- endcase // case (vec_size)
- end // block: p_boundary_value_comb
-
-// The calculated address is checked to see if it has crossed the boundary.
-// If it has the result address is wrapped, otherwise it is equal to the
-// calculated address.
-
- always @ (boundary or incr_addr or aligned_addr)
- begin : p_wrapped_addr_comb
-
- case (boundary)
-
- `ARM_FRBM_NOBOUND :
- wrapped_addr = incr_addr;
-
- `ARM_FRBM_BOUND4 :
- if (incr_addr [1:0] === 2'b00)
- begin
- wrapped_addr [31:2] = aligned_addr [31:2];
- wrapped_addr [1:0] = 2'b00;
- end // if (incr_addr [1:0] === 2'b00)
- else
- wrapped_addr = incr_addr;
-
- `ARM_FRBM_BOUND8 :
- if (incr_addr [2:0] === 3'b000)
- begin
- wrapped_addr [31:3] = aligned_addr [31:3];
- wrapped_addr [2:0] = 3'b000;
- end // if (incr_addr [2:0] === 3'b000)
- else
- wrapped_addr = incr_addr;
-
- `ARM_FRBM_BOUND16 :
- if (incr_addr [3:0] === 4'b0000)
- begin
- wrapped_addr [31:4] = aligned_addr [31:4];
- wrapped_addr [3:0] = 4'b0000;
- end // if (incr_addr [3:0] === 4'b0000)
- else
- wrapped_addr = incr_addr;
-
- `ARM_FRBM_BOUND32 :
- if (incr_addr [4:0] === 5'b00000)
- begin
- wrapped_addr [31:5] = aligned_addr [31:5];
- wrapped_addr [4:0] = 5'b00000;
- end // if (incr_addr [4:0] === 5'b00000)
- else
- wrapped_addr = incr_addr;
-
- `ARM_FRBM_BOUND64 :
- if (incr_addr [5:0] === 6'b000000)
- begin
- wrapped_addr [31:6] = aligned_addr [31:6];
- wrapped_addr [5:0] = 6'b000000;
- end // if (incr_addr [5:0] === 6'b000000)
- else
- wrapped_addr = incr_addr;
-
- `ARM_FRBM_BOUND128 :
- if (incr_addr [6:0] === 7'b0000000)
- begin
- wrapped_addr [31:7] = aligned_addr [31:7];
- wrapped_addr [6:0] = 7'b0000000;
- end // if (incr_addr [6:0] === 7'b000000)
- else
- wrapped_addr = incr_addr;
-
- default :
- wrapped_addr = {32{1'b0}};
-
- endcase // case(boundary)
-
- end // block: p_wrapped_addr_comb
-
-//---------------------------------------------------------------------------
-// Address Output
-//---------------------------------------------------------------------------
-// Address is calculated when there is a busy or sequential command otherwise
-// the value from the input file is used. The registered address is used for
-// poll commands.
-
- assign i_haddr = ((vec_cmd ===`ARM_FRBM_CMD_SEQ) || (vec_cmd ===`ARM_FRBM_CMD_BUSY)) ? wrapped_addr
- : vec_addr;
-
- assign HADDR = i_haddr;
-
-//---------------------------------------------------------------------------
-// Next Line File Read Control
-//---------------------------------------------------------------------------
-// If the FileReader is not attempting a transfer that will result in data
-// transfer, the master can continue to read commands from the file when HREADY
-// is low. The exception is when the command being executed is a poll command.
-
- assign rd_next = (next_poll_state ===`ARM_FRBM_ST_NO_POLL) &&
- ( (HREADY === 1'b1) ||
- ( (wait_rdy === 1'b0) &&
- ((vec_cmd ===`ARM_FRBM_CMD_BUSY ) || (vec_cmd ===`ARM_FRBM_CMD_IDLE ))
- )
- ) ? 1'b1
-
- : 1'b0;
-
-//---------------------------------------------------------------------------
-// Transfer Type Control
-//---------------------------------------------------------------------------
-// Transfer type output, when executing a poll command HTRANS can only be
-// set to NONSEQ or IDLE, depending on the poll state.
-// HTRANS over-ridden to IDLE when cancelling a burst due to error response.
-// For the other commands HTRANS is set to NONSEQ for read and write commands,
-// SEQ for sequential and BUSY for busy commands.
-
- always @ (vec_cmd or err_resp_reg or HRESP or HREADY or next_poll_state)
- begin : p_htrans_control_comb
- if (vec_cmd === `ARM_FRBM_CMD_POLL)
- begin
- if (next_poll_state === `ARM_FRBM_ST_POLL_TEST)
- i_htrans = `ARM_FRBM_TRN_NONSEQ;
- else
- i_htrans = `ARM_FRBM_TRN_IDLE;
- end
- else if ((HRESP === `ARM_FRBM_RSP_ERROR) && // ERROR response received
- (err_resp_reg === `ARM_FRBM_ERR_CANC) && // ERROR response expected
- (HREADY === 1'b1) && // 2nd cycle of ERROR response
- ((vec_cmd === `ARM_FRBM_CMD_SEQ) || (vec_cmd === `ARM_FRBM_CMD_BUSY))) // burst transfer
- i_htrans = `ARM_FRBM_TRN_IDLE; // cancel pending transfer
- else
- case (vec_cmd)
- `ARM_FRBM_CMD_WRITE : i_htrans = `ARM_FRBM_TRN_NONSEQ;
- `ARM_FRBM_CMD_READ : i_htrans = `ARM_FRBM_TRN_NONSEQ;
- `ARM_FRBM_CMD_SEQ : i_htrans = `ARM_FRBM_TRN_SEQ;
- `ARM_FRBM_CMD_BUSY : i_htrans = `ARM_FRBM_TRN_BUSY;
- `ARM_FRBM_CMD_IDLE : i_htrans = `ARM_FRBM_TRN_IDLE;
- `ARM_FRBM_CMD_QUIT : i_htrans = `ARM_FRBM_TRN_IDLE;
- default : i_htrans = `ARM_FRBM_TRN_IDLE;
- endcase // case (vec_cmd)
- end // block: p_htrans_control_comb
-
- assign HTRANS = i_htrans;
-
-//---------------------------------------------------------------------------
-// Direction Control
-//---------------------------------------------------------------------------
-// HWRITE is only asserted for a write command or the idle command, when dir
-// set. HWRITE retains its value until the end of the burst.
-
- assign i_hwrite = ((vec_cmd === `ARM_FRBM_CMD_BUSY) ||
- (vec_cmd === `ARM_FRBM_CMD_SEQ)) ? hwrite_reg
-
- : ((vec_cmd === `ARM_FRBM_CMD_WRITE) ||
- ((vec_cmd === `ARM_FRBM_CMD_IDLE) && (vec_dir === 1'b1))) ? 1'b1
-
- : 1'b0;
-
- assign HWRITE = i_hwrite;
-
-//------------------------------------------------------------------------------
-// Other Transfer Control Information
-//------------------------------------------------------------------------------
-
- assign HMASTLOCK = vec_lock;
- assign HSIZE = vec_size;
- assign HBURST = vec_burst;
- assign HPROT = vec_prot;
- assign HUNALIGN = unalign;
-
- assign LINENUM = stim_line_num;
-
-//------------------------------------------------------------------------------
-// Byte Lane Strobes
-//------------------------------------------------------------------------------
-// HSTRB is calculated when Bstrb is not specified in the stimulus, otherwise
-// the value from the input file is used. The registered version is used for
-// poll commands.
-//
-// Assumes 64-bit data bus, and that use_bstrb_flag signal is asserted for all
-// unaligned transfers.
-
- always @ (i_haddr[2:0] or vec_size or use_bstrb_flag or vec_bstrb)
- begin : p_bstrb_comb
- // If Bstrb is specified in the stimulus file, byte lane strobes are used
- // directly from the stimulus file.
- if (use_bstrb_flag === 1'b1)
- i_hbstrb = vec_bstrb;
- else
- begin
-// If use_bstrb_flag is not specified in the stimulus file, byte lane strobes
-// are calculated. Aligned transfers only are supported.
- case (vec_size)
- `ARM_FRBM_SZ_BYTE : begin
- case (i_haddr [2:0])
- 3'b000 : i_hbstrb = 8'b00000001;
- 3'b001 : i_hbstrb = 8'b00000010;
- 3'b010 : i_hbstrb = 8'b00000100;
- 3'b011 : i_hbstrb = 8'b00001000;
- 3'b100 : i_hbstrb = 8'b00010000;
- 3'b101 : i_hbstrb = 8'b00100000;
- 3'b110 : i_hbstrb = 8'b01000000;
- 3'b111 : i_hbstrb = 8'b10000000;
- default : i_hbstrb = 8'b00000000; // Invalid address
- endcase
- end
-
- `ARM_FRBM_SZ_HALF : begin
- case (i_haddr [2:0])
- 3'b000 : i_hbstrb = 8'b00000011;
- 3'b010 : i_hbstrb = 8'b00001100;
- 3'b100 : i_hbstrb = 8'b00110000;
- 3'b110 : i_hbstrb = 8'b11000000;
- default : i_hbstrb = 8'b00000000; // Invalid/unaligned address
- endcase
- end
-
- `ARM_FRBM_SZ_WORD : begin
- case (i_haddr [2:0])
- 3'b000 : i_hbstrb = 8'b00001111;
- 3'b100 : i_hbstrb = 8'b11110000;
- default : i_hbstrb = 8'b00000000; // Invalid/unaligned address
- endcase
- end
-
-
- `ARM_FRBM_SZ_DWORD : begin
- case (i_haddr [2:0])
- 3'b000 : i_hbstrb = 8'b11111111;
- default : i_hbstrb = 8'b00000000; // Invalid/unaligned address
- endcase
- end
-
- default : i_hbstrb = 8'b00000000; // Invalid size (> bus width)
- endcase
- end
- end
-//------------------------------------------------------------------------------
-// HSTRB Output
-//------------------------------------------------------------------------------
-
- assign HBSTRB = i_hbstrb;
-
-
-//------------------------------------------------------------------------------
-// Byte Lane Strobe data mask
-//------------------------------------------------------------------------------
-// Calculate 64-bit mask, based on iHSTRB
-// Note: This assumes little-endian mode.
-
- assign bstrb_mask [7:0] = i_hbstrb [0] ? 8'b11111111 : 8'b00000000;
- assign bstrb_mask [15:8] = i_hbstrb [1] ? 8'b11111111 : 8'b00000000;
- assign bstrb_mask [23:16] = i_hbstrb [2] ? 8'b11111111 : 8'b00000000;
- assign bstrb_mask [31:24] = i_hbstrb [3] ? 8'b11111111 : 8'b00000000;
- assign bstrb_mask [39:32] = i_hbstrb [4] ? 8'b11111111 : 8'b00000000;
- assign bstrb_mask [47:40] = i_hbstrb [5] ? 8'b11111111 : 8'b00000000;
- assign bstrb_mask [55:48] = i_hbstrb [6] ? 8'b11111111 : 8'b00000000;
- assign bstrb_mask [63:56] = i_hbstrb [7] ? 8'b11111111 : 8'b00000000;
-
-//------------------------------------------------------------------------------
-// Resultant mask - taking into account Bstrb values
-//------------------------------------------------------------------------------
-// Assumes 64-bit data bus, and that use_bstrb_flag signal will be asserted
-// for all unaligned transfers.
-
- assign mask = (use_bstrb_flag === 1'b1) ? (vec_data_mask & bstrb_mask) : vec_data_mask;
-
-//---------------------------------------------------------------------------
-// Data Control and Compare
-//---------------------------------------------------------------------------
-// When the transfer type from the previous address cycle was TRN_NONSEQ or
-// TRN_SEQ then either the read or write data bus will be active in the
-// next cycle.
-// write data is recorded in the address cycle
-
- assign i_hwdata = (
- (i_hwrite === 1'b1) &&
- (HREADY === 1'b1) &&
- ((i_htrans === `ARM_FRBM_TRN_NONSEQ) ||
- (i_htrans === `ARM_FRBM_TRN_SEQ))
- ) ? vec_data
- : {64{1'b0}};
-
- // The write data is registered when HREADY is asserted
- always @ (posedge HCLK or negedge HRESETn)
- begin : p_reg_wdata_seq
- if (HRESETn !== 1'b1)
- hwdata_reg <= {64{1'b0}};
- else if (HREADY === 1'b1)
- hwdata_reg <= i_hwdata;
- end // block: p_reg_wdata_seq
-
- // The registered value is output on the AHB-Lite interface
- assign HWDATA = hwdata_reg;
-
- // Read data is recorded in the cycle after the address and compared with
- // the expected data value after applying the mask.
- // Note that the data is checked only if an OKAY response is received.
- always @ (data_reg or HRESP or HRDATA or mask_reg or htrans_reg or hwrite_reg)
- begin : p_data_compare_comb
- if ((hwrite_reg === 1'b0) && (HRESP === `ARM_FRBM_RSP_OKAY) &&
- ((htrans_reg ===`ARM_FRBM_TRN_NONSEQ) || (htrans_reg ===`ARM_FRBM_TRN_SEQ)))
- data_compare = ((data_reg & mask_reg) ^ (HRDATA & mask_reg));
- else
- data_compare = {64{1'b0}};
- end // block: p_data_compare_comb
-
- // If data_compare is non-zero, flag an error.
- assign data_err = (data_compare !== {64{1'b0}}) ? 1'b1
- : 1'b0;
-
-//------------------------------------------------------------------------------
-// Poll State Machine
-//------------------------------------------------------------------------------
-// The poll command requires two AHB transfers: a read followed by an idle to
-// get the data from the read transfer. This command will continue until the
-// data read matches the expected data or the poll timeout count is reached.
-// The state machine is used to control the read and idle transfers and the
-// completion of the poll command.
-
- always @ (poll_state or vec_cmd or data_err or poll_count or timeout)
- begin : p_poll_state_comb
- case (poll_state)
-
- `ARM_FRBM_ST_NO_POLL : begin
- if (vec_cmd === `ARM_FRBM_CMD_POLL) // if poll command, read transfer in this cycle
- begin
- next_poll_state = `ARM_FRBM_ST_POLL_TEST; // test data in next cycle
- next_poll_count = timeout; // load poll counter with timeout value
- end
- else // no poll command
- begin
- next_poll_state = `ARM_FRBM_ST_NO_POLL;
- next_poll_count = poll_count;
- end
- end // case: `ARM_FRBM_ST_NO_POLL
-
- `ARM_FRBM_ST_POLL_TEST : begin // data phase of poll transfer
- if ((data_err === 1'b0) || // data matched and non-ERROR response
- (poll_count === 32'h00000001)) // poll timed out
- begin
- next_poll_state = `ARM_FRBM_ST_NO_POLL;
- next_poll_count = 32'b00000000;
- end
- else
- begin // data not matched and poll not timed out
- next_poll_state = `ARM_FRBM_ST_POLL_READ; // poll again
- if (poll_count !== 32'b00000000)
- next_poll_count = poll_count - 1'b1; // decrement timeout counter
- else
- next_poll_count = poll_count;
- end
- end // case: `ARM_FRBM_ST_POLL_TEST
-
- `ARM_FRBM_ST_POLL_READ : // address phase of poll transfer
- begin
- next_poll_state = `ARM_FRBM_ST_POLL_TEST; // next state always to test the data
- next_poll_count = poll_count;
- end
-
- default: // illegal state transition
- begin
- next_poll_state = `ARM_FRBM_ST_NO_POLL;
- next_poll_count = poll_count;
- end
-
- endcase // case(poll_state)
- end // block: p_poll_state_comb
-
- // Poll state and count registers
- always @ (posedge HCLK or negedge HRESETn)
- begin : p_poll_state_seq
- if (HRESETn !== 1'b1)
- begin
- poll_state <= `ARM_FRBM_ST_NO_POLL;
- poll_count <= 32'b00000000;
- end
- else
- if (HREADY === 1'b1) // updated on each transfer completion
- begin
- poll_state <= next_poll_state;
- poll_count <= next_poll_count;
- end
- end // block: p_poll_state_seq
-
-endmodule // FileReadCore
-
-// --================================ End ==================================--
diff --git a/hdl/verif/cmsdk/cmsdk_ahb_ram_beh.v b/hdl/verif/cmsdk/cmsdk_ahb_ram_beh.v
deleted file mode 100644
index 7ca65fc1c175a1b2f2c6fff4c5045f585c2de7e7..0000000000000000000000000000000000000000
--- a/hdl/verif/cmsdk/cmsdk_ahb_ram_beh.v
+++ /dev/null
@@ -1,209 +0,0 @@
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Simple AHB RAM behavioral model
-//-----------------------------------------------------------------------------
-module cmsdk_ahb_ram_beh #(
- parameter AW = 16,// Address width
- parameter filename = "",
- parameter WS_N = 0, // First access wait state
- parameter WS_S = 0) // Subsequent access wait state
- (
- input wire HCLK, // Clock
- input wire HRESETn, // Reset
- input wire HSEL, // Device select
- input wire [AW-1:0] HADDR, // Address
- input wire [1:0] HTRANS, // Transfer control
- input wire [2:0] HSIZE, // Transfer size
- input wire HWRITE, // Write control
- input wire [31:0] HWDATA, // Write data
- input wire HREADY, // Transfer phase done
- output wire HREADYOUT, // Device ready
- output wire [31:0] HRDATA, // Read data output
- output wire HRESP); // Device response (always OKAY)
-
- // Internal signals
- reg [7:0] ram_data[0:((1<<AW)-1)]; // 64k byte of RAM data
- wire read_valid; // Address phase read valid
- wire write_valid; // Address phase write valid
- reg read_enable; // Data phase read enable
- reg write_enable; // Data phase write enable
- reg [3:0] reg_byte_lane; // Data phase byte lane
- reg [3:0] next_byte_lane; // Next state of reg_byte_lane
-
- reg [7:0] rdata_out_0; // Read Data Output byte#0
- reg [7:0] rdata_out_1; // Read Data Output byte#1
- reg [7:0] rdata_out_2; // Read Data Output byte#2
- reg [7:0] rdata_out_3; // Read Data Output byte#3
- reg [AW-1:0] word_addr; // Word aligned address
- wire [AW-1:0] nxt_word_addr; // Word aligned address
- integer i; // Loop counter
-
- // Wait state control
- wire [31:0] nxt_waitstate_cnt;
- reg [31:0] reg_waitstate_cnt;
- wire sequential_access;
-
- // Start of main code
- // Initialize ROM
- initial
- begin
- for (i=0;i<(1<<AW);i=i+1)
- begin
- ram_data[i] = 8'h00; //Initialize all data to 0
- end
- if (filename != "")
- begin
- $readmemh(filename, ram_data); // Then read in program code
- end
- end
-
- // Generate read control (address phase)
- assign read_valid = HSEL & HREADY & HTRANS[1] & (~HWRITE);
- // Generate write control (address phase)
- assign write_valid = HSEL & HREADY & HTRANS[1] & HWRITE;
-
- // Read enable for each byte (address phase)
- always @(read_valid or write_valid or HADDR or HSIZE)
- begin
- if (read_valid | write_valid)
- begin
- case (HSIZE)
- 0 : // Byte
- begin
- case (HADDR[1:0])
- 0: next_byte_lane = 4'b0001; // Byte 0
- 1: next_byte_lane = 4'b0010; // Byte 1
- 2: next_byte_lane = 4'b0100; // Byte 2
- 3: next_byte_lane = 4'b1000; // Byte 3
- default:next_byte_lane = 4'b0000; // Address not valid
- endcase
- end
- 1 : // Halfword
- begin
- if (HADDR[1])
- next_byte_lane = 4'b1100; // Upper halfword
- else
- next_byte_lane = 4'b0011; // Lower halfword
- end
- default : // Word
- next_byte_lane = 4'b1111; // Whole word
- endcase
- end
- else
- next_byte_lane = 4'b0000; // Not reading
- end
-
- // Registering control signals to data phase
- always @(posedge HCLK or negedge HRESETn)
- begin
- if (~HRESETn)
- begin
- reg_byte_lane <= 4'b0000;
- read_enable <= 1'b0;
- write_enable <= 1'b0;
- word_addr <= {AW{1'b0}};
- end
- else if (HREADY)
- begin
- reg_byte_lane <= next_byte_lane;
- read_enable <= read_valid;
- write_enable <= write_valid;
- word_addr <= nxt_word_addr;
- end
- end
-
- assign nxt_word_addr = {HADDR[AW-1:2], 2'b00};
-
- // Read operation
- always @(read_enable or reg_byte_lane or word_addr)
- if ((read_enable & reg_byte_lane[0]))
- rdata_out_0 = ram_data[word_addr ];
- else
- rdata_out_0 = 8'h00;
-
- always @(read_enable or reg_byte_lane or word_addr)
- if ((read_enable & reg_byte_lane[1]))
- rdata_out_1 = ram_data[word_addr+1];
- else
- rdata_out_1 = 8'h00;
-
- always @(read_enable or reg_byte_lane or word_addr)
- if ((read_enable & reg_byte_lane[2]))
- rdata_out_2 = ram_data[word_addr+2];
- else
- rdata_out_2 = 8'h00;
-
- always @(read_enable or reg_byte_lane or word_addr)
- if ((read_enable & reg_byte_lane[3]))
- rdata_out_3 = ram_data[word_addr+3];
- else
- rdata_out_3 = 8'h00;
-
- // Registered write
- always @(posedge HCLK)
- begin
- if (write_enable & reg_byte_lane[0])
- begin
- ram_data[word_addr ] = HWDATA[ 7: 0];
- end
- if (write_enable & reg_byte_lane[1])
- begin
- ram_data[word_addr+1] = HWDATA[15: 8];
- end
- if (write_enable & reg_byte_lane[2])
- begin
- ram_data[word_addr+2] = HWDATA[23:16];
- end
- if (write_enable & reg_byte_lane[3])
- begin
- ram_data[word_addr+3] = HWDATA[31:24];
- end
- end
-
- // Wait state control
- // Wait state generate treat access as sequential if
- // HTRANS = 2'b11, or access address is in the same word,
- // or if the access is in the next word
- assign sequential_access = (HTRANS==2'b11) |
- (HADDR[AW-1:2] == word_addr[AW-1:2]) |
- (HADDR[AW-1:2] == (word_addr[AW-1:2]+1));
- assign nxt_waitstate_cnt = (read_valid|write_valid) ?
- ((sequential_access) ? WS_S : WS_N) :
- ((reg_waitstate_cnt!=0) ? (reg_waitstate_cnt - 1) : 0);
- // Register wait state counter
- always @(posedge HCLK or negedge HRESETn)
- begin
- if (~HRESETn)
- reg_waitstate_cnt <= 0;
- else
- reg_waitstate_cnt <= nxt_waitstate_cnt;
- end
-
- // Connect to top level
- assign HREADYOUT = (reg_waitstate_cnt==0) ? 1'b1 : 1'b0;
- assign HRESP = 1'b0; // Always response with OKAY
- // Read data output
- assign HRDATA = {rdata_out_3, rdata_out_2, rdata_out_1,rdata_out_0};
-
-endmodule
diff --git a/hdl/verif/cmsdk/cmsdk_ahb_slave_mux.v b/hdl/verif/cmsdk/cmsdk_ahb_slave_mux.v
deleted file mode 100644
index e6821446cfdae2866f21a258c96511cfca221a50..0000000000000000000000000000000000000000
--- a/hdl/verif/cmsdk/cmsdk_ahb_slave_mux.v
+++ /dev/null
@@ -1,226 +0,0 @@
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Simple AHB slave multiplexer
-//-----------------------------------------------------------------------------
-// Each port can be disabled by parameter if not used.
-
-module cmsdk_ahb_slave_mux #(
- // Parameters to enable/disable ports
- // By default all ports are enabled
- parameter PORT0_ENABLE=1,
- parameter PORT1_ENABLE=1,
- parameter PORT2_ENABLE=1,
- parameter PORT3_ENABLE=1,
- parameter PORT4_ENABLE=1,
- parameter PORT5_ENABLE=1,
- parameter PORT6_ENABLE=1,
- parameter PORT7_ENABLE=1,
- parameter PORT8_ENABLE=1,
- parameter PORT9_ENABLE=1,
-
- // Data Bus Width
- parameter DW=32
- )
- (
- input wire HCLK, // Clock
- input wire HRESETn, // Reset
- input wire HREADY, // Bus ready
- input wire HSEL0, // HSEL for AHB Slave #0
- input wire HREADYOUT0, // HREADY for Slave connection #0
- input wire HRESP0, // HRESP for slave connection #0
- input wire [DW-1:0] HRDATA0, // HRDATA for slave connection #0
- input wire HSEL1, // HSEL for AHB Slave #1
- input wire HREADYOUT1, // HREADY for Slave connection #1
- input wire HRESP1, // HRESP for slave connection #1
- input wire [DW-1:0] HRDATA1, // HRDATA for slave connection #1
- input wire HSEL2, // HSEL for AHB Slave #2
- input wire HREADYOUT2, // HREADY for Slave connection #2
- input wire HRESP2, // HRESP for slave connection #2
- input wire [DW-1:0] HRDATA2, // HRDATA for slave connection #2
- input wire HSEL3, // HSEL for AHB Slave #3
- input wire HREADYOUT3, // HREADY for Slave connection #3
- input wire HRESP3, // HRESP for slave connection #3
- input wire [DW-1:0] HRDATA3, // HRDATA for slave connection #3
- input wire HSEL4, // HSEL for AHB Slave #4
- input wire HREADYOUT4, // HREADY for Slave connection #4
- input wire HRESP4, // HRESP for slave connection #4
- input wire [DW-1:0] HRDATA4, // HRDATA for slave connection #4
- input wire HSEL5, // HSEL for AHB Slave #5
- input wire HREADYOUT5, // HREADY for Slave connection #5
- input wire HRESP5, // HRESP for slave connection #5
- input wire [DW-1:0] HRDATA5, // HRDATA for slave connection #5
- input wire HSEL6, // HSEL for AHB Slave #6
- input wire HREADYOUT6, // HREADY for Slave connection #6
- input wire HRESP6, // HRESP for slave connection #6
- input wire [DW-1:0] HRDATA6, // HRDATA for slave connection #6
- input wire HSEL7, // HSEL for AHB Slave #7
- input wire HREADYOUT7, // HREADY for Slave connection #7
- input wire HRESP7, // HRESP for slave connection #7
- input wire [DW-1:0] HRDATA7, // HRDATA for slave connection #7
- input wire HSEL8, // HSEL for AHB Slave #8
- input wire HREADYOUT8, // HREADY for Slave connection #8
- input wire HRESP8, // HRESP for slave connection #8
- input wire [DW-1:0] HRDATA8, // HRDATA for slave connection #8
- input wire HSEL9, // HSEL for AHB Slave #9
- input wire HREADYOUT9, // HREADY for Slave connection #9
- input wire HRESP9, // HRESP for slave connection #9
- input wire [DW-1:0] HRDATA9, // HRDATA for slave connection #9
- output wire HREADYOUT, // HREADY output to AHB master and AHB slaves
- output wire HRESP, // HRESP to AHB master
- output wire [DW-1:0] HRDATA // Read data to AHB master
- );
-
- wire mux_hready; // multiplexed HREADY sigal
- reg [9:0] reg_hsel; // Register selection control
- wire [9:0] nxt_hsel_reg; // next state for nxt_hsel_reg
-
- assign nxt_hsel_reg[0] = HSEL0 & (PORT0_ENABLE!=0);
- assign nxt_hsel_reg[1] = HSEL1 & (PORT1_ENABLE!=0);
- assign nxt_hsel_reg[2] = HSEL2 & (PORT2_ENABLE!=0);
- assign nxt_hsel_reg[3] = HSEL3 & (PORT3_ENABLE!=0);
- assign nxt_hsel_reg[4] = HSEL4 & (PORT4_ENABLE!=0);
- assign nxt_hsel_reg[5] = HSEL5 & (PORT5_ENABLE!=0);
- assign nxt_hsel_reg[6] = HSEL6 & (PORT6_ENABLE!=0);
- assign nxt_hsel_reg[7] = HSEL7 & (PORT7_ENABLE!=0);
- assign nxt_hsel_reg[8] = HSEL8 & (PORT8_ENABLE!=0);
- assign nxt_hsel_reg[9] = HSEL9 & (PORT9_ENABLE!=0);
-
- // Registering MuxCtrl
- always @(posedge HCLK or negedge HRESETn)
- begin
- if (~HRESETn)
- reg_hsel <= {10{1'b0}};
- else if (HREADY) // advance pipeline if HREADY is 1
- reg_hsel <= nxt_hsel_reg;
- end
-
- assign mux_hready =
- ((~reg_hsel[0]) | HREADYOUT0 | (PORT0_ENABLE==0)) &
- ((~reg_hsel[1]) | HREADYOUT1 | (PORT1_ENABLE==0)) &
- ((~reg_hsel[2]) | HREADYOUT2 | (PORT2_ENABLE==0)) &
- ((~reg_hsel[3]) | HREADYOUT3 | (PORT3_ENABLE==0)) &
- ((~reg_hsel[4]) | HREADYOUT4 | (PORT4_ENABLE==0)) &
- ((~reg_hsel[5]) | HREADYOUT5 | (PORT5_ENABLE==0)) &
- ((~reg_hsel[6]) | HREADYOUT6 | (PORT6_ENABLE==0)) &
- ((~reg_hsel[7]) | HREADYOUT7 | (PORT7_ENABLE==0)) &
- ((~reg_hsel[8]) | HREADYOUT8 | (PORT8_ENABLE==0)) &
- ((~reg_hsel[9]) | HREADYOUT9 | (PORT9_ENABLE==0)) ;
-
- assign HREADYOUT = mux_hready; // Connect to top level
-
- assign HRDATA =
- ({DW{(reg_hsel[0] & (PORT0_ENABLE!=0))}} & HRDATA0) |
- ({DW{(reg_hsel[1] & (PORT1_ENABLE!=0))}} & HRDATA1) |
- ({DW{(reg_hsel[2] & (PORT2_ENABLE!=0))}} & HRDATA2) |
- ({DW{(reg_hsel[3] & (PORT3_ENABLE!=0))}} & HRDATA3) |
- ({DW{(reg_hsel[4] & (PORT4_ENABLE!=0))}} & HRDATA4) |
- ({DW{(reg_hsel[5] & (PORT5_ENABLE!=0))}} & HRDATA5) |
- ({DW{(reg_hsel[6] & (PORT6_ENABLE!=0))}} & HRDATA6) |
- ({DW{(reg_hsel[7] & (PORT7_ENABLE!=0))}} & HRDATA7) |
- ({DW{(reg_hsel[8] & (PORT8_ENABLE!=0))}} & HRDATA8) |
- ({DW{(reg_hsel[9] & (PORT9_ENABLE!=0))}} & HRDATA9) ;
-
- assign HRESP =
- (reg_hsel[0] & HRESP0 & (PORT0_ENABLE!=0)) |
- (reg_hsel[1] & HRESP1 & (PORT1_ENABLE!=0)) |
- (reg_hsel[2] & HRESP2 & (PORT2_ENABLE!=0)) |
- (reg_hsel[3] & HRESP3 & (PORT3_ENABLE!=0)) |
- (reg_hsel[4] & HRESP4 & (PORT4_ENABLE!=0)) |
- (reg_hsel[5] & HRESP5 & (PORT5_ENABLE!=0)) |
- (reg_hsel[6] & HRESP6 & (PORT6_ENABLE!=0)) |
- (reg_hsel[7] & HRESP7 & (PORT7_ENABLE!=0)) |
- (reg_hsel[8] & HRESP8 & (PORT8_ENABLE!=0)) |
- (reg_hsel[9] & HRESP9 & (PORT9_ENABLE!=0)) ;
-
- // ------------------------------------------------------------
-
-`ifdef ARM_AHB_ASSERT_ON
- // ------------------------------------------------------------
- // Assertions
- // ------------------------------------------------------------
-`include "std_ovl_defines.h"
-
- // When HREADYOUT is low, reg_hsel must be non-zero (Property of design)
- assert_never
- #(`OVL_ERROR,`OVL_ASSERT,
- "reg_hsel must not be zero when HREADYOUT is low")
- u_ovl_readyout_asserted_when_not_active
- (.clk(HCLK), .reset_n(HRESETn),
- .test_expr( (~HREADYOUT) & (reg_hsel=={10{1'b0}}))
- );
-
- // Properties of the inputs of the design
-
- // HSEL should be one-hot
- // If this OVL fires - there is an error in the design of the address decoder
- assert_zero_one_hot
- #(`OVL_FATAL,10,`OVL_ASSERT,
- "Only one HSEL input can be activated.")
- u_ovl_hsel_one_hot
- (.clk(HCLK), .reset_n(HRESETn),
- .test_expr({HSEL0,
- HSEL1,
- HSEL2,
- HSEL3,
- HSEL4,
- HSEL5,
- HSEL6,
- HSEL7,
- HSEL8,
- HSEL9}));
-
- // When HREADYOUT is low, HREADY should be low
- assert_never
- #(`OVL_ERROR,`OVL_ASSERT,
- "HREADY should be low when HREADYOUT is low")
- u_ovl_ready_mismatch
- (.clk(HCLK), .reset_n(HRESETn),
- .test_expr( (~HREADYOUT) & HREADY )
- );
-
- // Check if a disabled port is selected
- // (system design error, check the verilog parameter in module instantiation)
- assert_never
- #(`OVL_ERROR,`OVL_ASSERT,
- "A disabled port is selected")
- u_ovl_disabled_port_selected
- (.clk(HCLK), .reset_n(HRESETn),
- .test_expr(HREADY & (
- ((PORT0_ENABLE==0) & HSEL0) |
- ((PORT1_ENABLE==0) & HSEL1) |
- ((PORT2_ENABLE==0) & HSEL2) |
- ((PORT3_ENABLE==0) & HSEL3) |
- ((PORT4_ENABLE==0) & HSEL4) |
- ((PORT5_ENABLE==0) & HSEL5) |
- ((PORT6_ENABLE==0) & HSEL6) |
- ((PORT7_ENABLE==0) & HSEL7) |
- ((PORT8_ENABLE==0) & HSEL8) |
- ((PORT9_ENABLE==0) & HSEL9)
- ))
- );
-
-`endif
-
-
-endmodule
diff --git a/hdl/verif/tb_wrapper_sha256_hashing_stream.sv b/hdl/verif/tb_wrapper_sha256_hashing_stream.sv
deleted file mode 100644
index 364d3167fa203e05bd3933596f870b42a9e0a88b..0000000000000000000000000000000000000000
--- a/hdl/verif/tb_wrapper_sha256_hashing_stream.sv
+++ /dev/null
@@ -1,254 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Testbench for Top-level AHB Wrapper
-// Modified from tb_frbm_example.v
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-------------------------------------------------------------------------
-// Abstract : Example for File Reader Bus Master
-// Testbench for the example AHB Lite slave.
-//=========================================================================--
-`include "wrapper_sha256_hashing_stream.sv"
-
-`timescale 1ns/1ps
-
-module tb_wrapper_sha256_hashing_stream;
-
-parameter CLK_PERIOD = 10;
-parameter ADDRWIDTH = 12;
-
-parameter InputFileName = ("../../accelerator-wrapper/simulate/stimulus/ahb_input_hash_stim.m2d");
-parameter MessageTag = "FileReader:";
-parameter StimArraySize = 10000;
-
-
-//********************************************************************************
-// Internal Wires
-//********************************************************************************
-
-// AHB Lite BUS SIGNALS
-wire hready;
-wire hresp;
-wire [31:0] hrdata;
-
-wire [1:0] htrans;
-wire [2:0] hburst;
-wire [3:0] hprot;
-wire [2:0] hsize;
-wire hwrite;
-wire hmastlock;
-wire [31:0] haddr;
-wire [31:0] hwdata;
-
-// Accelerator AHB Signals
-wire hsel0;
-wire hreadyout0;
-wire hresp0;
-wire [31:0] hrdata0;
-
-// Default Slave AHB Signals
-wire hsel1;
-wire hreadyout1;
-wire hresp1;
-wire [31:0] hrdata1;
-
-reg HCLK;
-reg HRESETn;
-
-//********************************************************************************
-// Clock and reset generation
-//********************************************************************************
-
-initial
- begin
- $dumpfile("wrapper_sha256_hashing_stream.vcd");
- $dumpvars(0, tb_wrapper_sha256_hashing_stream);
- HRESETn = 1'b0;
- HCLK = 1'b0;
- # (10*CLK_PERIOD);
- HRESETn = 1'b1;
- end
-
-always
- begin
- HCLK = #(CLK_PERIOD/2) ~HCLK;
- end
-
-
-//********************************************************************************
-// Address decoder, need to be changed for other configuration
-//********************************************************************************
-// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator
-// Other addresses : HSEL #1 - Default slave
-
- assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0;
- assign hsel1 = hsel0 ? 1'b0:1'b1;
-
-//********************************************************************************
-// File read bus master:
-// generate AHB Master signal by reading a file which store the AHB Operations
-//********************************************************************************
-
-cmsdk_ahb_fileread_master32 #(InputFileName,
- MessageTag,
- StimArraySize
-) u_ahb_fileread_master32 (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- .HREADY (hready),
- .HRESP ({hresp}), //AHB Lite response to AHB response
- .HRDATA (hrdata),
- .EXRESP (1'b0), // Exclusive response (tie low if not used)
-
-
- .HTRANS (htrans),
- .HBURST (hburst),
- .HPROT (hprot),
- .EXREQ (), // Exclusive access request (not used)
- .MEMATTR (), // Memory attribute (not used)
- .HSIZE (hsize),
- .HWRITE (hwrite),
- .HMASTLOCK (hmastlock),
- .HADDR (haddr),
- .HWDATA (hwdata),
-
- .LINENUM ()
-
- );
-
-
-//********************************************************************************
-// Slave multiplexer module:
-// multiplex the slave signals to master, three ports are enabled
-//********************************************************************************
-
- cmsdk_ahb_slave_mux #(
- 1, //PORT0_ENABLE
- 1, //PORT1_ENABLE
- 1, //PORT2_ENABLE
- 0, //PORT3_ENABLE
- 0, //PORT4_ENABLE
- 0, //PORT5_ENABLE
- 0, //PORT6_ENABLE
- 0, //PORT7_ENABLE
- 0, //PORT8_ENABLE
- 0 //PORT9_ENABLE
- ) u_ahb_slave_mux (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HREADY (hready),
- .HSEL0 (hsel0), // Input Port 0
- .HREADYOUT0 (hreadyout0),
- .HRESP0 (hresp0),
- .HRDATA0 (hrdata0),
- .HSEL1 (hsel1), // Input Port 1
- .HREADYOUT1 (hreadyout1),
- .HRESP1 (hresp1),
- .HRDATA1 (hrdata1),
- .HSEL2 (1'b0), // Input Port 2
- .HREADYOUT2 (),
- .HRESP2 (),
- .HRDATA2 (),
- .HSEL3 (1'b0), // Input Port 3
- .HREADYOUT3 (),
- .HRESP3 (),
- .HRDATA3 (),
- .HSEL4 (1'b0), // Input Port 4
- .HREADYOUT4 (),
- .HRESP4 (),
- .HRDATA4 (),
- .HSEL5 (1'b0), // Input Port 5
- .HREADYOUT5 (),
- .HRESP5 (),
- .HRDATA5 (),
- .HSEL6 (1'b0), // Input Port 6
- .HREADYOUT6 (),
- .HRESP6 (),
- .HRDATA6 (),
- .HSEL7 (1'b0), // Input Port 7
- .HREADYOUT7 (),
- .HRESP7 (),
- .HRDATA7 (),
- .HSEL8 (1'b0), // Input Port 8
- .HREADYOUT8 (),
- .HRESP8 (),
- .HRDATA8 (),
- .HSEL9 (1'b0), // Input Port 9
- .HREADYOUT9 (),
- .HRESP9 (),
- .HRDATA9 (),
-
- .HREADYOUT (hready), // Outputs
- .HRESP (hresp),
- .HRDATA (hrdata)
- );
-
-
-//********************************************************************************
-// Slave module 1: example AHB slave module
-//********************************************************************************
- wrapper_sha256_hashing_stream #(ADDRWIDTH
- ) accelerator (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .HSELS (hsel0),
- .HADDRS (haddr[ADDRWIDTH-1:0]),
- .HTRANSS (htrans),
- .HSIZES (hsize),
- .HWRITES (hwrite),
- .HREADYS (hready),
- .HWDATAS (hwdata),
-
- .HREADYOUTS (hreadyout0),
- .HRESPS (hresp0),
- .HRDATAS (hrdata0)
-
- );
-
-
-//********************************************************************************
-// Slave module 2: AHB default slave module
-//********************************************************************************
- cmsdk_ahb_default_slave u_ahb_default_slave(
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (hsel1),
- .HTRANS (htrans),
- .HREADY (hready),
- .HREADYOUT (hreadyout1),
- .HRESP (hresp1)
- );
-
- assign hrdata1 = {32{1'b0}}; // Default slave don't have data
-
- endmodule
\ No newline at end of file
diff --git a/hdl/verif/tb_wrapper_vr_loopback.sv b/hdl/verif/tb_wrapper_vr_loopback.sv
deleted file mode 100644
index 5e25339e114b82463f362b5f946cc606b96feeec..0000000000000000000000000000000000000000
--- a/hdl/verif/tb_wrapper_vr_loopback.sv
+++ /dev/null
@@ -1,260 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Testbench for Wrapper Valid-Ready Loopback Test
-// Modified from tb_frbm_example.v
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-------------------------------------------------------------------------
-// Abstract : Example for File Reader Bus Master
-// Testbench for the example AHB Lite slave.
-//=========================================================================--
-`include "cmsdk_ahb_filereadcore.v"
-`include "cmsdk_ahb_fileread_funnel.v"
-`include "cmsdk_ahb_fileread_master32.v"
-`include "cmsdk_ahb_default_slave.v"
-`include "cmsdk_ahb_slave_mux.v"
-`include "wrapper_vr_loopback.sv"
-
-`timescale 1ns/1ps
-
-module tb_wrapper_vr_loopback;
-
-parameter CLK_PERIOD = 10;
-parameter ADDRWIDTH = 12;
-
-// parameter InputFileName = "ahb_input_hash_stim.m2d";
-parameter InputFileName = ("../stimulus/ahb_input_hash_stim.m2d");
-parameter MessageTag = "FileReader:";
-parameter StimArraySize = 10000;
-
-
-//********************************************************************************
-// Internal Wires
-//********************************************************************************
-
-// AHB Lite BUS SIGNALS
-wire hready;
-wire hresp;
-wire [31:0] hrdata;
-
-wire [1:0] htrans;
-wire [2:0] hburst;
-wire [3:0] hprot;
-wire [2:0] hsize;
-wire hwrite;
-wire hmastlock;
-wire [31:0] haddr;
-wire [31:0] hwdata;
-
-// Accelerator AHB Signals
-wire hsel0;
-wire hreadyout0;
-wire hresp0;
-wire [31:0] hrdata0;
-
-// Default Slave AHB Signals
-wire hsel1;
-wire hreadyout1;
-wire hresp1;
-wire [31:0] hrdata1;
-
-reg HCLK;
-reg HRESETn;
-
-//********************************************************************************
-// Clock and reset generation
-//********************************************************************************
-
-initial
- begin
- $dumpfile("wrapper_vr_loopback.vcd");
- $dumpvars(0, tb_wrapper_vr_loopback);
- HRESETn = 1'b0;
- HCLK = 1'b0;
- # (10*CLK_PERIOD);
- HRESETn = 1'b1;
- end
-
-always
- begin
- HCLK = #(CLK_PERIOD/2) ~HCLK;
- end
-
-
-//********************************************************************************
-// Address decoder, need to be changed for other configuration
-//********************************************************************************
-// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator
-// Other addresses : HSEL #1 - Default slave
-
- assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0;
- assign hsel1 = hsel0 ? 1'b0:1'b1;
-
-//********************************************************************************
-// File read bus master:
-// generate AHB Master signal by reading a file which store the AHB Operations
-//********************************************************************************
-
-cmsdk_ahb_fileread_master32 #(InputFileName,
- MessageTag,
- StimArraySize
-) u_ahb_fileread_master32 (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- .HREADY (hready),
- .HRESP ({hresp}), //AHB Lite response to AHB response
- .HRDATA (hrdata),
- .EXRESP (1'b0), // Exclusive response (tie low if not used)
-
-
- .HTRANS (htrans),
- .HBURST (hburst),
- .HPROT (hprot),
- .EXREQ (), // Exclusive access request (not used)
- .MEMATTR (), // Memory attribute (not used)
- .HSIZE (hsize),
- .HWRITE (hwrite),
- .HMASTLOCK (hmastlock),
- .HADDR (haddr),
- .HWDATA (hwdata),
-
- .LINENUM ()
-
- );
-
-
-//********************************************************************************
-// Slave multiplexer module:
-// multiplex the slave signals to master, three ports are enabled
-//********************************************************************************
-
- cmsdk_ahb_slave_mux #(
- 1, //PORT0_ENABLE
- 1, //PORT1_ENABLE
- 1, //PORT2_ENABLE
- 0, //PORT3_ENABLE
- 0, //PORT4_ENABLE
- 0, //PORT5_ENABLE
- 0, //PORT6_ENABLE
- 0, //PORT7_ENABLE
- 0, //PORT8_ENABLE
- 0 //PORT9_ENABLE
- ) u_ahb_slave_mux (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HREADY (hready),
- .HSEL0 (hsel0), // Input Port 0
- .HREADYOUT0 (hreadyout0),
- .HRESP0 (hresp0),
- .HRDATA0 (hrdata0),
- .HSEL1 (hsel1), // Input Port 1
- .HREADYOUT1 (hreadyout1),
- .HRESP1 (hresp1),
- .HRDATA1 (hrdata1),
- .HSEL2 (1'b0), // Input Port 2
- .HREADYOUT2 (),
- .HRESP2 (),
- .HRDATA2 (),
- .HSEL3 (1'b0), // Input Port 3
- .HREADYOUT3 (),
- .HRESP3 (),
- .HRDATA3 (),
- .HSEL4 (1'b0), // Input Port 4
- .HREADYOUT4 (),
- .HRESP4 (),
- .HRDATA4 (),
- .HSEL5 (1'b0), // Input Port 5
- .HREADYOUT5 (),
- .HRESP5 (),
- .HRDATA5 (),
- .HSEL6 (1'b0), // Input Port 6
- .HREADYOUT6 (),
- .HRESP6 (),
- .HRDATA6 (),
- .HSEL7 (1'b0), // Input Port 7
- .HREADYOUT7 (),
- .HRESP7 (),
- .HRDATA7 (),
- .HSEL8 (1'b0), // Input Port 8
- .HREADYOUT8 (),
- .HRESP8 (),
- .HRDATA8 (),
- .HSEL9 (1'b0), // Input Port 9
- .HREADYOUT9 (),
- .HRESP9 (),
- .HRDATA9 (),
-
- .HREADYOUT (hready), // Outputs
- .HRESP (hresp),
- .HRDATA (hrdata)
- );
-
-
-//********************************************************************************
-// Slave module 1: example AHB slave module
-//********************************************************************************
- wrapper_vr_loopback #(ADDRWIDTH
- ) accelerator (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .HSELS (hsel0),
- .HADDRS (haddr[ADDRWIDTH-1:0]),
- .HTRANSS (htrans),
- .HSIZES (hsize),
- .HWRITES (hwrite),
- .HREADYS (hready),
- .HWDATAS (hwdata),
-
- .HREADYOUTS (hreadyout0),
- .HRESPS (hresp0),
- .HRDATAS (hrdata0)
-
- );
-
-
-//********************************************************************************
-// Slave module 2: AHB default slave module
-//********************************************************************************
- cmsdk_ahb_default_slave u_ahb_default_slave(
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (hsel1),
- .HTRANS (htrans),
- .HREADY (hready),
- .HREADYOUT (hreadyout1),
- .HRESP (hresp1)
- );
-
- assign hrdata1 = {32{1'b0}}; // Default slave don't have data
-
- endmodule
\ No newline at end of file