Regenerated Stimulus, tied off configuration and corrected Clock and Reset Wiring in Wrapper

flow/stimgen.py

@@ -79,29 +79,34 @@ def fri_output(out_file, word_list):
         f.write(table_str)
         f.write("\nQ") # Add End of Simulation Flag
 
-def stimulus_generation(in_file, start_address, size):
+def stimulus_generation(stim_file, ref_file, input_start_address, input_size, output_start_address, output_size):
     """ 
     This function takes 32 bit input stimulus file from accelerator model,
     calculates write addresses for each word and generates a .fri file which
     can be used to stimulate an AHB testbench
     """
     # Calculate End Address
-    end_address = start_address + size - 0x4
+    input_end_address = input_start_address + input_size - 0x4
     # print(f"End Address is {hex(end_address)}")
 
-    # Open File
-    with open(in_file, "r") as stim:
+    # Open Files
+    with open(stim_file, "r") as stim:
         csvreader = csv.reader(stim, delimiter=",")
         stim_list = list(csvreader)
 
-    # Initialise Packet List
-    packet_list = []
+    with open(ref_file, "r") as ref:
+        csvreader = csv.reader(ref, delimiter=",")
+        ref_list = list(csvreader)
+
+    # Initialise Packet Lists
+    write_packet_list = []
+    read_packet_list  = []
 
     # Initialise Temporary Structures
     temppacketstruct = InputPacketStruct()
     tempblockstruct = InputBlockStruct()
 
-    # Read Data into Structs
+    # Put Write Data into Structs
     for i in stim_list:
         tempblockstruct.word_append(int(i[0],16))
         # If Last Word in Block, Append to Packet and Reset Temporary block structure
@@ -110,7 +115,19 @@ def stimulus_generation(in_file, start_address, size):
             tempblockstruct = InputBlockStruct()
             # If Last Block in Packet , Append Packet to Packet List and Reset Temp Packet
             if (int(i[2])):
-                packet_list.append(temppacketstruct)
+                write_packet_list.append(temppacketstruct)
+                temppacketstruct = InputPacketStruct()
+
+    # Put Read Data into Structs
+    for i in ref_list:
+        tempblockstruct.word_append(int(i[0],16))
+        # If Last Word in Block, Append to Packet and Reset Temporary block structure
+        if (int(i[1])):
+            temppacketstruct.block_append(tempblockstruct)
+            tempblockstruct = InputBlockStruct()
+            # If Last Block in Packet , Append Packet to Packet List and Reset Temp Packet
+            if (int(i[2])):
+                read_packet_list.append(temppacketstruct)
                 temppacketstruct = InputPacketStruct()
         
     
@@ -118,28 +135,37 @@ def stimulus_generation(in_file, start_address, size):
     output_word_list = []
 
     # Generate Address for Packet
-    for packet_num, packet in enumerate(packet_list):
+    for packet_num, write_packet in enumerate(write_packet_list):
         # Calculate Number of Blocks in First Packet
-        num_blocks = len(packet.block_list)
-        # Each Block Can Contain 16 32-bit Words (512 bits) (0x4 * 16 = 0x40)
+        num_blocks = len(write_packet.block_list)
+        # Each Write Block Can Contain 16 32-bit Words (512 bits) (0x4 * 16 = 0x40)
         # - Work Out Required Size = (0x40 * NumBlocks)
         # - Work Out Beginning Address = (end_address + 0x4) - Size
         req_write_size = 0x40 * num_blocks
-        start_write_addr = start_address + size - req_write_size
+        start_write_addr = input_start_address + input_size - req_write_size
+        # Each Read Block Contains 8 32-bit Words (256 bits) (0x4 * 8 = 0x20)
+        req_read_size  = 0x20
+        start_read_addr  = output_start_address + output_size - req_read_size
         # print(f"Packet: {int(packet_num)} | Start Address: {hex(start_write_addr)}")
         write_addr = start_write_addr
-        for block_num, block in enumerate(packet.block_list):
-            read_address = write_addr + 0x0000_0800
+        read_addr  = start_read_addr
+        # Write out Packet containing multiple 512 bit Blocks to Input Port
+        for block_num, block in enumerate(write_packet.block_list):
             for word in block.word_list:
                 word_data = WordStruct(word, write_addr, TransactionType.WRITE, packet_num, block_num)
                 output_word_list.append(word_data)
                 # Increment Address
                 write_addr += 0x4
+        # Set Read Packet
+        read_packet = read_packet_list[packet_num]
+        # Read Back 256 Bit Packet from Output Port
+        for block_num, block in enumerate(read_packet.block_list):
             for word in block.word_list:
-                word_data = WordStruct(word, read_address, TransactionType.READ, packet_num, block_num)
+                word_data = WordStruct(word, read_addr, TransactionType.READ, packet_num, 0)
                 output_word_list.append(word_data)
                 # Increment Address
-                read_address += 0x4
+                read_addr += 0x4
+
 
     # Generate FRI File with Write Transactions
     fri_file = os.environ["WRAP_ACC_DIR"] + "/simulate/stimulus/" + "ahb_input_hash_stim.fri"
@@ -153,5 +179,8 @@ def stimulus_generation(in_file, start_address, size):
 if __name__ == "__main__":
     accelerator_input_address = 0x6001_0000
     accelerator_input_size = 0x0000_0800
-    in_file = os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/system/" + "input_data_32bit_stim.csv"
-    stimulus_generation(in_file, accelerator_input_address, accelerator_input_size)
\ No newline at end of file
+    accelerator_output_address = 0x6001_0800
+    accelerator_output_size = 0x0000_0800
+    stim_file = os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/system/" + "input_data_32bit_stim.csv"
+    ref_file = os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/system/" + "output_hash_32bit_ref.csv"
+    stimulus_generation(stim_file, ref_file, accelerator_input_address, accelerator_input_size, accelerator_output_address, accelerator_output_size)
\ No newline at end of file

hdl/src/wrapper_sha256_hashing_stream.sv

@@ -93,17 +93,30 @@ module wrapper_sha256_hashing_stream #(
   logic                 output_rready;     
 
   // Internal Wiring
+  // Input Packet Wires
   logic [511:0] in_packet;    
   logic         in_packet_last; 
   logic         in_packet_valid;
   logic         in_packet_ready;
 
-  // Internal Wiring
-  logic [256:0] out_packet;    
+  // Output Packet Wires
+  logic [255:0] out_packet;    
   logic         out_packet_last; 
   logic         out_packet_valid;
   logic         out_packet_ready;
 
+  // Configuration Tie Off
+  logic [63:0] cfg_size;
+  logic [1:0]  cfg_scheme;
+  logic cfg_last;
+  logic cfg_valid;
+  logic cfg_ready;
+
+  assign cfg_size   = 64'd512;
+  assign cfg_scheme = 2'd0;
+  assign cfg_last   = 1'b1;
+  assign cfg_valid  = 1'b1;
+
   //-----------------------------------------------------------
   // Module logic start
   //----------------------------------------------------------
@@ -175,8 +188,8 @@ module wrapper_sha256_hashing_stream #(
   );
 
   sha256_hashing_stream u_sha256_hashing_stream (
-        .clk            (clk),
-        .nrst           (nrst),
+        .clk            (HCLK),
+        .nrst           (HRESETn),
         .en             (1'b1),
         .sync_rst       (1'b0),