Skip to content
Snippets Groups Projects
Commit f5484458 authored by David Mapstone's avatar David Mapstone
Browse files

UPdated Port Names on Constructor and deconstructor and wired in hashing stream to wrapper

parent b481897a
No related branches found
No related tags found
No related merge requests found
Hide whitespace changes
Inline Side-by-side
hdl/src/wrapper_packet_construct.sv
+ 17
− 18
View file @ f5484458
......@@ -27,10 +27,10 @@ module wrapper_packet_construct #(
output logic rready,
// Valid/Ready interface
output logic [PACKETWIDTH-1:0] data_out,
output logic data_out_last,
output logic data_out_valid,
input logic data_out_ready
output logic [PACKETWIDTH-1:0] packet_data,
output logic packet_data_last,
output logic packet_data_valid,
input logic packet_data_ready
);
// 4KiB of Address Space for Accelerator (11:0)
......@@ -50,20 +50,20 @@ assign addr_top_bit = (addr[5:2] * 32) - 1 + 32;
always_ff @(posedge hclk or negedge hresetn) begin
if (~hresetn) begin
// Reset Construction Buffer
const_buffer <= {PACKETWIDTH{1'b0}};
const_buffer <= {PACKETWIDTH{1'b0}};
// Reset Values
data_out_valid <= 1'b0;
data_out_last <= 1'b0;
data_out <= {PACKETWIDTH{1'b0}};
last_wr_addr <= {ADDRWIDTH{1'b0}};
packet_data_valid <= 1'b0;
packet_data_last <= 1'b0;
packet_data <= {PACKETWIDTH{1'b0}};
last_wr_addr <= {ADDRWIDTH{1'b0}};
end else begin
// Handshake Output
if (data_out_ready && data_out_valid) begin
data_out_valid <= 1'b0;
if (packet_data_ready && packet_data_valid) begin
packet_data_valid <= 1'b0;
end
if (write_en) begin
// If not (awaiting handshake AND address generates new data payload)
if (!((data_out_valid && !data_out_ready) && (addr[5:2] == 4'hF))) begin
if (!((packet_data_valid && !packet_data_ready) && (addr[5:2] == 4'hF))) begin
// Buffer Address for future Comparison
last_wr_addr <= addr;
......@@ -76,14 +76,14 @@ always_ff @(posedge hclk or negedge hresetn) begin
// If last 32 bit word of 512 bit buffer
if (addr[5:2] == 4'hF) begin
// Produce Data Output
data_out <= {wdata,const_buffer[479:0]}; // Top word won't be in const_buffer
packet_data <= {wdata,const_buffer[479:0]}; // Top word won't be in const_buffer
// - until next cycle to splice it in to out data combinatorially
// Calculate Last Flag
data_out_last <= (addr[ADDRWIDTH-1:6] == 5'h1F) ? 1'b1 : 1'b0;
packet_data_last <= (addr[ADDRWIDTH-1:6] == 5'h1F) ? 1'b1 : 1'b0;
// Take Valid High
data_out_valid <= 1'b1;
packet_data_valid <= 1'b1;
// Reset Construction Buffer
const_buffer <= 512'd0;
const_buffer <= 512'd0;
end
end
end
......@@ -103,8 +103,7 @@ end
// Register Ready Control
always_comb begin
rready = 1'b1; // Always able to read - may return 0
// wready = ~((data_out_valid && ~data_out_ready) && (addr[5:2] == 4'hF));
wready = ~((data_out_valid && ~data_out_ready) && (((addr >> 2) & 11'hF) == 11'hF));
wready = ~((packet_data_valid && ~packet_data_ready) && (((addr >> 2) & 11'hF) == 11'hF));
end
endmodule
\ No newline at end of file
hdl/src/wrapper_packet_deconstruct.sv
+ 13
− 13
View file @ f5484458
......@@ -27,10 +27,10 @@ module wrapper_packet_deconstruct #(
output logic rready,
// Valid/Ready interface
input logic [PACKETWIDTH-1:0] data_in,
input logic data_in_last,
input logic data_in_valid,
output logic data_in_ready
input logic [PACKETWIDTH-1:0] packet_data,
input logic packet_data_last,
input logic packet_data_valid,
output logic packet_data_ready
);
// Create Deconstruction Buffer
......@@ -62,28 +62,28 @@ always_ff @(posedge hclk or negedge hresetn) begin
// Reset Construction Buffer
deconst_buf <= {PACKETWIDTH{1'b0}};
// Reset Values
data_in_ready <= 1'b0;
packet_data_ready <= 1'b0;
deconst_buf_valid <= 1'b0;
deconst_buf_flag <= {(PACKETWIDTH/32){1'b0}};
end else begin
// If ready is low and theres no valid data in buffer, asser ready
if (!data_in_ready && !deconst_buf_valid) begin
data_in_ready <= 1'b1;
if (!packet_data_ready && !deconst_buf_valid) begin
packet_data_ready <= 1'b1;
end
// Read Packet into Deconstruction Buffer
if (data_in_valid && data_in_ready) begin
data_in_ready <= 1'b0;
deconst_buf <= data_in;
if (packet_data_valid && packet_data_ready) begin
packet_data_ready <= 1'b0;
deconst_buf <= packet_data;
deconst_buf_valid <= 1'b1;
deconst_buf_flag <= {(PACKETWIDTH/32){1'b0}};
end
if (read_en) begin
// Register which words in the Deconstruction buffer have been read
// Check if All Words have been Read
if (deconst_buf_flag_reduced && !(data_in_valid && data_in_ready)) begin
if (deconst_buf_flag_reduced && !(packet_data_valid && packet_data_ready)) begin
// Set Ready High To Get more Data into Buffer
deconst_buf_valid <= 1'b0;
data_in_ready <= 1'b1;
packet_data_ready <= 1'b1;
end else begin
deconst_buf_flag <= deconst_buf_flag | cur_deconst_buf_flag;
end
......@@ -104,7 +104,7 @@ end
// Register Ready Control
always_comb begin
// Not Ready Out when waiting for Valid Data on Input
rready = ~data_in_ready;
rready = ~packet_data_ready;
// Write Ready always high but doesn't do anywthing
wready = 1'b1;
end
......
hdl/src/wrapper_top.sv → hdl/src/wrapper_sha256_hashing_stream.sv
+ 48
− 36
View file @ f5484458
//-----------------------------------------------------------------------------
// SoC Labs Basic Top-level Accelerator Wrapper
// SoC Labs Basic Accelerator Wrapper for Hashing Stream
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
......@@ -39,8 +39,9 @@
`include "wrapper_packet_construct.sv"
`include "wrapper_packet_deconstruct.sv"
`include "wrapper_ahb_interface.sv"
`include "sha256_hashing_stream.sv"
module wrapper_top #(
module wrapper_sha256_hashing_stream #(
parameter ADDRWIDTH=12 // Peripheral Address Width
)(
input logic HCLK, // Clock
......@@ -59,8 +60,7 @@ module wrapper_top #(
output logic HRESPS,
output logic [31:0] HRDATAS
);
// ----------------------------------------
// Internal wires declarations
......@@ -93,22 +93,17 @@ module wrapper_top #(
logic output_rready;
// Internal Wiring
logic [511:0] packet_data_out;
logic packet_data_out_last;
logic packet_data_out_valid;
logic packet_data_out_ready;
logic [511:0] in_packet;
logic in_packet_last;
logic in_packet_valid;
logic in_packet_ready;
// Internal Wiring
logic [511:0] packet_data_in;
logic packet_data_in_last;
logic packet_data_in_valid;
logic packet_data_in_ready;
// Test Wire Assignments
assign packet_data_in = packet_data_out;
assign packet_data_in_last = packet_data_out_last;
assign packet_data_in_valid = packet_data_out_valid;
assign packet_data_out_ready = packet_data_in_ready;
logic [256:0] out_packet;
logic out_packet_last;
logic out_packet_valid;
logic out_packet_ready;
//-----------------------------------------------------------
// Module logic start
//----------------------------------------------------------
......@@ -173,15 +168,41 @@ module wrapper_top #(
.rready (input_rready),
// Valid/Ready Interface
.data_out (packet_data_out),
.data_out_last (packet_data_out_last),
.data_out_valid (packet_data_out_valid),
.data_out_ready (packet_data_out_ready)
.packet_data (in_packet),
.packet_data_last (in_packet_last),
.packet_data_valid (in_packet_valid),
.packet_data_ready (in_packet_ready)
);
sha256_hashing_stream u_sha256_hashing_stream (
.clk (clk),
.nrst (nrst),
.en (1'b1),
.sync_rst (1'b0),
// Data in Channel
.data_in (in_packet),
.data_in_valid (in_packet_valid),
.data_in_ready (in_packet_ready),
.data_in_last (in_packet_last),
// Config In Channel
.cfg_size (cfg_size),
.cfg_scheme (cfg_scheme),
.cfg_last (cfg_last),
.cfg_valid (cfg_valid),
.cfg_ready (cfg_ready),
// Data Out Channel
.data_out (out_packet),
.data_out_last (out_packet_last),
.data_out_valid (out_packet_valid),
.data_out_ready (out_packet_ready)
);
wrapper_packet_deconstruct #(
(ADDRWIDTH - 1), // Only half address map allocated to this device
512 // Ouptut Packet WIdth
256 // Ouptut Packet WIdth
) u_wrapper_packet_deconstruct (
.hclk (HCLK),
.hresetn (HRESETn),
......@@ -197,24 +218,15 @@ module wrapper_top #(
.rready (output_rready),
// Valid/Ready Interface
.data_in (packet_data_in),
.data_in_last (packet_data_in_last),
.data_in_valid (packet_data_in_valid),
.data_in_ready (packet_data_in_ready)
.packet_data (out_packet),
.packet_data_last (out_packet_last),
.packet_data_valid (out_packet_valid),
.packet_data_ready (out_packet_ready)
);
//-----------------------------------------------------------
//Module logic end
//----------------------------------------------------------
//---------------------
//Test Logic
//---------------------
// assign data_out_ready = 1'b1;
// assign output_wready = 1'b1;
// assign output_rready = 1'b1;
// assign output_wready = 1'b1;
// assign output_rready = 1'b1;
`ifdef ARM_AHB_ASSERT_ON
`include "std_ovl_defines.h"
......
hdl/src/wrapper_vr_loopback.sv
+ 12
− 31
View file @ f5484458
......@@ -94,22 +94,11 @@ module wrapper_vr_loopback #(
logic output_rready;
// Internal Wiring
logic [511:0] packet_data_out;
logic packet_data_out_last;
logic packet_data_out_valid;
logic packet_data_out_ready;
logic [511:0] packet;
logic packet_last;
logic packet_valid;
logic packet_ready;
// Internal Wiring
logic [511:0] packet_data_in;
logic packet_data_in_last;
logic packet_data_in_valid;
logic packet_data_in_ready;
// Test Wire Assignments
assign packet_data_in = packet_data_out;
assign packet_data_in_last = packet_data_out_last;
assign packet_data_in_valid = packet_data_out_valid;
assign packet_data_out_ready = packet_data_in_ready;
//-----------------------------------------------------------
// Module logic start
//----------------------------------------------------------
......@@ -174,10 +163,10 @@ module wrapper_vr_loopback #(
.rready (input_rready),
// Valid/Ready Interface
.data_out (packet_data_out),
.data_out_last (packet_data_out_last),
.data_out_valid (packet_data_out_valid),
.data_out_ready (packet_data_out_ready)
.packet_data (packet),
.packet_data_last (packet_last),
.packet_data_valid (packet_valid),
.packet_data_ready (packet_ready)
);
wrapper_packet_deconstruct #(
......@@ -198,24 +187,16 @@ module wrapper_vr_loopback #(
.rready (output_rready),
// Valid/Ready Interface
.data_in (packet_data_in),
.data_in_last (packet_data_in_last),
.data_in_valid (packet_data_in_valid),
.data_in_ready (packet_data_in_ready)
.packet_data (packet),
.packet_data_last (packet_last),
.packet_data_valid (packet_valid),
.packet_data_ready (packet_ready)
);
//-----------------------------------------------------------
//Module logic end
//----------------------------------------------------------
//---------------------
//Test Logic
//---------------------
// assign data_out_ready = 1'b1;
// assign output_wready = 1'b1;
// assign output_rready = 1'b1;
// assign output_wready = 1'b1;
// assign output_rready = 1'b1;
`ifdef ARM_AHB_ASSERT_ON
`include "std_ovl_defines.h"
......
hdl/verif/tb_wrapper_top.sv → hdl/verif/tb_wrapper_sha256_hashing_stream.sv
+ 5
− 5
View file @ f5484458
......@@ -40,11 +40,11 @@
`include "cmsdk_ahb_fileread_master32.v"
`include "cmsdk_ahb_default_slave.v"
`include "cmsdk_ahb_slave_mux.v"
`include "wrapper_top.sv"
`include "wrapper_sha256_hashing_stream.sv"
`timescale 1ns/1ps
module tb_wrapper_top;
module tb_wrapper_sha256_hashing_stream;
parameter CLK_PERIOD = 10;
parameter ADDRWIDTH = 12;
......@@ -94,8 +94,8 @@ reg HRESETn;
initial
begin
$dumpfile("wrapper_top.vcd");
$dumpvars(0, tb_wrapper_top);
$dumpfile("wrapper_sha256_hashing_stream.vcd");
$dumpvars(0, tb_wrapper_sha256_hashing_stream);
HRESETn = 1'b0;
HCLK = 1'b0;
# (10*CLK_PERIOD);
......@@ -221,7 +221,7 @@ cmsdk_ahb_fileread_master32 #(InputFileName,
//********************************************************************************
// Slave module 1: example AHB slave module
//********************************************************************************
wrapper_top #(ADDRWIDTH
wrapper_sha256_hashing_stream #(ADDRWIDTH
) accelerator (
.HCLK (HCLK),
.HRESETn (HRESETn),
......
hdl/verif/tb_wrapper_vr_loopback.sv
+ 1
− 1
View file @ f5484458
//-----------------------------------------------------------------------------
// SoC Labs Basic Testbench for Top-level AHB Wrapper
// SoC Labs Basic Testbench for Wrapper Valid-Ready Loopback Test
// Modified from tb_frbm_example.v
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment