Merge branch 'feat_nanosoc_regions' into 'main'

Changed set_env flow to source script in soctools and breadcrumb left in...

See merge request !1

.gitignore

+# Simulation Related File Removal
 *.vcd
 *.vvp
 simulate/sim/*
+lint/*
 .socinit
 accelerator/html/*
 wrapper/html/*
-system/src/bootrom
+system/src/bootrom/*
+system/src/defines/*
 system/html/*
 flist/tmp
+
+# Compile Test Code Removal
+/system/testcodes/*/*.elf
+/system/testcodes/*/*.ELF
+/system/testcodes/*/*.hex
+/system/testcodes/*/*.lst
+/system/testcodes/*/*.o
+/system/testcodes/*/*.bin
+
+# Remove Implementation Files
+imp/fpga/*
+html
\ No newline at end of file

.gitlab-ci.yml

+# This file is a template, and might need editing before it works on your project.
+# This is a sample GitLab CI/CD configuration file that should run without any modifications.
+# It demonstrates a basic 3 stage CI/CD pipeline. Instead of real tests or scripts,
+# it uses echo commands to simulate the pipeline execution.
+#
+# A pipeline is composed of independent jobs that run scripts, grouped into stages.
+# Stages run in sequential order, but jobs within stages run in parallel.
+#
+# For more information, see: https://docs.gitlab.com/ee/ci/yaml/index.html#stages
+#
+# You can copy and paste this template into a new `.gitlab-ci.yml` file.
+# You should not add this template to an existing `.gitlab-ci.yml` file by using the `include:` keyword.
+#
+# To contribute improvements to CI/CD templates, please follow the Development guide at:
+# https://docs.gitlab.com/ee/development/cicd/templates.html
+# This specific template is located at:
+# https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml
+
+stages:          # List of stages for jobs, and their order of execution
+  - simulate
+  - build
+  - deploy
+
+variables:
+  GIT_SUBMODULE_STRATEGY: recursive
+  GIT_SUBMODULE_FORCE_HTTPS: "true"
+
+
+simulate-nanosoc:
+  stage: simulate
+  script:
+    - echo "Simulation phase started"
+    - git submodule foreach --recursive git submodule init
+    - git fetch --recurse-submodules
+    - source set_env.sh
+    - sleep 5
+  tags:
+    - VLAB-ZCU
+
+
+build-job-Z2:       # This job runs in the build stage, which runs first.
+  stage: build
+  script:
+    # move to fpga_imp directory and run the fpga build script for pynq z2
+    - git submodule foreach --recursive git submodule init
+    - git fetch --recurse-submodules
+    - source set_env.sh
+    - cd ./nanosoc_tech/fpga/
+    - make build_fpga FPGA=z2
+    - FILE=../../imp/fpga/output/pynq_z2/overlays/nanosoc_design.bit 
+    - if test -f "$FILE"; then
+    -   echo "Build successful"
+    - else
+    -   echo "Build failed"
+    -   exit 1
+    - fi
+  artifacts:
+    paths:
+      # Keep the generated bit and hwh file from fpga build script
+      - ./imp/fpga/output/pynq_z2/overlays/nanosoc_design.bit 
+      - ./imp/fpga/output/pynq_z2/overlays/nanosoc_design.hwh
+  tags:
+    - Vivado2021.1
+
+build-job-ZCU104:       # This job runs in the build stage, which runs first.
+  stage: build
+  script:
+   # move to fpga_imp directory and run the fpga build script for pynq z2 
+    - git submodule foreach --recursive git submodule init
+    - git fetch --recurse-submodules
+    - source set_env.sh
+    - cd ./nanosoc_tech/fpga
+    - make build_fpga FPGA=zcu104
+    - FILE=../../imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit 
+    - if test -f "$FILE"; then
+    -   echo "Build successful"
+    - else
+    -   echo "Build failed"
+    -   exit 1
+    - fi
+  artifacts:
+    paths:
+    # Keep the generated bit and hwh file from fpga build script
+      - ./imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit 
+      - ./imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.hwh 
+  tags:
+    - Vivado2021.1
+
+#deploy-job-Z2:      # This job runs in the deploy stage.
+#  stage: deploy  # It only runs when *both* jobs in the test stage complete successfully.
+#  environment: production
+#  script:
+#    - echo "Deploying application to Z2"
+#    # use smbclient to transfer accross the bit, hwh and python script files to the z2 xilinx board
+#    # could probably set this up as scp with RSA keys in future
+#    - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./nanosoc/fpga_imp/pynq_export/pz2/pynq/overlays/#soclabs/design_1.bit ./design_1.bit' -E 2>errorlog
+#    - if (grep -r "Connection to 192.168.2.99 failed" ./errorlog)
+#    - then
+#    -   echo "Connection to Z2 Board Failed"
+#    -   exit 1
+#    - else
+#    -   echo "Connection to Z2 Board successful"
+#    - fi
+#    - rm errorlog
+#    - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./nanosoc/fpga_imp/pynq_export/pz2/pynq/overlays/#soclabs/design_1.hwh ./design_1.hwh' -E 2>errorlog
+#    - if (grep -r "Connection to 192.168.2.99 failed" ./errorlog)
+#    - then
+#    -   echo "Connection to Z2 Board Failed"
+#    -   exit 1
+#    - else
+#    -   echo "Connection to Z2 Board successful"
+#    - fi
+#    - rm errorlog
+#    - cd ./nanosoc/fpga_imp/CI_verification
+#    - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'put ./load_bitfile.py ./load_bitfile.py' -E 2>errorlog
+#    - if (grep -r "Connection to 192.168.2.99 failed" ./errorlog)
+#    - then
+#    -   echo "Connection to Z2 Board Failed"
+#    -   exit 1
+#    - else
+#    -   echo "Connection to Z2 Board successful"
+#    - fi
+#    - rm errorlog
+#    # get root access on host machine, this was found to be needed because other screen would not work
+#    # however a more elegant solution would be better
+#    - echo gitrunner1 | sudo -S su
+#    # open detatched terminal with connection to the Xilinx Z2 board
+#    - sudo screen -S zynq -dm /dev/ttyUSB1 115200
+#    # get root access on xilinx board, this is needed because the python script won't run without
+#    # being root. 
+#    - sudo screen -r zynq -X stuff "sudo -S su \n"
+#    # setup pynq environment 
+#    - sudo screen -r zynq -X stuff "source /etc/profile.d/pynq_venv.sh \n"
+#    - sudo screen -r zynq -X stuff "source /etc/profile.d/xrt_setup.sh \n"
+#    - sudo screen -r zynq -X stuff "source /etc/profile.d/boardname.sh \n"
+#    # run load_bitfile: this loads the overlay and checks that it has been loaded
+#    # script will output "Overlay Loaded" if successful
+#    - sudo screen -r zynq -X stuff "python3 load_bitfile.py > tmp \n"
+#    # sleep 1 minute: this is needed as currently the terminal running the CI/CD script will not wait
+#    # for the python script to finish. A more elegant solution should be implemented in future
+#    - sleep 60
+#    # copy over the tmp file back to host machine and check if "Overlay Loaded" has been outputed f
+#    - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'get tmp'
+#    - if (grep -r "Overlay Loaded" ./tmp)
+#    - then
+#    -   echo "Bit file loaded successfully"
+#    - else
+#    -   echo "Bit file load failed"
+#    -   exit 1
+#    - fi
+#  after_script:
+#    # cleanup: remove detached terminal screen
+#    - echo gitrunner1 | sudo -S su
+#    - sudo screen -X -S zynq quit
+#  tags:
+#    - Z2
+
+deploy-job-ZCU104:      # This job runs in the deploy stage.
+  stage: deploy  # It only runs when *both* jobs in the test stage complete successfully.
+  environment: production
+  script:
+    - echo "Deploying application to ZCU104"
+    # start a detached terminal so that the xilinx environment can be opened without interferring w
+    - screen -dmS zynq -L -Logfile screenlog
+    - sleep 5
+    # copy over vlab.py and vkey and then connect to ZCU104 board
+    # FUTURE Work: need to add error handling for if the board does not connect, 
+    # could grep from screenlog to see if successfully connected
+    - screen -r zynq -X stuff "cp -r /home/dwn1c21/FPGA/. ./ \n"
+    - screen -r zynq -X stuff "./ZCU104_connect.sh\n"
+    - sleep 10
+    # use scp to copy over bit files and python script
+    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/aes-128-project/nanosoc_tech/fpga/ci_tools/load_bitfile.py ./ \n"
+    - sleep 2
+    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/aes-128-project/imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit ./pynq/overlays/soclabs/design_1.bit \n"
+    - sleep 2
+    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/aes-128-project/imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.hwh ./pynq/overlays/soclabs/design_1.hwh \n"
+    - sleep 2
+    # Need root access to load the overlay onto the FPGA
+    - screen -r zynq -X stuff "sudo su\n"
+    - sleep 1
+    - screen -r zynq -X stuff "xilinx\n"
+    - screen -r zynq -X stuff "source /etc/profile.d/pynq_venv.sh \n"
+    - screen -r zynq -X stuff "source /etc/profile.d/xrt_setup.sh \n"
+    - screen -r zynq -X stuff "source /etc/profile.d/boardname.sh \n"
+    - sleep 5
+    # run load_bitfile: this loads the overlay and checks that it has been loaded
+    # script will output "Overlay Loaded" if successful
+    - screen -r zynq -X stuff "python3 load_bitfile.py \n"
+    - sleep 40
+    # deactivate the pynq virtual environment and exit root access
+    - screen -r zynq -X stuff "deactivate \n"
+    - screen -r zynq -X stuff "exit \n"
+    # test the screenlog for "Overlay Loaded"
+    - cp ./nanosoc/fpga_imp/CI_verification/test_bitfile_ZCU104.sh ./
+    - chmod +x test_bitfile_ZCU104.sh
+    - ./test_bitfile_ZCU104.sh
+
+  after_script:
+    # cleanup xilinx directories and quit screen
+    - screen -r zynq -X stuff "rm load_bitfile.py \n"
+    - screen -X -S zynq quit
+  tags:
+    - ZCU104
+    
+

.gitmodules

 [submodule "accelerator_wrapper_tech"]
 	path = accelerator_wrapper_tech
 	url = https://git.soton.ac.uk/soclabs/accelerator_wrapper_tech.git
+	branch = main
 [submodule "nanosoc_tech"]
 	path = nanosoc_tech
 	url = https://git.soton.ac.uk/soclabs/nanosoc_tech.git
+	branch = feat_nanosoc_regions
 [submodule "soctools_flow"]
 	path = soctools_flow
 	url = https://git.soton.ac.uk/soclabs/soctools_flow.git
+	branch = main
 [submodule "generic_lib_tech"]
 	path = generic_lib_tech
 	url = https://git.soton.ac.uk/soclabs/generic_lib_tech.git
+	branch = main
 [submodule "fpga_lib_tech"]
 	path = fpga_lib_tech
 	url = https://git.soton.ac.uk/soclabs/fpga_lib_tech.git
+	branch = main
 [submodule "rtl_primitives_tech"]
 	path = rtl_primitives_tech
 	url = https://git.soton.ac.uk/soclabs/rtl_primitives_tech.git
+	branch = main
+[submodule "secworks-aes"]
+	path = secworks-aes
+	url = https://github.com/secworks/aes.git
+	branch = master

.slprojroot

+#-----------------------------------------------------------------------------
+# SoC Labs Project Root Marker
+# - This file tells environment setter that this is root of a SoC Labs Project
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright  2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
\ No newline at end of file

README.md

 # Accelerator System Top-Level
 
-This repo is the top-level repository which contains accelerator and SoC Labs provided design IP in forms of git subrepositories.
+This repo is the top-level repository which contains an example accelerator based on the secworks AES engine integrated in SoC Labs provided nanosoc chip design IP in forms of git subrepositories.
 
 The SoC wiring is handled in this repository too, along with design and verification for accelerator wrappers.
 
-## Creating own top-level
+## Re-creating the top-level design
 
-The first stage of putting your accelerator into a SoC is to build the accelerator in your own repository. 
 
-Once you have a custom design repository, you are able to fork the template System Top-level repository and make some changes.
-
-After forking, you need to add your own repository as a submodule. The first thing to do is to clone your new forked top-level.
-
-## Cloning 
-
-To clone this repository and its subrepository, use the following command:
-
-`git clone --recusrive $REPO_NAME`
-
-Once the repository and the subrepository has been cloned, the next stage is to initalise the environment variables and check out the sub repositories to a branch.
-
-First navigate to the top of this cloned repository and run:
+Set up the environment variables and paths for this prohect:
 
 `source set_env.sh` 
 
-This sets the environment variables related to this project and creates visability to the scripts in the flow directory. Because of this, you scan now run:
-
-`soc-init`
-
-This checks out all the repositories to the `main` branch. You are then able to check out the sub repos to the desired branches.
-
-## Adding Submodule
-
-After setting up your workarea, you now need to add your accelerator design repository as a subrepo.
-
-From `$SOCLABS_DESIGN_ROOT`, you are able to run:
+This sets the environment variables related to this project and creates visability to the scripts in the flow directory. 
 
-`git submodule status` 
+## Running the simulation
 
-This lists the sub repositories and their branches. Make sure these are all you are expecting other than your design repo and you can then use the 
+This design instantiates a custom (AMBA-AHB) wrapper around the AES core to implement a memory-mapped 128-bit AES encrypt/decrypt accelerator that can be used as a software-driven peripheral or a semi-autonomous DMA subystem when 128-bit keys and variable length data payloads can be set up as scatter/gather descriptor chains for background processing.
 
-`git submodule add -b $BRANCH $REPOSITORY_URL`
+To run the simulation the 'socsim' command executes the makefile in the 'nanosoc_tech' microcontroller framework. (Edit the simulator target in nanosoc_tech/nanosoc/makefile for the simulator EDA tool used). Then use the 
 
-to add the repo into this work area.
+  `socsim system_aes128 TESTNAME=aes128_tests`
 
-You then need to push the .gitmodules file back to remote to save this configuration.
+This runs the integration test program on the Arm Cortex-M0 processor using the 'system_aes128.sh' script provided in the simulate/socsim directory and the logs are produced in the simulate/sim/system_aes128/logs directory.
\ No newline at end of file

accelerator_wrapper_tech @ 0748aa7d

-Subproject commit 33b0a1afab0d8d3279e9f6156a18d7b4954f9f5f
+Subproject commit 0748aa7d6c1186bf8195557eef230a95d2a7c53c

env/dependency_env.sh

@@ -15,7 +15,7 @@
 #-----------------------------------------------------------------------------
 
 # Accelerator Engine -- Add Your Accelerator Environment Variable HERE!
-# export YOUR_ACCELERATOR_DIR="$SOCLABS_PROJECT_DIR/your_accelerator"
+export ACCELERATOR_DIR="$SOCLABS_PROJECT_DIR/secworks-aes"
 
 # Accelerator Wrapper
 export SOCLABS_WRAPPER_TECH_DIR="$SOCLABS_PROJECT_DIR/accelerator_wrapper_tech"
@@ -23,6 +23,15 @@ export SOCLABS_WRAPPER_TECH_DIR="$SOCLABS_PROJECT_DIR/accelerator_wrapper_tech"
 # NanoSoC
 export SOCLABS_NANOSOC_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech"
 
+# SoCDebug
+export SOCLABS_SOCDEBUG_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech/nanosoc/socdebug_tech"
+
+# SLCore-M0
+export SOCLABS_SLCOREM0_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech/nanosoc/slcorem0_tech"
+
+# SLDMA-230
+export SOCLABS_SLDMA230_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech/nanosoc/sldma230_tech"
+
 # Primtives
 export SOCLABS_PRIMITIVES_TECH_DIR="$SOCLABS_PROJECT_DIR/rtl_primitives_tech"
 

flist/ahb/ahb_ip.flist

@@ -16,8 +16,8 @@
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog
+// CMSDK AHB Slave Mux IP
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v
 
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog
+// CMSDK AHB Default Slave IP
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
\ No newline at end of file

flist/project/wrapper.flist → flist/ahb/ahb_ip_qs.flist

 //-----------------------------------------------------------------------------
-// Accelerator Wrapper Filelist
+// Accelerator Wrapper CMSDK Filelist
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
@@ -9,20 +9,15 @@
 // Copyright � 2021-3, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 //-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Top-level Accelerator Wrapper
+// Abstract : Verilog Command File for Accelerator CMSDK AHB IP
 //-----------------------------------------------------------------------------
 
-// DESIGN_TOP your_wrapper
-
 // ============= Verilog library extensions ===========
 +libext+.v+.vlib
 
-// =============    Wrapper IP Filelist    ========================
--f $(SOCLABS_PROJECT_DIR)/flist/wrapper/wrapper_ip.flist
-
 // =============    Accelerator Module search path    =============
--y $(SOCLABS_PROJECT_DIR)/wrapper/src/
-+incdir+$(SOCLABS_PROJECT_DIR)/wrapper/src/
+// CMSDK AHB Slave Mux IP
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v
 
-// Add the source files related to your custom wrapper
-// $(SOCLABS_PROJECT_DIR)/wrapper/src/your_wrapper.v
+// CMSDK AHB Default Slave IP
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
\ No newline at end of file

flist/ahb/ahb_vip.flist

@@ -16,6 +16,7 @@
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog
-
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_filereadcore.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_funnel.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master32.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master64.v

flist/generic_lib/generic_lib_ip.flist → flist/ahb/ahb_vip_qs.flist

 //-----------------------------------------------------------------------------
-// Generic Library Filelist
+// Accelerator Wrapper CMSDK Filelist
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
@@ -9,17 +9,14 @@
 // Copyright � 2021-3, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 //-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Generic Library
+// Abstract : Verilog Command File for Accelerator CMSDK AHB VIP
 //-----------------------------------------------------------------------------
 
 // ============= Verilog library extensions ===========
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
-$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_INOUT8MA_NOE.v
-$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDIO.v
-$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSSIO.v
-$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDSOC.v
-$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSS.v
-$(SOCLABS_GENERIC_LIB_TECH_DIR)/mem/verilog/SROM_Ax32.v
-$(SOCLABS_GENERIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_filereadcore.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_funnel.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master32.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master64.v
\ No newline at end of file

flist/apb/apb_ip.flist

 //-----------------------------------------------------------------------------
-// Accelerator Wrapper CMSDK Filelist
+// CMSDK APB IP Filelist
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
@@ -15,13 +15,8 @@
 // ============= Verilog library extensions ===========
 +libext+.v+.vlib
 
-// =============    Accelerator Module search path    =============
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog
-
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave.v
+// =============    CMSDK APB IP search path    =============
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave.v

flist/nanosoc/nanosoc_test_io_ip.flist → flist/apb/apb_ip_qs.flist

 //-----------------------------------------------------------------------------
-// NanoSoC Chip Test Interface IP Filelist
+// CMSDK APB IP Filelist
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
@@ -9,13 +9,14 @@
 // Copyright � 2021-3, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 //-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for NanoSoC Chip Test Interface IP
+// Abstract : Verilog Command File for Accelerator CMSDK AHB IP
 //-----------------------------------------------------------------------------
 
 // ============= Verilog library extensions ===========
 +libext+.v+.vlib
 
-// =============    NanoSoC Chip Test Interface IP Filelists   =============
-$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_adp_control_v1_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_adp_manager.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v
+// =============    CMSDK APB IP search path    =============
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v
\ No newline at end of file
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave.v

flist/corstone-101/corstone-101_ip.flist

-//-----------------------------------------------------------------------------
-// NanoSoC Corstone-101 Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Arm Corstone-101
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// =============    Corstone-101 search path    =============
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
-
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog
\ No newline at end of file

flist/corstone-101/corstone-101_vip.flist

-//-----------------------------------------------------------------------------
-// NanoSoC Corstone-101 VIP Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Arm Corstone-101 VIP
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// =============    DMA-230 search path    =============
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
-
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
\ No newline at end of file

flist/cortex-m0/cortex-m0_ip.flist

-//-----------------------------------------------------------------------------
-// NanoSoC Cortex-M0 Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Arm Cortex-M0
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// =============    Accelerator Module search path    =============
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
-
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog

flist/nanosoc/nanosoc_chip_ip.flist

-//-----------------------------------------------------------------------------
-// NanoSoC Chip Related IP Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for NanoSoC Bus Matrix IP
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// =============    NanoSoC Bus Matrix IP search path    =============
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip_pads.v
-
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_cpu.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sysio.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sys_ahb_decode.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_subsystem.v
-
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_cs_rom_table.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_pin_mux.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_stclkctrl.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_clkctrl.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_sysctrl.v
-
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_usrt.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
\ No newline at end of file

flist/nanosoc/nanosoc_tb.flist

-//-----------------------------------------------------------------------------
-// NanoSoC Testbench Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for NanoSoC Testbench
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// =============    NanoSoC Testbench search path    =============
-+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/
-
-// - Top-level testbench
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_tb.v
-
-// - Testbench components
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_clkreset.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_uart_capture.v
-
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_track_tb_iostream.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_track.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
\ No newline at end of file

flist/primitives/primitives.flist

-//-----------------------------------------------------------------------------
-// Primitives Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for RTL Primitives
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// =============    RTL Primitives search path    =============
--y $(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/
-+incdir+$(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/
-
-$(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/fifo_vr.sv

flist/project/accelerator.flist

 //-----------------------------------------------------------------------------
-// Accelerator Filelist
+// Accelerator Subsystem Filelist
 //-----------------------------------------------------------------------------
 //-----------------------------------------------------------------------------
 // Abstract : This file contains a list of files and directories related to
-//            your accelerator.
+//            your accelerator. PLEASE MODIFY!!!
 //-----------------------------------------------------------------------------
 
-// DESIGN_TOP accelerator
+// DESIGN_TOP accelerator_subsystem
 
 // ============= Verilog library extensions ===========
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
+
+// ! Point this to your Accelerator RTL
++incdir+$(ACCELERATOR_DIR)/src/rtl
+
+// ! Point this to your Wrapper RTL
+$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
+
+// ! Point this to your Subsystem RTL
+$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
\ No newline at end of file