diff --git a/.gitignore b/.gitignore
index 842fc71a62a4b6fdbfad7ff5b7d5f6818694d117..62e6899e9d512af6aed2fbd977eafc1a1d05a989 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,9 +1,24 @@
+# Simulation Related File Removal
*.vcd
*.vvp
simulate/sim/*
+lint/*
.socinit
accelerator/html/*
wrapper/html/*
-system/src/bootrom
+system/src/bootrom/*
+system/src/defines/*
system/html/*
-flist/tmp
\ No newline at end of file
+flist/tmp
+
+# Compile Test Code Removal
+/system/testcodes/*/*.elf
+/system/testcodes/*/*.ELF
+/system/testcodes/*/*.hex
+/system/testcodes/*/*.lst
+/system/testcodes/*/*.o
+/system/testcodes/*/*.bin
+
+# Remove Implementation Files
+imp/fpga/*
+html
\ No newline at end of file
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
new file mode 100644
index 0000000000000000000000000000000000000000..a2ac7670955c8a43414219274879ab7f023a87a4
--- /dev/null
+++ b/.gitlab-ci.yml
@@ -0,0 +1,206 @@
+# This file is a template, and might need editing before it works on your project.
+# This is a sample GitLab CI/CD configuration file that should run without any modifications.
+# It demonstrates a basic 3 stage CI/CD pipeline. Instead of real tests or scripts,
+# it uses echo commands to simulate the pipeline execution.
+#
+# A pipeline is composed of independent jobs that run scripts, grouped into stages.
+# Stages run in sequential order, but jobs within stages run in parallel.
+#
+# For more information, see: https://docs.gitlab.com/ee/ci/yaml/index.html#stages
+#
+# You can copy and paste this template into a new `.gitlab-ci.yml` file.
+# You should not add this template to an existing `.gitlab-ci.yml` file by using the `include:` keyword.
+#
+# To contribute improvements to CI/CD templates, please follow the Development guide at:
+# https://docs.gitlab.com/ee/development/cicd/templates.html
+# This specific template is located at:
+# https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml
+
+stages: # List of stages for jobs, and their order of execution
+ - simulate
+ - build
+ - deploy
+
+variables:
+ GIT_SUBMODULE_STRATEGY: recursive
+ GIT_SUBMODULE_FORCE_HTTPS: "true"
+
+
+simulate-nanosoc:
+ stage: simulate
+ script:
+ - echo "Simulation phase started"
+ - git submodule foreach --recursive git submodule init
+ - git fetch --recurse-submodules
+ - source set_env.sh
+ - sleep 5
+ tags:
+ - VLAB-ZCU
+
+
+build-job-Z2: # This job runs in the build stage, which runs first.
+ stage: build
+ script:
+ # move to fpga_imp directory and run the fpga build script for pynq z2
+ - git submodule foreach --recursive git submodule init
+ - git fetch --recurse-submodules
+ - source set_env.sh
+ - cd ./nanosoc_tech/fpga/
+ - make build_fpga FPGA=z2
+ - FILE=../../imp/fpga/output/pynq_z2/overlays/nanosoc_design.bit
+ - if test -f "$FILE"; then
+ - echo "Build successful"
+ - else
+ - echo "Build failed"
+ - exit 1
+ - fi
+ artifacts:
+ paths:
+ # Keep the generated bit and hwh file from fpga build script
+ - ./imp/fpga/output/pynq_z2/overlays/nanosoc_design.bit
+ - ./imp/fpga/output/pynq_z2/overlays/nanosoc_design.hwh
+ tags:
+ - Vivado2021.1
+
+build-job-ZCU104: # This job runs in the build stage, which runs first.
+ stage: build
+ script:
+ # move to fpga_imp directory and run the fpga build script for pynq z2
+ - git submodule foreach --recursive git submodule init
+ - git fetch --recurse-submodules
+ - source set_env.sh
+ - cd ./nanosoc_tech/fpga
+ - make build_fpga FPGA=zcu104
+ - FILE=../../imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit
+ - if test -f "$FILE"; then
+ - echo "Build successful"
+ - else
+ - echo "Build failed"
+ - exit 1
+ - fi
+ artifacts:
+ paths:
+ # Keep the generated bit and hwh file from fpga build script
+ - ./imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit
+ - ./imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.hwh
+ tags:
+ - Vivado2021.1
+
+#deploy-job-Z2: # This job runs in the deploy stage.
+# stage: deploy # It only runs when *both* jobs in the test stage complete successfully.
+# environment: production
+# script:
+# - echo "Deploying application to Z2"
+# # use smbclient to transfer accross the bit, hwh and python script files to the z2 xilinx board
+# # could probably set this up as scp with RSA keys in future
+# - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./nanosoc/fpga_imp/pynq_export/pz2/pynq/overlays/#soclabs/design_1.bit ./design_1.bit' -E 2>errorlog
+# - if (grep -r "Connection to 192.168.2.99 failed" ./errorlog)
+# - then
+# - echo "Connection to Z2 Board Failed"
+# - exit 1
+# - else
+# - echo "Connection to Z2 Board successful"
+# - fi
+# - rm errorlog
+# - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./nanosoc/fpga_imp/pynq_export/pz2/pynq/overlays/#soclabs/design_1.hwh ./design_1.hwh' -E 2>errorlog
+# - if (grep -r "Connection to 192.168.2.99 failed" ./errorlog)
+# - then
+# - echo "Connection to Z2 Board Failed"
+# - exit 1
+# - else
+# - echo "Connection to Z2 Board successful"
+# - fi
+# - rm errorlog
+# - cd ./nanosoc/fpga_imp/CI_verification
+# - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'put ./load_bitfile.py ./load_bitfile.py' -E 2>errorlog
+# - if (grep -r "Connection to 192.168.2.99 failed" ./errorlog)
+# - then
+# - echo "Connection to Z2 Board Failed"
+# - exit 1
+# - else
+# - echo "Connection to Z2 Board successful"
+# - fi
+# - rm errorlog
+# # get root access on host machine, this was found to be needed because other screen would not work
+# # however a more elegant solution would be better
+# - echo gitrunner1 | sudo -S su
+# # open detatched terminal with connection to the Xilinx Z2 board
+# - sudo screen -S zynq -dm /dev/ttyUSB1 115200
+# # get root access on xilinx board, this is needed because the python script won't run without
+# # being root.
+# - sudo screen -r zynq -X stuff "sudo -S su \n"
+# # setup pynq environment
+# - sudo screen -r zynq -X stuff "source /etc/profile.d/pynq_venv.sh \n"
+# - sudo screen -r zynq -X stuff "source /etc/profile.d/xrt_setup.sh \n"
+# - sudo screen -r zynq -X stuff "source /etc/profile.d/boardname.sh \n"
+# # run load_bitfile: this loads the overlay and checks that it has been loaded
+# # script will output "Overlay Loaded" if successful
+# - sudo screen -r zynq -X stuff "python3 load_bitfile.py > tmp \n"
+# # sleep 1 minute: this is needed as currently the terminal running the CI/CD script will not wait
+# # for the python script to finish. A more elegant solution should be implemented in future
+# - sleep 60
+# # copy over the tmp file back to host machine and check if "Overlay Loaded" has been outputed f
+# - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'get tmp'
+# - if (grep -r "Overlay Loaded" ./tmp)
+# - then
+# - echo "Bit file loaded successfully"
+# - else
+# - echo "Bit file load failed"
+# - exit 1
+# - fi
+# after_script:
+# # cleanup: remove detached terminal screen
+# - echo gitrunner1 | sudo -S su
+# - sudo screen -X -S zynq quit
+# tags:
+# - Z2
+
+deploy-job-ZCU104: # This job runs in the deploy stage.
+ stage: deploy # It only runs when *both* jobs in the test stage complete successfully.
+ environment: production
+ script:
+ - echo "Deploying application to ZCU104"
+ # start a detached terminal so that the xilinx environment can be opened without interferring w
+ - screen -dmS zynq -L -Logfile screenlog
+ - sleep 5
+ # copy over vlab.py and vkey and then connect to ZCU104 board
+ # FUTURE Work: need to add error handling for if the board does not connect,
+ # could grep from screenlog to see if successfully connected
+ - screen -r zynq -X stuff "cp -r /home/dwn1c21/FPGA/. ./ \n"
+ - screen -r zynq -X stuff "./ZCU104_connect.sh\n"
+ - sleep 10
+ # use scp to copy over bit files and python script
+ - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/aes-128-project/nanosoc_tech/fpga/ci_tools/load_bitfile.py ./ \n"
+ - sleep 2
+ - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/aes-128-project/imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit ./pynq/overlays/soclabs/design_1.bit \n"
+ - sleep 2
+ - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/aes-128-project/imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.hwh ./pynq/overlays/soclabs/design_1.hwh \n"
+ - sleep 2
+ # Need root access to load the overlay onto the FPGA
+ - screen -r zynq -X stuff "sudo su\n"
+ - sleep 1
+ - screen -r zynq -X stuff "xilinx\n"
+ - screen -r zynq -X stuff "source /etc/profile.d/pynq_venv.sh \n"
+ - screen -r zynq -X stuff "source /etc/profile.d/xrt_setup.sh \n"
+ - screen -r zynq -X stuff "source /etc/profile.d/boardname.sh \n"
+ - sleep 5
+ # run load_bitfile: this loads the overlay and checks that it has been loaded
+ # script will output "Overlay Loaded" if successful
+ - screen -r zynq -X stuff "python3 load_bitfile.py \n"
+ - sleep 40
+ # deactivate the pynq virtual environment and exit root access
+ - screen -r zynq -X stuff "deactivate \n"
+ - screen -r zynq -X stuff "exit \n"
+ # test the screenlog for "Overlay Loaded"
+ - cp ./nanosoc/fpga_imp/CI_verification/test_bitfile_ZCU104.sh ./
+ - chmod +x test_bitfile_ZCU104.sh
+ - ./test_bitfile_ZCU104.sh
+
+ after_script:
+ # cleanup xilinx directories and quit screen
+ - screen -r zynq -X stuff "rm load_bitfile.py \n"
+ - screen -X -S zynq quit
+ tags:
+ - ZCU104
+
+
diff --git a/.gitmodules b/.gitmodules
index f5c1b168def62d7e50b5cae600d3da68f58a5c15..a8815a4ea4978303683375dee88b2ab9c6636155 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,18 +1,28 @@
[submodule "accelerator_wrapper_tech"]
path = accelerator_wrapper_tech
-url = https://git.soton.ac.uk/soclabs/accelerator_wrapper_tech.git
+ url = https://git.soton.ac.uk/soclabs/accelerator_wrapper_tech.git
+ branch = main
[submodule "nanosoc_tech"]
path = nanosoc_tech
-url = https://git.soton.ac.uk/soclabs/nanosoc_tech.git
+ url = https://git.soton.ac.uk/soclabs/nanosoc_tech.git
+ branch = feat_nanosoc_regions
[submodule "soctools_flow"]
path = soctools_flow
url = https://git.soton.ac.uk/soclabs/soctools_flow.git
+ branch = main
[submodule "generic_lib_tech"]
path = generic_lib_tech
url = https://git.soton.ac.uk/soclabs/generic_lib_tech.git
+ branch = main
[submodule "fpga_lib_tech"]
path = fpga_lib_tech
url = https://git.soton.ac.uk/soclabs/fpga_lib_tech.git
+ branch = main
[submodule "rtl_primitives_tech"]
path = rtl_primitives_tech
url = https://git.soton.ac.uk/soclabs/rtl_primitives_tech.git
+ branch = main
+[submodule "secworks-aes"]
+ path = secworks-aes
+ url = https://github.com/secworks/aes.git
+ branch = master
diff --git a/.slprojroot b/.slprojroot
new file mode 100644
index 0000000000000000000000000000000000000000..e88cb3343527fe89a1fdfc777745ce9a037b7456
--- /dev/null
+++ b/.slprojroot
@@ -0,0 +1,11 @@
+#-----------------------------------------------------------------------------
+# SoC Labs Project Root Marker
+# - This file tells environment setter that this is root of a SoC Labs Project
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright 2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
\ No newline at end of file
diff --git a/README.md b/README.md
index adaf8ae28806348d42a72d3a5bb10ff6a732fd4e..2fc1d2049bd067bd8ddc32d21f8b13b7b99d5def 100644
--- a/README.md
+++ b/README.md
@@ -1,47 +1,24 @@
# Accelerator System Top-Level
-This repo is the top-level repository which contains accelerator and SoC Labs provided design IP in forms of git subrepositories.
+This repo is the top-level repository which contains an example accelerator based on the secworks AES engine integrated in SoC Labs provided nanosoc chip design IP in forms of git subrepositories.
The SoC wiring is handled in this repository too, along with design and verification for accelerator wrappers.
-## Creating own top-level
+## Re-creating the top-level design
-The first stage of putting your accelerator into a SoC is to build the accelerator in your own repository.
-Once you have a custom design repository, you are able to fork the template System Top-level repository and make some changes.
-
-After forking, you need to add your own repository as a submodule. The first thing to do is to clone your new forked top-level.
-
-## Cloning
-
-To clone this repository and its subrepository, use the following command:
-
-`git clone --recusrive $REPO_NAME`
-
-Once the repository and the subrepository has been cloned, the next stage is to initalise the environment variables and check out the sub repositories to a branch.
-
-First navigate to the top of this cloned repository and run:
+Set up the environment variables and paths for this prohect:
`source set_env.sh`
-This sets the environment variables related to this project and creates visability to the scripts in the flow directory. Because of this, you scan now run:
-
-`soc-init`
-
-This checks out all the repositories to the `main` branch. You are then able to check out the sub repos to the desired branches.
-
-## Adding Submodule
-
-After setting up your workarea, you now need to add your accelerator design repository as a subrepo.
-
-From `$SOCLABS_DESIGN_ROOT`, you are able to run:
+This sets the environment variables related to this project and creates visability to the scripts in the flow directory.
-`git submodule status`
+## Running the simulation
-This lists the sub repositories and their branches. Make sure these are all you are expecting other than your design repo and you can then use the
+This design instantiates a custom (AMBA-AHB) wrapper around the AES core to implement a memory-mapped 128-bit AES encrypt/decrypt accelerator that can be used as a software-driven peripheral or a semi-autonomous DMA subystem when 128-bit keys and variable length data payloads can be set up as scatter/gather descriptor chains for background processing.
-`git submodule add -b $BRANCH $REPOSITORY_URL`
+To run the simulation the 'socsim' command executes the makefile in the 'nanosoc_tech' microcontroller framework. (Edit the simulator target in nanosoc_tech/nanosoc/makefile for the simulator EDA tool used). Then use the
-to add the repo into this work area.
+ `socsim system_aes128 TESTNAME=aes128_tests`
-You then need to push the .gitmodules file back to remote to save this configuration.
\ No newline at end of file
+This runs the integration test program on the Arm Cortex-M0 processor using the 'system_aes128.sh' script provided in the simulate/socsim directory and the logs are produced in the simulate/sim/system_aes128/logs directory.
\ No newline at end of file
diff --git a/accelerator_wrapper_tech b/accelerator_wrapper_tech
index 33b0a1afab0d8d3279e9f6156a18d7b4954f9f5f..0748aa7d6c1186bf8195557eef230a95d2a7c53c 160000
--- a/accelerator_wrapper_tech
+++ b/accelerator_wrapper_tech
@@ -1 +1 @@
-Subproject commit 33b0a1afab0d8d3279e9f6156a18d7b4954f9f5f
+Subproject commit 0748aa7d6c1186bf8195557eef230a95d2a7c53c
diff --git a/env/dependency_env.sh b/env/dependency_env.sh
index f76f37f14ffb6e1ed188dac99004a5f31aebd942..ffe841d4a237482660fb9aca17172e06268c2384 100755
--- a/env/dependency_env.sh
+++ b/env/dependency_env.sh
@@ -15,7 +15,7 @@
#-----------------------------------------------------------------------------
# Accelerator Engine -- Add Your Accelerator Environment Variable HERE!
-# export YOUR_ACCELERATOR_DIR="$SOCLABS_PROJECT_DIR/your_accelerator"
+export ACCELERATOR_DIR="$SOCLABS_PROJECT_DIR/secworks-aes"
# Accelerator Wrapper
export SOCLABS_WRAPPER_TECH_DIR="$SOCLABS_PROJECT_DIR/accelerator_wrapper_tech"
@@ -23,6 +23,15 @@ export SOCLABS_WRAPPER_TECH_DIR="$SOCLABS_PROJECT_DIR/accelerator_wrapper_tech"
# NanoSoC
export SOCLABS_NANOSOC_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech"
+# SoCDebug
+export SOCLABS_SOCDEBUG_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech/nanosoc/socdebug_tech"
+
+# SLCore-M0
+export SOCLABS_SLCOREM0_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech/nanosoc/slcorem0_tech"
+
+# SLDMA-230
+export SOCLABS_SLDMA230_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech/nanosoc/sldma230_tech"
+
# Primtives
export SOCLABS_PRIMITIVES_TECH_DIR="$SOCLABS_PROJECT_DIR/rtl_primitives_tech"
diff --git a/flist/ahb/ahb_ip.flist b/flist/ahb/ahb_ip.flist
index cc09e5740a211a1be9bf7c0d0836f9c3cfed5563..25495b56bbab3fba6304e6bd5aec6f1b17822815 100644
--- a/flist/ahb/ahb_ip.flist
+++ b/flist/ahb/ahb_ip.flist
@@ -16,8 +16,8 @@
+libext+.v+.vlib
// ============= Accelerator Module search path =============
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog
+// CMSDK AHB Slave Mux IP
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog
\ No newline at end of file
+// CMSDK AHB Default Slave IP
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
\ No newline at end of file
diff --git a/flist/project/wrapper.flist b/flist/ahb/ahb_ip_qs.flist
similarity index 60%
rename from flist/project/wrapper.flist
rename to flist/ahb/ahb_ip_qs.flist
index f553705071213a964e6b0cd98eb3143546c13462..086b01d88eb25b4fff13804474bc0ce8dbbe10ef 100644
--- a/flist/project/wrapper.flist
+++ b/flist/ahb/ahb_ip_qs.flist
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// Accelerator Wrapper Filelist
+// Accelerator Wrapper CMSDK Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
@@ -9,20 +9,15 @@
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Top-level Accelerator Wrapper
+// Abstract : Verilog Command File for Accelerator CMSDK AHB IP
//-----------------------------------------------------------------------------
-// DESIGN_TOP your_wrapper
-
// ============= Verilog library extensions ===========
+libext+.v+.vlib
-// ============= Wrapper IP Filelist ========================
--f $(SOCLABS_PROJECT_DIR)/flist/wrapper/wrapper_ip.flist
-
// ============= Accelerator Module search path =============
--y $(SOCLABS_PROJECT_DIR)/wrapper/src/
-+incdir+$(SOCLABS_PROJECT_DIR)/wrapper/src/
+// CMSDK AHB Slave Mux IP
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v
-// Add the source files related to your custom wrapper
-// $(SOCLABS_PROJECT_DIR)/wrapper/src/your_wrapper.v
+// CMSDK AHB Default Slave IP
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
\ No newline at end of file
diff --git a/flist/ahb/ahb_vip.flist b/flist/ahb/ahb_vip.flist
index 86e67d2772f42b00acb99e5c310df6d3c6d0ff20..162f68d5fd167523de2b5fad580e43ead87516f1 100644
--- a/flist/ahb/ahb_vip.flist
+++ b/flist/ahb/ahb_vip.flist
@@ -16,6 +16,7 @@
+libext+.v+.vlib
// ============= Accelerator Module search path =============
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog
-
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_filereadcore.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_funnel.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master32.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master64.v
diff --git a/flist/generic_lib/generic_lib_ip.flist b/flist/ahb/ahb_vip_qs.flist
similarity index 52%
rename from flist/generic_lib/generic_lib_ip.flist
rename to flist/ahb/ahb_vip_qs.flist
index 3995db36d85edb39185dc00bf9c6e92519ad6a1f..1789500ab765a93dc220bc974b73b8b44b46f093 100644
--- a/flist/generic_lib/generic_lib_ip.flist
+++ b/flist/ahb/ahb_vip_qs.flist
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// Generic Library Filelist
+// Accelerator Wrapper CMSDK Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
@@ -9,17 +9,14 @@
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Generic Library
+// Abstract : Verilog Command File for Accelerator CMSDK AHB VIP
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= Accelerator Module search path =============
-$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_INOUT8MA_NOE.v
-$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDIO.v
-$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSSIO.v
-$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDSOC.v
-$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSS.v
-$(SOCLABS_GENERIC_LIB_TECH_DIR)/mem/verilog/SROM_Ax32.v
-$(SOCLABS_GENERIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v
\ No newline at end of file
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_filereadcore.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_funnel.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master32.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master64.v
diff --git a/flist/apb/apb_ip.flist b/flist/apb/apb_ip.flist
index 24e608fc499ba3e7d2a19a25aa1c09e7cad2afd5..5c4d72466ffa9a70fa35427fe1263805b1d7cf5c 100644
--- a/flist/apb/apb_ip.flist
+++ b/flist/apb/apb_ip.flist
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// Accelerator Wrapper CMSDK Filelist
+// CMSDK APB IP Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
@@ -15,13 +15,8 @@
// ============= Verilog library extensions ===========
+libext+.v+.vlib
-// ============= Accelerator Module search path =============
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog
-
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave.v
+// ============= CMSDK APB IP search path =============
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave.v
diff --git a/flist/apb/apb_ip_qs.flist b/flist/apb/apb_ip_qs.flist
new file mode 100644
index 0000000000000000000000000000000000000000..dcf0915f90edb2e689ac8a86c4a9ef1fe3fbde13
--- /dev/null
+++ b/flist/apb/apb_ip_qs.flist
@@ -0,0 +1,22 @@
+//-----------------------------------------------------------------------------
+// CMSDK APB IP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Accelerator CMSDK AHB IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= CMSDK APB IP search path =============
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave.v
diff --git a/flist/corstone-101/corstone-101_ip.flist b/flist/corstone-101/corstone-101_ip.flist
deleted file mode 100644
index 60800f67280ad289a9ec194d023efb323097536c..0000000000000000000000000000000000000000
--- a/flist/corstone-101/corstone-101_ip.flist
+++ /dev/null
@@ -1,36 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC Corstone-101 Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Arm Corstone-101
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= Corstone-101 search path =============
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
-
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog
\ No newline at end of file
diff --git a/flist/corstone-101/corstone-101_vip.flist b/flist/corstone-101/corstone-101_vip.flist
deleted file mode 100644
index 1c64fa5d3d1e204c79637f2b0439f6be42c0a41a..0000000000000000000000000000000000000000
--- a/flist/corstone-101/corstone-101_vip.flist
+++ /dev/null
@@ -1,25 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC Corstone-101 VIP Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Arm Corstone-101 VIP
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= DMA-230 search path =============
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
-
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
\ No newline at end of file
diff --git a/flist/cortex-m0/cortex-m0_ip.flist b/flist/cortex-m0/cortex-m0_ip.flist
deleted file mode 100644
index 49a5afa4d06f259a081718493e20385becc91e42..0000000000000000000000000000000000000000
--- a/flist/cortex-m0/cortex-m0_ip.flist
+++ /dev/null
@@ -1,31 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC Cortex-M0 Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Arm Cortex-M0
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= Accelerator Module search path =============
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
-
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
diff --git a/flist/dma-230/pl230_ip.flist b/flist/dma-230/pl230_ip.flist
deleted file mode 100644
index 8c862a5c564d5835d00c8451d8b8e69d1e28c69f..0000000000000000000000000000000000000000
--- a/flist/dma-230/pl230_ip.flist
+++ /dev/null
@@ -1,26 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC DMA-230 Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Arm DMA-230
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= DMA-230 search path =============
-+incdir+$(SOCLABS_PROJECT_DIR)/system/defines/pl230
-
-$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_ahb_ctrl.v
-$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_apb_regs.v
-$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_dma_data.v
-$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_udma.v
-$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_undefs.v
-
diff --git a/flist/nanosoc/nanosoc_chip_ip.flist b/flist/nanosoc/nanosoc_chip_ip.flist
deleted file mode 100644
index fc7bb4af29cdef10727453778b943da7e9bdd32f..0000000000000000000000000000000000000000
--- a/flist/nanosoc/nanosoc_chip_ip.flist
+++ /dev/null
@@ -1,34 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC Chip Related IP Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for NanoSoC Bus Matrix IP
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= NanoSoC Bus Matrix IP search path =============
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip_pads.v
-
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_cpu.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sysio.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sys_ahb_decode.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_subsystem.v
-
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_cs_rom_table.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_pin_mux.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_stclkctrl.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_clkctrl.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_sysctrl.v
-
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_usrt.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
\ No newline at end of file
diff --git a/flist/nanosoc/nanosoc_matrix_ip.flist b/flist/nanosoc/nanosoc_matrix_ip.flist
deleted file mode 100644
index 00a82ce06798aea2b116a458884931e9381b19f9..0000000000000000000000000000000000000000
--- a/flist/nanosoc/nanosoc_matrix_ip.flist
+++ /dev/null
@@ -1,21 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC Bus Matrix IP Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for NanoSoC Bus Matrix IP
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= NanoSoC Bus Matrix IP search path =============
-+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix
-
--y $(SOCLABS_NANOSOC_TECH_DIR)/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix
\ No newline at end of file
diff --git a/flist/nanosoc/nanosoc_tb.flist b/flist/nanosoc/nanosoc_tb.flist
deleted file mode 100644
index 893b1b20d8f6dfea446790408650cc341ec6f705..0000000000000000000000000000000000000000
--- a/flist/nanosoc/nanosoc_tb.flist
+++ /dev/null
@@ -1,33 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC Testbench Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for NanoSoC Testbench
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= NanoSoC Testbench search path =============
-+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/
-
-// - Top-level testbench
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_tb.v
-
-// - Testbench components
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_clkreset.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_uart_capture.v
-
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_track_tb_iostream.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_track.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
\ No newline at end of file
diff --git a/flist/nanosoc/nanosoc_test_io_ip.flist b/flist/nanosoc/nanosoc_test_io_ip.flist
deleted file mode 100644
index 5df3c3dcb5d35605572b5e615909f89094b2062a..0000000000000000000000000000000000000000
--- a/flist/nanosoc/nanosoc_test_io_ip.flist
+++ /dev/null
@@ -1,21 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC Chip Test Interface IP Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for NanoSoC Chip Test Interface IP
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= NanoSoC Chip Test Interface IP Filelists =============
-$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_adp_control_v1_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_adp_manager.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v
\ No newline at end of file
diff --git a/flist/primitives/primitives.flist b/flist/primitives/primitives.flist
deleted file mode 100644
index bb0e871402821e9580b4bc395d92665ed92ec658..0000000000000000000000000000000000000000
--- a/flist/primitives/primitives.flist
+++ /dev/null
@@ -1,22 +0,0 @@
-//-----------------------------------------------------------------------------
-// Primitives Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for RTL Primitives
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= RTL Primitives search path =============
--y $(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/
-+incdir+$(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/
-
-$(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/fifo_vr.sv
diff --git a/flist/project/accelerator.flist b/flist/project/accelerator.flist
index a9d3db2dc3a46ea5ef527b4cfe2415f01681e1a4..2bf1f3cca8cefb5be849d385cfaed848cf9b789a 100644
--- a/flist/project/accelerator.flist
+++ b/flist/project/accelerator.flist
@@ -1,14 +1,23 @@
//-----------------------------------------------------------------------------
-// Accelerator Filelist
+// Accelerator Subsystem Filelist
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : This file contains a list of files and directories related to
-// your accelerator.
+// your accelerator. PLEASE MODIFY!!!
//-----------------------------------------------------------------------------
-// DESIGN_TOP accelerator
+// DESIGN_TOP accelerator_subsystem
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= Accelerator Module search path =============
+
+// ! Point this to your Accelerator RTL
++incdir+$(ACCELERATOR_DIR)/src/rtl
+
+// ! Point this to your Wrapper RTL
+$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
+
+// ! Point this to your Subsystem RTL
+$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
\ No newline at end of file
diff --git a/flist/project/system.flist b/flist/project/system.flist
index 22628425123d4fffeada2c9c72cc4b2d4bddf6b9..d5a2331282074eec794511815c9fdb51b3ac9ca6 100644
--- a/flist/project/system.flist
+++ b/flist/project/system.flist
@@ -12,56 +12,24 @@
// Abstract : Verilog Command File for Top-level Accelerator System
//-----------------------------------------------------------------------------
-// DESIGN_TOP nanosoc_chip
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
// ============= Accelerator Module search path =============
-// ! Point this to your accelerator filelist
-// -f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist
-
-// ============= Wrapper Filelist =========================
--f $(SOCLABS_PROJECT_DIR)/flist/project/wrapper.flist
+// ! Point this to your accelerator subsystem filelist
// ============= System Component Filelist ================
+// - Custom Accelerator Filelist
+-f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist
// - Primitives IP
--f $(SOCLABS_PROJECT_DIR)/flist/primitives/primitives.flist
-
-// - CMSDK IP
--f $(SOCLABS_PROJECT_DIR)/flist/ahb/ahb_ip.flist
--f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip.flist
-
-// - NanoSoC Chip IP
--f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_chip_ip.flist
-
-// - NanoSoC Bus Matrix
--f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_matrix_ip.flist
-
-// - NanoSoc Test Interface IP
--f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_test_io_ip.flist
+-f $(SOCLABS_PRIMITIVES_TECH_DIR)/flist/rtl_primitives_ip.flist
// - Generic Pad Library
--f $(SOCLABS_PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist
-
-// - CMSDK VIP
--f $(SOCLABS_PROJECT_DIR)/flist/corstone-101/corstone-101_vip.flist
-
-// - Corstone-101 System components
--f $(SOCLABS_PROJECT_DIR)/flist/corstone-101/corstone-101_ip.flist
-
-// - DMA controller
--f $(SOCLABS_PROJECT_DIR)/flist/dma-230/pl230_ip.flist
-
-// - Cortex-M0 IP
--f $(SOCLABS_PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist
+-f $(SOCLABS_GENERIC_LIB_TECH_DIR)/flist/generic_lib_ip.flist
-// - NanoSoC Custom Expansion Region
-$(SOCLABS_PROJECT_DIR)/system/src/nanosoc_exp.v
+// - FPGA sram
+-f $(SOCLABS_FPGA_LIB_TECH_DIR)/flist/fpga_lib_mem_ip.flist
-// - Top level
--f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist
+// - Accelerator Wrapper IP
+-f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
-// ============= Bootrom Filelist ================
+// - Bootrom Code RTL
$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file
diff --git a/flist/project/top.flist b/flist/project/top.flist
new file mode 100644
index 0000000000000000000000000000000000000000..c87d9bec9506e498c15bfcddee635d3463533e3b
--- /dev/null
+++ b/flist/project/top.flist
@@ -0,0 +1,35 @@
+//-----------------------------------------------------------------------------
+// Project Top-level Filelist System Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Top-level Accelerator System
+//-----------------------------------------------------------------------------
+
+// DESIGN_TOP nanosoc_chip
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= System Filelist =========================
+// - Defines RTL
++incdir+$(SOCLABS_PROJECT_DIR)/system/src/defines
+
+-f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist
+
+// NanoSoC Testbench
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_tb.flist
+
+// ============= Arm-IP Specific Filelists =========================
+// - NanoSoC Chip IP
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc.flist
+
+// - CMSDK IP
+-f $(SOCLABS_PROJECT_DIR)/flist/ahb/ahb_ip.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip.flist
\ No newline at end of file
diff --git a/flist/project/top_qs.flist b/flist/project/top_qs.flist
new file mode 100644
index 0000000000000000000000000000000000000000..669cdfb1750033c598188fc79db452aa2ce2bd64
--- /dev/null
+++ b/flist/project/top_qs.flist
@@ -0,0 +1,35 @@
+//-----------------------------------------------------------------------------
+// Project Top-level Filelist System Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Top-level Accelerator System
+//-----------------------------------------------------------------------------
+
+// DESIGN_TOP nanosoc_chip
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= System Filelist =========================
+// - Defines RTL
++incdir+$(SOCLABS_PROJECT_DIR)/system/src/defines
+
+-f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist
+
+// NanoSoC Testbench
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_tb_qs.flist
+
+// ============= Arm-IP Specific Filelists =========================
+// - NanoSoC Chip IP
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_qs.flist
+
+// - CMSDK IP
+-f $(SOCLABS_PROJECT_DIR)/flist/ahb/ahb_ip_qs.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip_qs.flist
\ No newline at end of file
diff --git a/flist/wrapper/wrapper_ip.flist b/flist/wrapper/wrapper_ip.flist
deleted file mode 100644
index 1e406b83de4b000401025601907afab9d4f1cdc2..0000000000000000000000000000000000000000
--- a/flist/wrapper/wrapper_ip.flist
+++ /dev/null
@@ -1,32 +0,0 @@
-//-----------------------------------------------------------------------------
-// Accelerator Wrapper Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Accelerator Wrapper IP
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= Accelerator Module search path =============
--y $(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/
-+incdir+$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/
-
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_constructor.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_deconstructor.sv
-
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_addr_calc.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_data_req.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_construct.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_deconstruct.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_req_ctrl_reg.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_dmac_req.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_valid_filter.sv
diff --git a/flow/adp_verify.py b/flow/adp_verify.py
deleted file mode 100644
index f2122bae70d9187cba8be3ad501657860cc2e868..0000000000000000000000000000000000000000
--- a/flow/adp_verify.py
+++ /dev/null
@@ -1,95 +0,0 @@
-#-----------------------------------------------------------------------------
-# ADP Command File Verification Script
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright � 2021-3, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-class address_region():
- def __init__(self, base, size):
- self.base = base
- self.size = size
- self.end = base + size - 4
-
-class read_word():
- def __init__(self, index, region, address, read_data = 0,exp_data = 0):
- self.index = index
- self.region = region
- self.address = int(str(address), 16)
- self.read_data = int(str(read_data), 16)
- self.exp_data = int(str(exp_data), 16)
-
- def validate(self):
- if (self.address >= self.region.base and self.address <= self.region.end):
- return True
- else:
- return False
-
- def check_address(self, address):
- # print(f"self: {hex(self.address)} test: {address}")
- if (self.address == int(str(address), 16)):
- return True
- else:
- return False
-
- def set_read_data(self, read_data):
- self.read_data = int(read_data, 16)
-
- def set_exp_data(self, exp_data):
- self.exp_data = int(exp_data, 16)
-
- def verify(self):
- assert (self.read_data == self.exp_data)
-
-def adp_verify(adp_input, adp_output, out_log):
- # Create Input Region for Accelerator
- accel_input_port = address_region(base = 0x6001_0000, size = 0x0000_0800)
- accel_output_port = address_region(base = 0x6001_0800, size = 0x0000_0800)
-
- word_list = []
- temp_address_buf = 0x0
-
- # Read in adp input
- adp_input_lines = open(adp_input, "r").readlines()
- idx = 0
- for line in adp_input_lines:
- line_split = str(line).split()
- if len(line_split) > 1:
- if line_split[0].lower() == "a":
- # Capture Address
- temp_address_buf = line_split[1]
- if line_split[0].lower() == "r":
- temp_read_word = read_word(idx, accel_output_port, temp_address_buf, exp_data = line_split[1])
- if temp_read_word.validate():
- word_list.append(temp_read_word)
- idx += 1
-
- # Read in adp output
- adp_output_lines = open(adp_output, "r").readlines()
- idx = 0
- temp_address_buf = 0x0
- for line in adp_output_lines:
- line_split = str(line).split()
- if len(line_split) > 1:
- if line_split[0] == "]A":
- # Capture Address
- temp_address_buf = line_split[1]
- if line_split[0] == "]R":
- if word_list[idx].check_address(temp_address_buf):
- word_list[idx].set_read_data(line_split[1])
- idx += 1
-
- # Perform Verification
- for word in word_list:
- word.verify()
- print(f"Tests Passed on {len(word_list)} reads")
-
-if __name__ == "__main__":
- adp_input = "ft1248_ip.log"
- adp_output = "ft1248_op.log"
- output_log = "verify.log"
- adp_verify(adp_input,adp_output,output_log)
diff --git a/flow/stimgen.py b/flow/stimgen.py
deleted file mode 100755
index 996b7384f7d1a509ecf535aa9f150f06a6a09dbc..0000000000000000000000000000000000000000
--- a/flow/stimgen.py
+++ /dev/null
@@ -1,214 +0,0 @@
-#!/usr/bin/env python
-
-import csv, os, tabulate
-from enum import Enum
-
-soclabs_header = """;#-----------------------------------------------------------------------------
-;# SoC Labs Basic Hashing Accelerator Wrapper Input Stimulus File
-;# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-;#
-;# Contributors
-;#
-;# David Mapstone (d.a.mapstone@soton.ac.uk)
-;#
-;# Copyright 2023, SoC Labs (www.soclabs.org)
-;#-----------------------------------------------------------------------------"""
-
-class TransactionType(Enum):
- """ Enumerated Types for Transaction Types for ASCII Debug """
- READ = 1
- WRITE = 2
- def __str__(self):
- if (self == TransactionType.READ):
- return "R"
- elif (self == TransactionType.WRITE):
- return "W"
-
-class TransactionSize(Enum):
- """ Enumerated Types for Transaction Types for ASCII Debug """
- WORD = 1
- HALFWORD = 2
- def __str__(self):
- if (self == TransactionSize.WORD):
- return "word"
- elif (self == TransactionSize.HALFWORD):
- return "halfword"
-
-class InputBlockStruct:
- def __init__(self):
- self.word_list = []
-
- def word_append(self, word):
- self.word_list.append(word)
-
-class InputPacketStruct:
- def __init__(self):
- self.block_list = []
-
- def block_append(self, block):
- self.block_list.append(block)
-
-class WordStruct:
- def __init__(self, data, addr, trans, packet_num = 0, block_num = 0, size = TransactionSize.WORD):
- self.data = data
- self.addr = addr
- self.trans = trans
- self.packet_num = packet_num
- self.block_num = block_num
- self.size = size
-
-def adp_output(out_file, word_list):
- """
- This function takes a list of 32 bit words and addresses and formats
- the data into .cmd format for the ADP module
- testbench
- """
-
- data = []
- for word in word_list:
- if (word.data > 0):
- data.append(["a", "{0:#0{1}x}".format(word.addr,10)])
- data.append([str(word.trans).lower(), "{0:#0{1}x}".format(word.data,10)])
-
- table_str = tabulate.tabulate(data, tablefmt="plain")
-
- with open(out_file, "w", encoding="UTF8", newline='') as f:
- f.write("A\n")
- f.write(table_str)
- f.write("\n A")
- f.write("\nX")
- f.write("\n!")
-
-def fri_output(out_file, word_list):
- """
- This function takes a list of 32 bit words and addresses and formats
- the data into .fri format to be fed into fml2conv.pl script to stimulate
- testbench
- """
-
- # Column Names
- col_names = ["Transaction", "Address", "Data", "Size"]
-
- data = []
- for word in word_list:
- if (word.data > 0):
- data.append([str(word.trans), "{0:#0{1}x}".format(word.addr,10), "{0:#0{1}x}".format(word.data,10), str(word.size)])
-
- table_str = tabulate.tabulate(data, headers=col_names, tablefmt="plain")
-
- with open(out_file, "w", encoding="UTF8", newline='') as f:
- f.write(soclabs_header + "\n;")
- f.write(table_str)
- f.write("\nQ") # Add End of Simulation Flag
-
-def stimulus_generation(stim_file, ref_file, input_start_address, input_size, output_start_address, output_size, gen_fri=True):
- """
- This function takes 32 bit input stimulus file from accelerator model,
- calculates write addresses for each word and generates a .fri file which
- can be used to stimulate an AHB testbench
- """
- fri_file = os.environ["SOCLABS_PROJECT_DIR"] + "/wrapper/stimulus/" + "ahb_input_hash_stim.fri"
-
- if gen_fri:
- # Calculate End Address
- input_end_address = input_start_address + input_size - 0x4
- # print(f"End Address is {hex(end_address)}")
-
- # Open Files
- with open(stim_file, "r") as stim:
- csvreader = csv.reader(stim, delimiter=",")
- stim_list = list(csvreader)
-
- with open(ref_file, "r") as ref:
- csvreader = csv.reader(ref, delimiter=",")
- ref_list = list(csvreader)
-
- # Initialise Packet Lists
- write_packet_list = []
- read_packet_list = []
-
- # Initialise Temporary Structures
- temppacketstruct = InputPacketStruct()
- tempblockstruct = InputBlockStruct()
-
- # Put Write Data into Structs
- for i in stim_list:
- tempblockstruct.word_append(int(i[0],16))
- # If Last Word in Block, Append to Packet and Reset Temporary block structure
- if (int(i[1])):
- temppacketstruct.block_append(tempblockstruct)
- tempblockstruct = InputBlockStruct()
- # If Last Block in Packet , Append Packet to Packet List and Reset Temp Packet
- if (int(i[2])):
- write_packet_list.append(temppacketstruct)
- temppacketstruct = InputPacketStruct()
-
- # Put Read Data into Structs
- for i in ref_list:
- tempblockstruct.word_append(int(i[0],16))
- # If Last Word in Block, Append to Packet and Reset Temporary block structure
- if (int(i[1])):
- temppacketstruct.block_append(tempblockstruct)
- tempblockstruct = InputBlockStruct()
- # If Last Block in Packet , Append Packet to Packet List and Reset Temp Packet
- if (int(i[2])):
- read_packet_list.append(temppacketstruct)
- temppacketstruct = InputPacketStruct()
-
-
- # List of Ouptut Transactions
- output_word_list = []
-
- # Generate Address for Packet
- for packet_num, write_packet in enumerate(write_packet_list):
- # Calculate Number of Blocks in First Packet
- num_blocks = len(write_packet.block_list)
- # Each Write Block Can Contain 16 32-bit Words (512 bits) (0x4 * 16 = 0x40)
- # - Work Out Required Size = (0x40 * NumBlocks)
- # - Work Out Beginning Address = (end_address + 0x4) - Size
- req_write_size = 0x40 * num_blocks
- start_write_addr = input_start_address + input_size - req_write_size
- # Each Read Block Contains 8 32-bit Words (256 bits) (0x4 * 8 = 0x20)
- req_read_size = 0x20
- start_read_addr = output_start_address + output_size - req_read_size
- # print(f"Packet: {int(packet_num)} | Start Address: {hex(start_write_addr)}")
- write_addr = start_write_addr
- read_addr = start_read_addr
- # Write out Packet containing multiple 512 bit Blocks to Input Port
- for block_num, block in enumerate(write_packet.block_list):
- for word in block.word_list:
- word_data = WordStruct(word, write_addr, TransactionType.WRITE, packet_num, block_num)
- output_word_list.append(word_data)
- # Increment Address
- write_addr += 0x4
- # Set Read Packet
- read_packet = read_packet_list[packet_num]
- # Read Back 256 Bit Packet from Output Port
- for block_num, block in enumerate(read_packet.block_list):
- for word in block.word_list:
- word_data = WordStruct(word, read_addr, TransactionType.READ, packet_num, 0)
- output_word_list.append(word_data)
- # Increment Address
- read_addr += 0x4
-
-
- # Generate ADP Command File with Write Transactions
- adp_file = os.environ["SOCLABS_PROJECT_DIR"] + "/system/stimulus/" + "adp_hash_stim.cmd"
- adp_output(adp_file, output_word_list)
-
- # Generate FRI File with Write Transactions
- fri_output(fri_file, output_word_list)
-
- # Call fm2conv.pl script
- m2d_file = os.environ["SOCLABS_PROJECT_DIR"] + "/wrapper/stimulus/" + "ahb_input_hash_stim.m2d"
- os.system(f"fm2conv.pl -busWidth=32 -infile={fri_file} -outfile={m2d_file}")
-
-
-if __name__ == "__main__":
- accelerator_input_address = 0x6001_0000
- accelerator_input_size = 0x0000_0400
- accelerator_output_address = 0x6001_0400
- accelerator_output_size = 0x0000_0400
- stim_file = os.environ["SOCLABS_PROJECT_DIR"] + "/wrapper/stimulus/" + "input_block_32bit_stim.csv"
- ref_file = os.environ["SOCLABS_PROJECT_DIR"] + "/wrapper/stimulus/" + "output_hash_32bit_ref.csv"
- stimulus_generation(stim_file, ref_file, accelerator_input_address, accelerator_input_size, accelerator_output_address, accelerator_output_size, gen_fri=False)
\ No newline at end of file
diff --git a/fpga_lib_tech b/fpga_lib_tech
index c51fa197a1d89ed556653fd7743c4aba20383b39..a49f272ade4fdbf04242ef63aa5262fbde746352 160000
--- a/fpga_lib_tech
+++ b/fpga_lib_tech
@@ -1 +1 @@
-Subproject commit c51fa197a1d89ed556653fd7743c4aba20383b39
+Subproject commit a49f272ade4fdbf04242ef63aa5262fbde746352
diff --git a/generic_lib_tech b/generic_lib_tech
index 53dca95d66a93333a7e6e8bbbda0696a348da0b5..9fe199f7c78d66e5a36b568996901b955717c8ab 160000
--- a/generic_lib_tech
+++ b/generic_lib_tech
@@ -1 +1 @@
-Subproject commit 53dca95d66a93333a7e6e8bbbda0696a348da0b5
+Subproject commit 9fe199f7c78d66e5a36b568996901b955717c8ab
diff --git a/nanosoc_tech b/nanosoc_tech
index 91ce5d7d85e099cdaf3194a97795c439c27fdd1c..4a29fd4d7d6349c973b8dab7e89b069883fff2ff 160000
--- a/nanosoc_tech
+++ b/nanosoc_tech
@@ -1 +1 @@
-Subproject commit 91ce5d7d85e099cdaf3194a97795c439c27fdd1c
+Subproject commit 4a29fd4d7d6349c973b8dab7e89b069883fff2ff
diff --git a/proj-branch b/projbranch
similarity index 89%
rename from proj-branch
rename to projbranch
index c8662e937f4d3be543ec54963a5166f6176f746a..c324fd1a322c7fbcb35aacd643adb64b90fdce48 100644
--- a/proj-branch
+++ b/projbranch
@@ -11,11 +11,11 @@
# Each Repo needs to have its branch set manually in here - they will defaultly be checked out to main
# Project Repository Subrepository Branch Index
# Add your Accelerator Repository here
-# accelerator_repo: main
-nanosoc_tech: main
+secworks-aes: master
+
+nanosoc_tech: feat_nanosoc_regions
accelerator_wrapper_tech: main
fpga_lib_tech: main
generic_lib_tech: main
rtl_primitives_tech: main
soctools_flow: main
-soctools_flow/tools/chipkit_flow: main
\ No newline at end of file
diff --git a/rtl_primitives_tech b/rtl_primitives_tech
index ce27da6f556a7dd20bcce213278e6f29b8d66332..a2e3f406afbdfb4a7a38438e2356c16a8756158e 160000
--- a/rtl_primitives_tech
+++ b/rtl_primitives_tech
@@ -1 +1 @@
-Subproject commit ce27da6f556a7dd20bcce213278e6f29b8d66332
+Subproject commit a2e3f406afbdfb4a7a38438e2356c16a8756158e
diff --git a/secworks-aes b/secworks-aes
new file mode 160000
index 0000000000000000000000000000000000000000..b9a3f1965b4e0568f0ca9b2d575ce6ea6fec2f36
--- /dev/null
+++ b/secworks-aes
@@ -0,0 +1 @@
+Subproject commit b9a3f1965b4e0568f0ca9b2d575ce6ea6fec2f36
diff --git a/set_env.sh b/set_env.sh
index 8304f5c4cd0707b5b64d8035f3736a7f86bcf08a..09a7a60cae14d922498d553f5326dc41f3c01a6f 100755
--- a/set_env.sh
+++ b/set_env.sh
@@ -10,63 +10,5 @@
#-----------------------------------------------------------------------------
#!/bin/bash
-# Get Root Location of Design Structure
-if [ -z $SOCLABS_DESIGN_ROOT ]; then
- # If $SOCLABS_DESIGN_ROOT hasn't been set yet
- SOCLABS_DESIGN_ROOT=`git rev-parse --show-superproject-working-tree`
-
- if [ -z $SOCLABS_DESIGN_ROOT ]; then
- # If not in a submodule - at root
- SOCLABS_DESIGN_ROOT=`git rev-parse --show-toplevel`
- fi
-
- # Source Top-Level Sourceme
- source $SOCLABS_DESIGN_ROOT/set_env.sh
-else
- # Set Environment Variable for this Repository
- export SOCLABS_PROJECT_DIR="$(cd -P "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
-
- # If this Repo is root of workspace
- if [ $SOCLABS_PROJECT_DIR = $SOCLABS_DESIGN_ROOT ]; then
- echo "Design Workspace: $SOCLABS_DESIGN_ROOT"
- export SOCLABS_DESIGN_ROOT
- fi
-
- # Add in location for socsim scripts
- export SOCLABS_SOCSIM_PATH=$SOCLABS_PROJECT_DIR/simulate/socsim
-
-
- # Source dependency environment variable script
- source $SOCLABS_PROJECT_DIR/env/dependency_env.sh
-
- # Add Scripts to Path
- # "TECH_DIR"
- while read line; do
- eval PATH="$PATH:\$${line}/flow"
- done <<< "$(awk 'BEGIN{for(v in ENVIRON) print v}' | grep TECH_DIR)"
-
- # "FLOW_DIR"
- while read line; do
- eval PATH="$PATH:\$${line}/tools"
- done <<< "$(awk 'BEGIN{for(v in ENVIRON) print v}' | grep FLOW_DIR)"
-
- # "SOCLABS_PROJECT_DIR"
- while read line; do
- eval PATH="$PATH:\$${line}/flow"
- done <<< "$(awk 'BEGIN{for(v in ENVIRON) print v}' | grep SOCLABS_PROJECT_DIR)"
-
- export PATH
-fi
-
-# Check cloned repository has been initialised
-if [ ! -f $SOCLABS_PROJECT_DIR/.socinit ]; then
- echo "Running First Time Repository Initialisation"
- # Source environment variables for all submodules
- cd $SOCLABS_DESIGN_ROOT
- git submodule update --remote --recursive
- git submodule foreach --recursive git checkout main
- # Read proj-branch file to find out which branch each subrepo needs to be on
- git config --file .gitmodules --get-regexp path | awk '{ print $2 }' | while read line; do cd $SOCLABS_PROJECT_DIR/$line && git checkout `grep $line $SOCLABS_PROJECT_DIR/proj-branch | awk '{ print $2 }'` && git pull; done
- git restore $SOCLABS_DESIGN_ROOT/.gitmodules
- touch $SOCLABS_PROJECT_DIR/.socinit
-fi
\ No newline at end of file
+# Source set_env script from soctools_flow
+source soctools_flow/bin/project_setup.sh
diff --git a/simulate/socsim/system_secworks_sha256.sh b/simulate/socsim/regression_aes128.sh
similarity index 81%
rename from simulate/socsim/system_secworks_sha256.sh
rename to simulate/socsim/regression_aes128.sh
index e7a53ab9224e8da9b18fbae3c5483b5d848bba0c..737c8ae3ac20a8dadf5f225d81560b2d081223f9 100755
--- a/simulate/socsim/system_secworks_sha256.sh
+++ b/simulate/socsim/regression_aes128.sh
@@ -19,13 +19,13 @@ SIM_DIR=$SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
# Create Directory to put simulation files
mkdir -p $SIM_DIR
-cd $SOCLABS_PROJECT_DIR/simulate/sim/system_secworks_sha256
+cd $SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
# Compile Simulation
# Call makefile in NanoSoC Repo with options
echo ${2}
-make -C $SOCLABS_NANOSOC_TECH_DIR/system run_xm \
+make -C $SOCLABS_NANOSOC_TECH_DIR regression_mti \
SIM_DIR=$SIM_DIR \
- ADP_FILE=$SOCLABS_PROJECT_DIR/system/stimulus/adp_hash_stim.cmd \
+ ACCELERATOR=yes \
${@:2}
diff --git a/simulate/socsim/bootrom.sh b/simulate/socsim/system_aes128.sh
similarity index 86%
rename from simulate/socsim/bootrom.sh
rename to simulate/socsim/system_aes128.sh
index f2357a61cc7e44da565333f510594b1176c32b79..1bfacd413d1a7326dee7254953312d535c2a755a 100755
--- a/simulate/socsim/bootrom.sh
+++ b/simulate/socsim/system_aes128.sh
@@ -19,11 +19,13 @@ SIM_DIR=$SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
# Create Directory to put simulation files
mkdir -p $SIM_DIR
-cd $SOCLABS_PROJECT_DIR/simulate/sim/system_secworks_sha256
+cd $SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
# Compile Simulation
# Call makefile in NanoSoC Repo with options
echo ${2}
-make -C $SOCLABS_NANOSOC_TECH_DIR/system bootrom \
+make -C $SOCLABS_NANOSOC_TECH_DIR run_mti \
SIM_DIR=$SIM_DIR \
+ ACCELERATOR=yes \
+ ${@:2}
diff --git a/simulate/socsim/wrapper_secworks_sha256.sh b/simulate/socsim/wrapper_secworks_sha256.sh
deleted file mode 100755
index 2ac6f8611376c1c35a35ab96d90819e3fb7b3026..0000000000000000000000000000000000000000
--- a/simulate/socsim/wrapper_secworks_sha256.sh
+++ /dev/null
@@ -1,37 +0,0 @@
-#-----------------------------------------------------------------------------
-# SoC Labs Simulation script for wrapper level verification testbench
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright 2022, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-#!/usr/bin/env bash
-
-# Generate Stimulus from stimulus generation Script
-# python3 $SECWORKS_SHA2_TECH_DIR/flow/stimgen.py
-# Create Simulatiom Directory to Run in
-mkdir -p $SOCLABS_PROJECT_DIR/simulate/sim/
-mkdir -p $SOCLABS_PROJECT_DIR/simulate/sim/wrapper_secworks_sha256
-
-cd $SOCLABS_PROJECT_DIR/simulate/sim/wrapper_secworks_sha256
-# Compile Simulation
-xrun \
- -64bit \
- -sv \
- -timescale 1ps/1ps \
- +access+r \
- -f $SOCLABS_PROJECT_DIR/flist/primatives.flist \
- -f $SOCLABS_PROJECT_DIR/flist/wrapper_ip.flist \
- -f $SOCLABS_PROJECT_DIR/flist/ahb_ip.flist \
- -f $SOCLABS_PROJECT_DIR/flist/apb_ip.flist \
- -f $SOCLABS_PROJECT_DIR/flist/wrapper.flist \
- -f $SOCLABS_PROJECT_DIR/flist/ahb_vip.flist \
- -f $SOCLABS_PROJECT_DIR/flist/secworks_sha25_stream.flist \
- -xmlibdirname $SOCLABS_PROJECT_DIR/simulate/sim/wrapper_secworks_sha256 \
- $SOCLABS_PROJECT_DIR/wrapper/verif/tb_wrapper_secworks_sha256.sv \
- -gui \
- -top tb_wrapper_secworks_sha256
\ No newline at end of file
diff --git a/soctools_flow b/soctools_flow
index e5b63d6e283f277a79947bcd4a616e4bf3ebadd9..348337022305cebea816cf80fb1eb8e5dd42632e 160000
--- a/soctools_flow
+++ b/soctools_flow
@@ -1 +1 @@
-Subproject commit e5b63d6e283f277a79947bcd4a616e4bf3ebadd9
+Subproject commit 348337022305cebea816cf80fb1eb8e5dd42632e
diff --git a/system/cpu_software/software_list.txt b/system/cpu_software/software_list.txt
deleted file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000
diff --git a/system/defines/pl230/pl230_defs.v b/system/defines/pl230/pl230_defs.v
deleted file mode 100644
index dcf4f1040e44f0b5ead58276a3367e5617e91c4a..0000000000000000000000000000000000000000
--- a/system/defines/pl230/pl230_defs.v
+++ /dev/null
@@ -1,189 +0,0 @@
-//-----------------------------------------------------------------------------
-// customised example Cortex-M0 controller DMA230 configuration
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright � 2021, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from ARM Limited.
-//
-// (C) COPYRIGHT 2006-2007 ARM Limited.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
-//
-// File Name : pl230_defs.v
-// Checked In : $Date: 2007-06-06 21:55:22 +0530 (Wed, 06 Jun 2007) $
-// Revision : $Revision: 13823 $
-// State : $state: PL230-DE-98007-r0p0-02rel0 $
-//
-//-----------------------------------------------------------------------------
-// Purpose : Peripheral specific macro definitions
-//
-//-----------------------------------------------------------------------------
-
-
-`ifdef ARM_TIMESCALE_DEFINED
- `timescale 1ns/1ps
-`endif
-
-// Set the number of channels implemented
-`define PL230_CHNLS 2
-`define PL230_CHNL_BITS 1
-//`define PL230_ONE_CHNL
-
-// Include Integration Test Logic
-`define PL230_INCLUDE_TEST
-
-
-// AHB Interface
-`define PL230_AHB_TRANS_IDLE 2'b00
-`define PL230_AHB_TRANS_NONSEQ 2'b10
-`define PL230_AHB_READ 1'b0
-`define PL230_AHB_WRITE 1'b1
-`define PL230_AHB_SIZE_BYTE 3'b000
-`define PL230_AHB_SIZE_HWORD 3'b001
-`define PL230_AHB_SIZE_WORD 3'b010
-
-// PrimeCell Configuration
-`define PL230_PERIPH_ID_0 8'h30
-`define PL230_PERIPH_ID_1 8'hB2
-`define PL230_PERIPH_ID_2 8'h0B
-`define PL230_PERIPH_ID_3 8'h00
-`define PL230_PERIPH_ID_4 8'h04
-`define PL230_PCELL_ID_0 8'h0D
-`define PL230_PCELL_ID_1 8'hF0
-`define PL230_PCELL_ID_2 8'h05
-`define PL230_PCELL_ID_3 8'hB1
-
-// Memory Mapped Registers
-// Controller Configuration Registers
-`define PL230_ADDR_DMA_STATUS 12'h000
-`define PL230_ADDR_DMA_CFG 12'h004
-`define PL230_ADDR_CTRL_BASE_PTR 12'h008
-`define PL230_ADDR_ALT_CTRL_BASE_PTR 12'h00C
-`define PL230_ADDR_DMA_WAITONREQ_STATUS 12'h010
-`define PL230_ADDR_CHNL_SW_REQUEST 12'h014
-`define PL230_ADDR_CHNL_USEBURST_SET 12'h018
-`define PL230_ADDR_CHNL_USEBURST_CLR 12'h01C
-`define PL230_ADDR_CHNL_REQ_MASK_SET 12'h020
-`define PL230_ADDR_CHNL_REQ_MASK_CLR 12'h024
-`define PL230_ADDR_CHNL_ENABLE_SET 12'h028
-`define PL230_ADDR_CHNL_ENABLE_CLR 12'h02C
-`define PL230_ADDR_CHNL_PRI_ALT_SET 12'h030
-`define PL230_ADDR_CHNL_PRI_ALT_CLR 12'h034
-`define PL230_ADDR_CHNL_PRIORITY_SET 12'h038
-`define PL230_ADDR_CHNL_PRIORITY_CLR 12'h03C
-// Reserved 12'h040
-// Reserved 12'h044
-// Reserved 12'h048
-`define PL230_ADDR_ERR_CLR 12'h04C
-// Integration Test Registers
-`define PL230_ADDR_INTEGRATION_CFG 12'hE00
-// Reserved 12'hE04
-`define PL230_ADDR_STALL_STATUS 12'hE08
-// Reserved 12'hE0C
-`define PL230_ADDR_DMA_REQ_STATUS 12'hE10
-// Reserved 12'hE14
-`define PL230_ADDR_DMA_SREQ_STATUS 12'hE18
-// Reserved 12'hE1C
-`define PL230_ADDR_DMA_DONE_SET 12'hE20
-`define PL230_ADDR_DMA_DONE_CLR 12'hE24
-`define PL230_ADDR_DMA_ACTIVE_SET 12'hE28
-`define PL230_ADDR_DMA_ACTIVE_CLR 12'hE2C
-// Reserved 12'hE30
-// Reserved 12'hE34
-// Reserved 12'hE38
-// Reserved 12'hE3C
-// Reserved 12'hE40
-// Reserved 12'hE44
-`define PL230_ADDR_ERR_SET 12'hE48
-// Reserved 12'hE4C
-// PrimeCell Configuration Registers
-`define PL230_ADDR_PERIPH_ID_4 12'hFD0
-// Reserved 12'hFD4
-// Reserved 12'hFD8
-// Reserved 12'hFDC
-`define PL230_ADDR_PERIPH_ID_0 12'hFE0
-`define PL230_ADDR_PERIPH_ID_1 12'hFE4
-`define PL230_ADDR_PERIPH_ID_2 12'hFE8
-`define PL230_ADDR_PERIPH_ID_3 12'hFEC
-`define PL230_ADDR_PCELL_ID_0 12'hFF0
-`define PL230_ADDR_PCELL_ID_1 12'hFF4
-`define PL230_ADDR_PCELL_ID_2 12'hFF8
-`define PL230_ADDR_PCELL_ID_3 12'hFFC
-
-
-// Bit vector definitions for channel_cfg
-`define PL230_CHANNEL_CFG_BITS 20
-// Destination address increment
-`define PL230_CHANNEL_CFG_DST_INC channel_cfg[19:18]
-`define PL230_HRDATA_DST_INC hrdata[31:30]
-// Destination transfer size
-// Source and destination sizes must match
-// so the same bits as the src_size are used
-`define PL230_CHANNEL_CFG_DST_SIZE channel_cfg[15:14]
-`define PL230_HRDATA_DST_SIZE hrdata[29:28]
-// Source address increment
-`define PL230_CHANNEL_CFG_SRC_INC channel_cfg[17:16]
-`define PL230_HRDATA_SRC_INC hrdata[27:26]
-// Source transfer size
-`define PL230_CHANNEL_CFG_SRC_SIZE channel_cfg[15:14]
-`define PL230_HRDATA_SRC_SIZE hrdata[25:24]
-// Destination AHB protection control
-`define PL230_CHANNEL_CFG_DST_PROT_CTRL channel_cfg[13:11]
-`define PL230_HRDATA_DST_PROT_CTRL hrdata[23:21]
-// Source AHB protection control
-`define PL230_CHANNEL_CFG_SRC_PROT_CTRL channel_cfg[10:8]
-`define PL230_HRDATA_SRC_PROT_CTRL hrdata[20:18]
-// Power of two transactions per request
-`define PL230_CHANNEL_CFG_R channel_cfg[7:4]
-`define PL230_HRDATA_R hrdata[17:14]
-// Number of bits in the N counter - hrdata[13:4]
-`define PL230_N_COUNT_BITS 10
-// Lsb bit offset for n_minus_1
-`define PL230_N_COUNT_OFFSET 4
-// Set chnl_useburst_status
-`define PL230_CHANNEL_CFG_NEXT_USEBURST channel_cfg[3]
-`define PL230_HRDATA_NEXT_USEBURST hrdata[3]
-// DMA cycle control
-`define PL230_CHANNEL_CFG_CYCLE_CTRL channel_cfg[2:0]
-`define PL230_HRDATA_CYCLE_CTRL hrdata[2:0]
-
-
-// Number of bits for the statemachine
-`define PL230_STATE_BITS 4
-// Statemachine state encoding
-`define PL230_ST_IDLE 4'h0
-`define PL230_ST_RD_CTRL 4'h1
-`define PL230_ST_RD_SPTR 4'h2
-`define PL230_ST_RD_DPTR 4'h3
-`define PL230_ST_RD_SDAT 4'h4
-`define PL230_ST_WR_DDAT 4'h5
-`define PL230_ST_WAIT 4'h6
-`define PL230_ST_WR_CTRL 4'h7
-`define PL230_ST_STALL 4'h8
-`define PL230_ST_DONE 4'h9
-`define PL230_ST_PSGP 4'hA
-`define PL230_ST_RESVD_0 4'hB
-`define PL230_ST_RESVD_1 4'hC
-`define PL230_ST_RESVD_2 4'hD
-`define PL230_ST_RESVD_3 4'hE
-`define PL230_ST_RESVD_4 4'hF
-
-`define PL230_SIZE_BYTE 2'b00
-`define PL230_SIZE_HWORD 2'b01
-`define PL230_SIZE_WORD 2'b10
-`define PL230_SIZE_RESVD 2'b11
-
-// pl230_defs.v end
diff --git a/system/defines/pl230/pl230_undefs.v b/system/defines/pl230/pl230_undefs.v
deleted file mode 100644
index 07223868feff9eff4930d29734b2b2e6292f6e38..0000000000000000000000000000000000000000
--- a/system/defines/pl230/pl230_undefs.v
+++ /dev/null
@@ -1,178 +0,0 @@
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from ARM Limited.
-//
-// (C) COPYRIGHT 2006-2007 ARM Limited.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
-//
-// File Name : pl230_undefs.v
-// Checked In : $Date: 2007-03-15 15:17:04 +0530 (Thu, 15 Mar 2007) $
-// Revision : $Revision: 10866 $
-// State : $state: PL230-DE-98007-r0p0-02rel0 $
-//
-//-----------------------------------------------------------------------------
-// Purpose : Undefine peripheral specific macro definitions
-//
-//-----------------------------------------------------------------------------
-
-
-
-
-
-
-// Set the number of channels implemented
-`undef PL230_CHNLS
-`undef PL230_CHNL_BITS
-`undef PL230_ONE_CHNL
-
-// Include Integration Test Logic
-`undef PL230_INCLUDE_TEST
-
-
-// AHB Interface
-`undef PL230_AHB_TRANS_IDLE
-`undef PL230_AHB_TRANS_NONSEQ
-`undef PL230_AHB_READ
-`undef PL230_AHB_WRITE
-`undef PL230_AHB_SIZE_BYTE
-`undef PL230_AHB_SIZE_HWORD
-`undef PL230_AHB_SIZE_WORD
-
-// PrimeCell Configuration
-`undef PL230_PERIPH_ID_0
-`undef PL230_PERIPH_ID_1
-`undef PL230_PERIPH_ID_2
-`undef PL230_PERIPH_ID_3
-`undef PL230_PERIPH_ID_4
-`undef PL230_PCELL_ID_0
-`undef PL230_PCELL_ID_1
-`undef PL230_PCELL_ID_2
-`undef PL230_PCELL_ID_3
-
-// Memory Mapped Registers
-// Controller Configuration Registers
-`undef PL230_ADDR_DMA_STATUS
-`undef PL230_ADDR_DMA_CFG
-`undef PL230_ADDR_CTRL_BASE_PTR
-`undef PL230_ADDR_ALT_CTRL_BASE_PTR
-`undef PL230_ADDR_DMA_WAITONREQ_STATUS
-`undef PL230_ADDR_CHNL_SW_REQUEST
-`undef PL230_ADDR_CHNL_USEBURST_SET
-`undef PL230_ADDR_CHNL_USEBURST_CLR
-`undef PL230_ADDR_CHNL_REQ_MASK_SET
-`undef PL230_ADDR_CHNL_REQ_MASK_CLR
-`undef PL230_ADDR_CHNL_ENABLE_SET
-`undef PL230_ADDR_CHNL_ENABLE_CLR
-`undef PL230_ADDR_CHNL_PRI_ALT_SET
-`undef PL230_ADDR_CHNL_PRI_ALT_CLR
-`undef PL230_ADDR_CHNL_PRIORITY_SET
-`undef PL230_ADDR_CHNL_PRIORITY_CLR
-// Reserved
-// Reserved
-// Reserved
-`undef PL230_ADDR_ERR_CLR
-// Integration Test Registers
-`undef PL230_ADDR_INTEGRATION_CFG
-// Reserved
-`undef PL230_ADDR_STALL_STATUS
-// Reserved
-`undef PL230_ADDR_DMA_REQ_STATUS
-// Reserved
-`undef PL230_ADDR_DMA_SREQ_STATUS
-// Reserved
-`undef PL230_ADDR_DMA_DONE_SET
-`undef PL230_ADDR_DMA_DONE_CLR
-`undef PL230_ADDR_DMA_ACTIVE_SET
-`undef PL230_ADDR_DMA_ACTIVE_CLR
-// Reserved
-// Reserved
-// Reserved
-// Reserved
-// Reserved
-// Reserved
-`undef PL230_ADDR_ERR_SET
-// Reserved
-// PrimeCell Configuration Registers
-`undef PL230_ADDR_PERIPH_ID_4
-// Reserved
-// Reserved
-// Reserved
-`undef PL230_ADDR_PERIPH_ID_0
-`undef PL230_ADDR_PERIPH_ID_1
-`undef PL230_ADDR_PERIPH_ID_2
-`undef PL230_ADDR_PERIPH_ID_3
-`undef PL230_ADDR_PCELL_ID_0
-`undef PL230_ADDR_PCELL_ID_1
-`undef PL230_ADDR_PCELL_ID_2
-`undef PL230_ADDR_PCELL_ID_3
-
-
-// Bit vector definitions for channel_cfg
-`undef PL230_CHANNEL_CFG_BITS
-// Destination address increment
-`undef PL230_CHANNEL_CFG_DST_INC
-`undef PL230_HRDATA_DST_INC
-// Destination transfer size
-// Source and destination sizes must match
-// so the same bits as the src_size are used
-`undef PL230_CHANNEL_CFG_DST_SIZE
-`undef PL230_HRDATA_DST_SIZE
-// Source address increment
-`undef PL230_CHANNEL_CFG_SRC_INC
-`undef PL230_HRDATA_SRC_INC
-// Source transfer size
-`undef PL230_CHANNEL_CFG_SRC_SIZE
-`undef PL230_HRDATA_SRC_SIZE
-// Destination AHB protection control
-`undef PL230_CHANNEL_CFG_DST_PROT_CTRL
-`undef PL230_HRDATA_DST_PROT_CTRL
-// Source AHB protection control
-`undef PL230_CHANNEL_CFG_SRC_PROT_CTRL
-`undef PL230_HRDATA_SRC_PROT_CTRL
-// Power of two transactions per request
-`undef PL230_CHANNEL_CFG_R
-`undef PL230_HRDATA_R
-// Number of bits in the N counter - hrdata[13:4]
-`undef PL230_N_COUNT_BITS
-// Lsb bit offset for n_minus_1
-`undef PL230_N_COUNT_OFFSET
-// Set chnl_useburst_status
-`undef PL230_CHANNEL_CFG_NEXT_USEBURST
-`undef PL230_HRDATA_NEXT_USEBURST
-// DMA cycle control
-`undef PL230_CHANNEL_CFG_CYCLE_CTRL
-`undef PL230_HRDATA_CYCLE_CTRL
-
-
-// Number of bits for the statemachine
-`undef PL230_STATE_BITS
-// Statemachine state encoding
-`undef PL230_ST_IDLE
-`undef PL230_ST_RD_CTRL
-`undef PL230_ST_RD_SPTR
-`undef PL230_ST_RD_DPTR
-`undef PL230_ST_RD_SDAT
-`undef PL230_ST_WR_DDAT
-`undef PL230_ST_WAIT
-`undef PL230_ST_WR_CTRL
-`undef PL230_ST_STALL
-`undef PL230_ST_DONE
-`undef PL230_ST_PSGP
-`undef PL230_ST_RESVD_0
-`undef PL230_ST_RESVD_1
-`undef PL230_ST_RESVD_2
-`undef PL230_ST_RESVD_3
-`undef PL230_ST_RESVD_4
-
-`undef PL230_SIZE_BYTE
-`undef PL230_SIZE_HWORD
-`undef PL230_SIZE_WORD
-`undef PL230_SIZE_RESVD
-
-// pl230_undefs.v end
diff --git a/system/src/accelerator_subsystem.v b/system/src/accelerator_subsystem.v
new file mode 100644
index 0000000000000000000000000000000000000000..6e68edad48b81fb3e96af758649229329eaf826c
--- /dev/null
+++ b/system/src/accelerator_subsystem.v
@@ -0,0 +1,72 @@
+//-----------------------------------------------------------------------------
+// SoC Labs Accelerator Subsystem for SecWorks AES-128 Accelerator
+// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (C) 2023; SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module accelerator_subsystem #(
+ parameter SYS_ADDR_W = 32,
+ parameter SYS_DATA_W = 32,
+ parameter ACC_ADDR_W = 16,
+ parameter IRQ_NUM = 4
+) (
+ input wire HCLK, // Clock
+ input wire HRESETn, // Reset
+
+ // AHB connection to Initiator
+ input wire HSEL,
+ input wire [SYS_ADDR_W-1:0] HADDR,
+ input wire [1:0] HTRANS,
+ input wire [2:0] HSIZE,
+ input wire [3:0] HPROT,
+ input wire HWRITE,
+ input wire HREADY,
+ input wire [SYS_DATA_W-1:0] HWDATA,
+
+ output wire HREADYOUT,
+ output wire HRESP,
+ output wire [SYS_DATA_W-1:0] HRDATA,
+
+ // Data Request Signal to DMAC
+ output wire [1:0] EXP_DRQ,
+ input wire [1:0] EXP_DLAST,
+
+ // Interrupts
+ output wire [IRQ_NUM-1:0] EXP_IRQ
+);
+
+ //--------------------------------------
+ // AES Accelerator Wrapper
+ //--------------------------------------
+ soclabs_ahb_aes128_ctrl u_exp_aes128 (
+ .ahb_hclk (HCLK),
+ .ahb_hresetn (HRESETn),
+ .ahb_hsel (HSEL),
+ .ahb_haddr16 (HADDR[ACC_ADDR_W-1:0]),
+ .ahb_htrans (HTRANS),
+ .ahb_hwrite (HWRITE),
+ .ahb_hsize (HSIZE),
+ .ahb_hprot (HPROT),
+ .ahb_hwdata (HWDATA),
+ .ahb_hready (HREADY),
+ .ahb_hrdata (HRDATA),
+ .ahb_hreadyout (HREADYOUT),
+ .ahb_hresp (HRESP),
+ .drq_ipdma128 (EXP_DRQ[0]),
+ .dlast_ipdma128 (EXP_DLAST[0]),
+ .drq_opdma128 (EXP_DRQ[1]),
+ .dlast_opdma128 (EXP_DLAST[1]),
+ .irq_key128 (EXP_IRQ[0]),
+ .irq_ip128 (EXP_IRQ[1]),
+ .irq_op128 (EXP_IRQ[2]),
+ .irq_error (EXP_IRQ[3]),
+ .irq_merged ( )
+ );
+
+endmodule
diff --git a/system/src/nanosoc_exp.v b/system/src/nanosoc_exp.v
deleted file mode 100644
index b8794b4d226d02c414918bbd9a26d0b4bd5d108b..0000000000000000000000000000000000000000
--- a/system/src/nanosoc_exp.v
+++ /dev/null
@@ -1,152 +0,0 @@
-//-----------------------------------------------------------------------------
-// Nanosoc Expansion Region AHB Address Region
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-`include "cmsdk_ahb_default_slave.v"
-`include "cmsdk_ahb_slave_mux.v"
-
-module nanosoc_exp #(
- parameter ADDRWIDTH=29, // Region Address Width
- parameter ACCEL_ADDRWIDTH=12 // Region Address Width
- )(
- input wire HCLK, // Clock
- input wire HRESETn, // Reset
-
- // AHB connection to Initiator
- input wire HSELS,
- input wire [ADDRWIDTH-1:0] HADDRS,
- input wire [1:0] HTRANSS,
- input wire [2:0] HSIZES,
- input wire [3:0] HPROTS,
- input wire HWRITES,
- input wire HREADYS,
- input wire [31:0] HWDATAS,
-
- output wire HREADYOUTS,
- output wire HRESPS,
- output wire [31:0] HRDATAS,
-
- output wire ip_data_req,
- output wire op_data_req
- );
-
-//********************************************************************************
-// Internal Wires
-//********************************************************************************
-
-// Accelerator AHB Signals
-wire HSEL0;
-wire HREADYOUT0;
-wire HRESP0;
-wire [31:0] HRDATA0;
-
-// Default Slave AHB Signals
-wire HSEL1;
-wire HREADYOUT1;
-wire HRESP1;
-wire [31:0] HRDATA1;
-
-//********************************************************************************
-// Address decoder, need to be changed for other configuration
-//********************************************************************************
-// 0x00010000 - 0x00010FFF : HSEL #0 - Hash Accelerator
-// Other addresses : HSEL #1 - Default target
-
- assign HSEL0 = (HADDRS[ADDRWIDTH-1:12] == 'h00010) ? 1'b1:1'b0;
- assign HSEL1 = HSEL0 ? 1'b0:1'b1;
-
-//********************************************************************************
-// Slave multiplexer module:
-// multiplex the target signals to master, three ports are enabled
-//********************************************************************************
-
-cmsdk_ahb_slave_mux #(
- 1, //PORT0_ENABLE
- 1, //PORT1_ENABLE
- 1, //PORT2_ENABLE
- 0, //PORT3_ENABLE
- 0, //PORT4_ENABLE
- 0, //PORT5_ENABLE
- 0, //PORT6_ENABLE
- 0, //PORT7_ENABLE
- 0, //PORT8_ENABLE
- 0 //PORT9_ENABLE
- ) u_ahb_slave_mux (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HREADY (HREADYS),
- .HSEL0 (HSEL0), // Input Port 0
- .HREADYOUT0 (HREADYOUT0),
- .HRESP0 (HRESP0),
- .HRDATA0 (HRDATA0),
- .HSEL1 (HSEL1), // Input Port 1
- .HREADYOUT1 (HREADYOUT1),
- .HRESP1 (HRESP1),
- .HRDATA1 (HRDATA1),
- .HSEL2 (1'b0), // Input Port 2
- .HREADYOUT2 (),
- .HRESP2 (),
- .HRDATA2 (),
- .HSEL3 (1'b0), // Input Port 3
- .HREADYOUT3 (),
- .HRESP3 (),
- .HRDATA3 (),
- .HSEL4 (1'b0), // Input Port 4
- .HREADYOUT4 (),
- .HRESP4 (),
- .HRDATA4 (),
- .HSEL5 (1'b0), // Input Port 5
- .HREADYOUT5 (),
- .HRESP5 (),
- .HRDATA5 (),
- .HSEL6 (1'b0), // Input Port 6
- .HREADYOUT6 (),
- .HRESP6 (),
- .HRDATA6 (),
- .HSEL7 (1'b0), // Input Port 7
- .HREADYOUT7 (),
- .HRESP7 (),
- .HRDATA7 (),
- .HSEL8 (1'b0), // Input Port 8
- .HREADYOUT8 (),
- .HRESP8 (),
- .HRDATA8 (),
- .HSEL9 (1'b0), // Input Port 9
- .HREADYOUT9 (),
- .HRESP9 (),
- .HRDATA9 (),
-
- .HREADYOUT (HREADYOUTS), // Outputs
- .HRESP (HRESPS),
- .HRDATA (HRDATAS)
- );
-
-
-//********************************************************************************
-// Slave module 1: Accelerator AHB target module
-//********************************************************************************
-
-// Instantiate your accelerator wrapper HERE
-
-//********************************************************************************
-// Slave module 2: AHB default target module
-//********************************************************************************
- cmsdk_ahb_default_slave u_ahb_default_slave(
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (HSEL1),
- .HTRANS (HTRANSS),
- .HREADY (HREADYS),
- .HREADYOUT (HREADYOUT1),
- .HRESP (HRESP1)
- );
-
- assign HRDATA1 = {32{1'b0}}; // Default target don't have data
-
-endmodule
diff --git a/system/testcodes/aes128_tests_dma230/adp.cmd b/system/testcodes/aes128_tests_dma230/adp.cmd
new file mode 100644
index 0000000000000000000000000000000000000000..8b137891791fe96927ad78e64b0aad7bded08bdc
--- /dev/null
+++ b/system/testcodes/aes128_tests_dma230/adp.cmd
@@ -0,0 +1 @@
+
diff --git a/system/testcodes/aes128_tests_dma230/aes128.h b/system/testcodes/aes128_tests_dma230/aes128.h
new file mode 100644
index 0000000000000000000000000000000000000000..202adf42b9efc670fa80c6c2b5335b9352b41cd0
--- /dev/null
+++ b/system/testcodes/aes128_tests_dma230/aes128.h
@@ -0,0 +1,71 @@
+#ifndef _AES128_H_
+#define _AES128_H_
+
+#include <stdint.h>
+
+// define the API addresses here.
+
+#define AES128_BASE (0x60000000)
+
+// byte address I/O buffers
+#define AES128_BUF_SIZE (0x4000)
+
+typedef struct {
+ __I uint32_t CORE_NAME[2]; /* 0x0000-0007 */
+ __I uint32_t CORE_VERSION; /* 0x0008-000B */
+ uint32_t RESRV0C; /* 0x000C */
+ __IO uint32_t CTRL; /* 0x0010 */
+ __O uint32_t CTRL_SET; /* 0x0014 */
+ __O uint32_t CTRLL_CLR; /* 0x0018 */
+ __I uint32_t STATUS; /* 0x001c */
+ __IO uint32_t QUAL; /* 0x0020 */
+ uint32_t RESRV24[3]; /* 0x0024 - 2F*/
+ __IO uint32_t DRQ_MSK; /* 0x0030 */
+ __O uint32_t DRQ_MSK_SET; /* 0x0034 */
+ __O uint32_t DRQ_MSK_CLR; /* 0x0038 */
+ __I uint32_t DRQ_STATUS; /* 0x003C */
+ __IO uint32_t IRQ_MSK; /* 0x0040 */
+ __O uint32_t IRQ_MSK_SET; /* 0x0044 */
+ __O uint32_t IRQ_MSK_CLR; /* 0x0048 */
+ __I uint32_t IRQ_STATUS; /* 0x004C */
+ uint8_t RESRV50[AES128_BUF_SIZE - 0x50];/* 0x0050-0x3FFC (4096-20 words) */
+ __IO uint8_t KEY128[AES128_BUF_SIZE]; /* 0x4000-7FFF (0x3FFF is last alias) */
+ __IO uint8_t TXTIP128[AES128_BUF_SIZE]; /* 0x8000-BFFF (0x3FFF is last alias) */
+ __I uint8_t TXTOP128[AES128_BUF_SIZE]; /* 0xC000-FFFF (0x3FFF is last alias) */
+} AES128_TypeDef;
+
+#define AES128 ((AES128_TypeDef *) AES128_BASE )
+
+#define AES_BLOCK_SIZE 16
+
+#define AES_KEY_LEN_128 16
+
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+
+#define AES128_CTRL_REG_WIDTH ( 8)
+#define AES128_CTRL_BIT_MAX ( (CTRL_REG_WIDTH-1)
+#define AES128_CTRL_KEY_REQ_BIT (1<<0)
+#define AES128_CTRL_IP_REQ_BIT (1<<1)
+#define AES128_CTRL_OP_REQ_BIT (1<<2)
+#define AES128_CTRL_ERR_REQ_BIT (1<<3)
+#define AES128_CTRL_BYPASS_BIT (1<<6)
+#define AES128_CTRL_ENCODE_BIT (1<<7)
+#define AES128_STAT_REG_WIDTH ( 8)
+#define AES128_STAT_KEY_REQ_BIT (1<<0)
+#define AES128_STAT_IP_REQ_BIT (1<<1)
+#define AES128_STAT_OP_REQ_BIT (1<<2)
+#define AES128_STAT_ERR_REQ_BIT (1<<3)
+#define AES128_STAT_KEYOK_BIT (1<<4)
+#define AES128_STAT_VALID_BIT (1<<5)
+#define AES128_STAT_BYPASS_BIT (1<<6)
+#define AES128_STAT_ENCODE_BIT (1<<7)
+#define AES128_KEY_REQ_BIT (1<<0)
+#define AES128_IP_REQ_BIT (1<<1)
+#define AES128_OP_REQ_BIT (1<<2)
+#define AES128_ERR_REQ_BIT (1<<3)
+#define AES128_KEYOK_BIT (1<<4)
+#define AES128_VALID_BIT (1<<5)
+#define AES128_BYPASS_BIT (1<<6)
+#define AES128_ENCODE_BIT (1<<7)
+
+#endif // _AES128_H_
diff --git a/system/testcodes/aes128_tests_dma230/aes128_tests_dma230.c b/system/testcodes/aes128_tests_dma230/aes128_tests_dma230.c
new file mode 100644
index 0000000000000000000000000000000000000000..36bc54900904cd499bb5b92a8bfd15ec7568479f
--- /dev/null
+++ b/system/testcodes/aes128_tests_dma230/aes128_tests_dma230.c
@@ -0,0 +1,688 @@
+#include "CMSDK_CM0.h"
+#include "aes128.h"
+#include <string.h>
+#include "uart_stdout.h"
+#include <stdio.h>
+// memcopy implememtation
+#define os_memcpy memcpy
+#define os_memset memset
+// PL230DMA implementation
+#include "dma_pl230_driver.h"
+
+
+static volatile dma_pl230_channel_data aes_ip_chain[2];
+static volatile dma_pl230_channel_data aes_op_chain[2];
+
+// associate DMA channel numbers
+#define DMA_CHAN_AES128_IP (0)
+#define DMA_CHAN_AES128_OP (1)
+
+volatile int dma_done_irq_occurred;
+volatile int dma_done_irq_expected;
+volatile int dma_error_irq_occurred;
+volatile int dma_error_irq_expected;
+volatile int aes_key_irq_occurred;
+volatile int aes_key_irq_expected;
+volatile int aes_ip_irq_occurred;
+volatile int aes_ip_irq_expected;
+volatile int aes_op_irq_occurred;
+volatile int aes_op_irq_expected;
+volatile int aes_err_irq_occurred;
+volatile int aes_err_irq_expected;
+
+ uint8_t _test_key128[AES_KEY_LEN_128] = {
+ 0x75, 0x46, 0x20, 0x67,
+ 0x6e, 0x75, 0x4b, 0x20,
+ 0x79, 0x6d, 0x20, 0x73,
+ 0x74, 0x61, 0x68, 0x54 };
+
+ uint8_t test_key128[AES_KEY_LEN_128] = {
+ 0x54, 0x68, 0x61, 0x74,
+ 0x73, 0x20, 0x6d, 0x79,
+ 0x20, 0x4b, 0x75, 0x6e,
+ 0x67, 0x20, 0x46, 0x75 };
+
+ uint8_t buf128[AES_BLOCK_SIZE] = {
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00 };
+
+ uint8_t _test_text128[AES_BLOCK_SIZE] = {
+ 0x6f, 0x77, 0x54, 0x20,
+ 0x65, 0x6e, 0x69, 0x4e,
+ 0x20, 0x65, 0x6e, 0x4f,
+ 0x20, 0x6f, 0x77, 0x54 };
+
+ uint8_t test_text128[AES_BLOCK_SIZE] = {
+ 0x54, 0x77, 0x6f, 0x20,
+ 0x4f, 0x6e, 0x65, 0x20,
+ 0x4e, 0x69, 0x6e, 0x65,
+ 0x20, 0x54, 0x77, 0x6f };
+
+ uint8_t test_exp128[AES_BLOCK_SIZE] = {
+ 0x29, 0xc3, 0x50, 0x5f,
+ 0x57, 0x14, 0x20, 0xf6,
+ 0x40, 0x22, 0x99, 0xb3,
+ 0x1a, 0x02, 0xd7, 0x3a };
+
+// add extra block[128] with all zeros to toggle bits low
+ uint8_t shift_patt[129*16] = {
+ 0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,//127
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//128
+ };
+
+ uint8_t shift_buf1[sizeof(shift_patt)];
+ uint8_t shift_buf2[sizeof(shift_patt)];
+
+
+/* Note: Hardware supports byte, half-word or word accesses
+ So memcpy() can be used to load/save data
+ And memset() can be used to pad out data-in to 128-bits
+ mode =0 (bypass), =1 (encode) or =2 (decode)
+*/
+void aes128_driver_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input,
+ uint8_t *result, uint8_t mode)
+{
+ // Reset engine
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ AES128->QUAL = 0;
+ AES128->CTRL = AES128_CTRL_KEY_REQ_BIT | AES128_CTRL_IP_REQ_BIT | AES128_CTRL_OP_REQ_BIT | AES128_CTRL_ERR_REQ_BIT;
+
+ // Set up parameters
+ if (mode == 1)
+ AES128->CTRL_SET = AES128_ENCODE_BIT; // ENCODE mode
+ if (mode == 0)
+ AES128->CTRL_SET = AES128_BYPASS_BIT; // BYPASS mode
+
+ AES128->IRQ_MSK_SET = (AES128_ERR_REQ_BIT | AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+
+ // Program Key
+ os_memcpy((uint8_t *)AES128->KEY128, key, AES_KEY_LEN_128);
+ while (!(AES128->STATUS & AES128_KEYOK_BIT))
+ ;
+
+ /* payload */
+ while(nbytes) {
+ uint8_t len = (nbytes > AES_BLOCK_SIZE) ? AES_BLOCK_SIZE : nbytes;
+ /* Align/pad input and load into hardware */
+ os_memcpy((uint8_t *)AES128->TXTIP128, input, len);
+ //patch up any zero-padding
+ if (len < AES_BLOCK_SIZE)
+ os_memset((uint8_t *)&(AES128->TXTIP128[len]), 0, AES_BLOCK_SIZE-len);
+ /* Auto-started! - no need for manual start */
+ /* Poll until completed */
+ while (!(AES128->STATUS & AES128_VALID_BIT))
+ ;
+ os_memcpy(result, (uint8_t *)AES128->TXTOP128, AES_BLOCK_SIZE);
+ /* Accounting */
+ input += len;
+ result += len;
+ nbytes -= len;
+ AES128->IRQ_MSK_SET = (AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ }
+ AES128->CTRL = 0;
+}
+
+// wrapper functions
+
+void aes128_bypass_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_driver_memcpy(key, nbytes, input, result, 0); }
+
+void aes128_encrypt_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_driver_memcpy(key, nbytes, input, result, 1); }
+
+void aes128_decrypt_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_driver_memcpy(key, nbytes, input, result, 2); }
+
+
+int aes128_buffer_verify(uint32_t buflen, uint8_t *buf_A, uint8_t *buf_B)
+{
+ int i, j, fail = 0;
+ for (i=0 ; i < buflen; i++) {
+ if (buf_A[i] != buf_B[i]){
+ fail = 1;
+ break;
+ }
+ }
+ if (fail) {
+ j=i; // print offending block
+ for (i=(j - (j%16)) ; i < (j-(j%16)+16); i++) {
+ if (i%16==0)
+ printf(" //%03d\n", (i>>4));
+ printf("0x%02x,", buf_A[i]);
+ }
+ }
+ if (fail){
+ i=j;
+ printf("Verify compare FAIL\n EXPECTED_RESULT[%2d]= 0x%02x, ACTUAL_RESULT= 0x%02x \n",i, buf_B[i], buf_A[i]);
+ return(-1);
+ }
+ return(0);
+}
+
+void aes128_driver_aligned_dma32(uint8_t *key, uint32_t nbytes, uint8_t *input,
+ uint8_t *result, uint8_t mode)
+{
+ int c;
+ // Reset engine
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ AES128->QUAL = 0;
+ AES128->CTRL = AES128_CTRL_KEY_REQ_BIT | AES128_CTRL_IP_REQ_BIT | AES128_CTRL_OP_REQ_BIT;
+
+ // Set up parameters
+ if (mode == 1)
+ AES128->CTRL_SET = AES128_ENCODE_BIT; // ENCODE mode
+ if (mode == 0)
+ AES128->CTRL_SET = AES128_BYPASS_BIT; // BYPASS mode
+
+ dma_pl230_data_struct_init(); // initialize
+
+ // program DMA transfers in multiples of 4 words (nbytes scaled >>2 for words)
+ aes_ip_chain[0].SrcEndPointer = DMA_PL230_PTR_END(key,PL230_XFER_W,4);
+ aes_ip_chain[0].DstEndPointer = DMA_PL230_PTR_END(&(AES128->KEY128[AES128_BUF_SIZE-16]),PL230_XFER_W,4);
+ aes_ip_chain[0].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_DEV_CHAIN_ALT,PL230_XFER_W,4,PL230_CTRL_RPWR_4);
+
+ aes_ip_chain[1].SrcEndPointer = DMA_PL230_PTR_END(input,PL230_XFER_W,(nbytes>>2));
+ aes_ip_chain[1].DstEndPointer = DMA_PL230_PTR_END(&(AES128->TXTIP128[AES128_BUF_SIZE-nbytes]),PL230_XFER_W,(nbytes>>2));
+ aes_ip_chain[1].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_BASIC,PL230_XFER_W,(nbytes>>2),PL230_CTRL_RPWR_4);
+
+ c=DMA_CHAN_AES128_IP;
+ dma_pl230_table->Primary[c].SrcEndPointer = DMA_PL230_PTR_END(&(aes_ip_chain[0].SrcEndPointer), PL230_XFER_W,(2*4));
+ dma_pl230_table->Primary[c].DstEndPointer = DMA_PL230_PTR_END(&(dma_pl230_table->Alternate[c]), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].Control= DMA_PL230_CTRL_DSTFIX(PL230_CTRL_CYCLE_DEV_CHAIN_PRI,PL230_XFER_W,(2*4),PL230_CTRL_RPWR_4);
+
+ aes_op_chain[0].SrcEndPointer = DMA_PL230_PTR_END(&(AES128->TXTOP128[AES128_BUF_SIZE-nbytes]),PL230_XFER_W,(nbytes>>2));
+ aes_op_chain[0].DstEndPointer = DMA_PL230_PTR_END(result,PL230_XFER_W,(nbytes>>2));
+ aes_op_chain[0].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_BASIC,PL230_XFER_W,(nbytes>>2),PL230_CTRL_RPWR_4);
+
+ c=DMA_CHAN_AES128_OP;
+ dma_pl230_table->Primary[c].SrcEndPointer = DMA_PL230_PTR_END(&(aes_op_chain[0].SrcEndPointer), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].DstEndPointer = DMA_PL230_PTR_END(&(dma_pl230_table->Alternate[c]), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].Control= DMA_PL230_CTRL_DSTFIX(PL230_CTRL_CYCLE_DEV_CHAIN_PRI,PL230_XFER_W,(1*4),PL230_CTRL_RPWR_4);
+
+ // enable DMA controller channels
+ dma_pl230_init((1<<DMA_CHAN_AES128_OP) | (1<<DMA_CHAN_AES128_IP)); // two active
+
+ // and enable DMA requests
+ AES128->DRQ_MSK_SET = (AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ AES128->IRQ_MSK_SET = (AES128_ERR_REQ_BIT | AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ // test to ensure output DMA has started
+ while (!(dma_pl230_channel_active((1<<DMA_CHAN_AES128_OP))))
+ ;
+ while (dma_pl230_channel_active((1<<DMA_CHAN_AES128_OP)))
+ ;
+ while (dma_pl230_channel_active((1<<DMA_CHAN_AES128_OP)))
+ ;
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ DMA_PL230_DMAC->DMA_CFG = 0; /* Disable DMA controller for initialization */
+ dma_pl230_init(0); // none active
+ return;
+}
+
+void aes128_driver_dma8(uint8_t *key, uint32_t nbytes, uint8_t *input,
+ uint8_t *result, uint8_t mode)
+{
+ int c;
+ // Reset engine
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ AES128->QUAL = 0;
+ AES128->CTRL = AES128_CTRL_KEY_REQ_BIT | AES128_CTRL_IP_REQ_BIT | AES128_CTRL_OP_REQ_BIT;
+
+ // Set up parameters
+ if (mode == 1)
+ AES128->CTRL_SET = AES128_ENCODE_BIT; // ENCODE mode
+ if (mode == 0)
+ AES128->CTRL_SET = AES128_BYPASS_BIT; // BYPASS mode
+
+ dma_pl230_data_struct_init(); // initialize
+
+ // program DMA transfers in multiples of 16 bytes
+ aes_ip_chain[0].SrcEndPointer = DMA_PL230_PTR_END(key,PL230_XFER_B,16);
+ aes_ip_chain[0].DstEndPointer = DMA_PL230_PTR_END(&(AES128->KEY128[AES128_BUF_SIZE-16]),PL230_XFER_B,16);
+ aes_ip_chain[0].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_DEV_CHAIN_ALT,PL230_XFER_B,16,PL230_CTRL_RPWR_16);
+
+ aes_ip_chain[1].SrcEndPointer = DMA_PL230_PTR_END(input,PL230_XFER_B,(nbytes));
+ aes_ip_chain[1].DstEndPointer = DMA_PL230_PTR_END(&(AES128->TXTIP128[AES128_BUF_SIZE-nbytes]),PL230_XFER_B,(nbytes));
+ aes_ip_chain[1].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_BASIC,PL230_XFER_B,(nbytes),PL230_CTRL_RPWR_16);
+
+ c=DMA_CHAN_AES128_IP;
+ dma_pl230_table->Primary[c].SrcEndPointer = DMA_PL230_PTR_END(&(aes_ip_chain[0].SrcEndPointer), PL230_XFER_W, (2*4));
+ dma_pl230_table->Primary[c].DstEndPointer = DMA_PL230_PTR_END(&(dma_pl230_table->Alternate[c]), PL230_XFER_W, (1*4));
+ dma_pl230_table->Primary[c].Control= DMA_PL230_CTRL_DSTFIX(PL230_CTRL_CYCLE_DEV_CHAIN_PRI,PL230_XFER_W,(2*4),PL230_CTRL_RPWR_4);
+
+ aes_op_chain[0].SrcEndPointer = DMA_PL230_PTR_END(&(AES128->TXTOP128[AES128_BUF_SIZE-nbytes]),PL230_XFER_B,(nbytes));
+ aes_op_chain[0].DstEndPointer = DMA_PL230_PTR_END(result,PL230_XFER_B,(nbytes));
+ aes_op_chain[0].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_BASIC,PL230_XFER_B,(nbytes),PL230_CTRL_RPWR_16);
+
+ c=DMA_CHAN_AES128_OP;
+ dma_pl230_table->Primary[c].SrcEndPointer = DMA_PL230_PTR_END(&(aes_op_chain[0].SrcEndPointer), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].DstEndPointer = DMA_PL230_PTR_END(&(dma_pl230_table->Alternate[c]), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].Control= DMA_PL230_CTRL_DSTFIX(PL230_CTRL_CYCLE_DEV_CHAIN_PRI,PL230_XFER_W,(1*4),PL230_CTRL_RPWR_4);
+
+ // enable DMA controller channels
+ dma_pl230_init((1<<DMA_CHAN_AES128_OP) | (1<<DMA_CHAN_AES128_IP)); // two active
+
+ // and enable DMA requests
+ AES128->DRQ_MSK_SET = (AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ AES128->IRQ_MSK_SET = (AES128_ERR_REQ_BIT | AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ // test to ensure output DMA has started
+ while (!(dma_pl230_channel_active(1<<DMA_CHAN_AES128_OP)))
+ ;
+ while (dma_pl230_channel_active(1<<DMA_CHAN_AES128_OP))
+ ;
+ while (dma_pl230_channel_active(1<<DMA_CHAN_AES128_OP))
+ ;
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ DMA_PL230_DMAC->DMA_CFG = 0; /* Disable DMA controller for initialization */
+ dma_pl230_init(0); // none active
+ return;
+}
+
+// wrapper functions
+
+void aes128_alignchk_block_dma(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result, uint8_t mode)
+ { uint32_t dma_max = DMA_PL230_MAX_XFERS; // default to 1 K bytes
+ if (((((long)key) & 3)==0) && ((((long)input) & 3)==0) && ((((long)result) & 3)==0)) dma_max=(DMA_PL230_MAX_XFERS<<2);
+ while (nbytes >dma_max) {
+ if (dma_max == DMA_PL230_MAX_XFERS) // 1K bytes DMA
+ aes128_driver_dma8(key, dma_max, input, result, mode);
+ else // 1K words DMA
+ aes128_driver_aligned_dma32(key, dma_max, input, result, mode);
+ nbytes -= dma_max; input += dma_max; result += dma_max;
+ }
+ if (dma_max == DMA_PL230_MAX_XFERS) // up to 1K bytes remaining
+ aes128_driver_dma8(key, nbytes, input, result, mode);
+ else // up to 1K words remaining
+ aes128_driver_aligned_dma32(key, nbytes, input, result, mode);
+ }
+
+void aes128_bypass_dma(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_alignchk_block_dma (key, nbytes, input, result, 0); }
+
+void aes128_encrypt_dma(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_alignchk_block_dma (key, nbytes, input, result, 1); }
+
+void aes128_decrypt_dma(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_alignchk_block_dma (key, nbytes, input, result, 2); }
+
+
+int main(void) {
+ char rx_char [256] = "SoCLabs AES128v1"; // init to 0
+ unsigned char id_string [16] = {0};
+ int i, fail=0;
+ unsigned char * p;
+
+ UartStdOutInit();
+ printf("%s\n",rx_char);
+ printf("AES128 test program\n");
+ printf(" AES128 ID: ");
+ // iterate over 3 32-bit fields
+ p = (unsigned char *)AES128->CORE_NAME;
+ for (i = 0; i < 12; i++) {
+ id_string[i^3]=*p; // fix byte ordering per word
+ p+=1;
+ }
+ id_string[12] = 0;
+ printf("%s\n",id_string);
+
+ aes_key_irq_occurred = 0;
+ aes_key_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP0_IRQn);
+ NVIC_EnableIRQ(EXP0_IRQn);
+ aes_ip_irq_occurred = 0;
+ aes_ip_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP1_IRQn);
+ NVIC_EnableIRQ(EXP1_IRQn);
+ aes_op_irq_occurred = 0;
+ aes_op_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP2_IRQn);
+ NVIC_EnableIRQ(EXP2_IRQn);
+ aes_err_irq_occurred = 0;
+ aes_err_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP3_IRQn);
+ NVIC_EnableIRQ(EXP3_IRQn);
+
+ printf("AES128 SW (memcpy) tests...\n");
+ printf(" AES128 reference pattern test\n");
+
+ printf(" AES128 input/output bypass test\n");
+ aes128_bypass_memcpy(test_key128, sizeof(test_text128), test_text128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+
+ if (aes_key_irq_occurred != 1){ fail++;
+ printf(" ++ AES key request IRQ count = %d\n", aes_key_irq_occurred); }
+ if (aes_ip_irq_occurred != 2){ fail++;
+ printf(" ++ AES inp request missing: IRQ count = %d\n", aes_ip_irq_occurred); }
+ if (aes_op_irq_occurred != 1){ fail++;
+ printf(" ++ AES out request missing: IRQ count = %d\n", aes_op_irq_occurred); }
+ if (aes_err_irq_occurred != 0){ fail++;
+ printf(" ++ AES err request missing: IRQ count = %d\n", aes_err_irq_occurred); }
+
+ printf(" AES128 encrypt test\n");
+ aes128_encrypt_memcpy(test_key128, sizeof(test_text128), test_text128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_exp128);
+
+ printf(" AES128 decrypt test\n");
+ aes128_decrypt_memcpy(test_key128, sizeof(buf128), buf128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+
+ aes_key_irq_occurred = 0;
+ aes_ip_irq_occurred = 0;
+ aes_op_irq_occurred = 0;
+ aes_err_irq_occurred = 0;
+
+ printf(" AES128 logic toggle test\n");
+ printf(" AES128 input/output pattern test\n");
+ aes128_bypass_memcpy(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
+ fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf1, shift_patt);
+
+ if (aes_key_irq_occurred != 1){ fail++;
+ printf(" ++ AES key request IRQ count = %d\n", aes_key_irq_occurred); }
+ if (aes_ip_irq_occurred != (129+1)){ fail++;
+ printf(" ++ AES inp request missing: IRQ count = %d\n", aes_ip_irq_occurred); }
+ if (aes_op_irq_occurred != 129){ fail++;
+ printf(" ++ AES out request missing: IRQ count = %d\n", aes_op_irq_occurred); }
+ if (aes_err_irq_occurred != 0){ fail++;
+ printf(" ++ AES err request missing: IRQ count = %d\n", aes_err_irq_occurred); }
+
+ printf(" AES128 pattern encrypt test\n");
+ aes128_encrypt_memcpy(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
+ printf(" AES128 pattern decrypt test\n");
+ aes128_decrypt_memcpy(test_key128, sizeof(shift_patt), shift_buf1, shift_buf2);
+ fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf2, shift_patt);
+
+ printf("AES128 DMA tests...\n");
+
+ aes_key_irq_occurred = 0;
+ aes_ip_irq_occurred = 0;
+ aes_op_irq_occurred = 0;
+ aes_err_irq_occurred = 0;
+ dma_error_irq_expected = 0;
+ dma_error_irq_occurred = 0;
+ dma_done_irq_expected = 1;
+ dma_done_irq_occurred = 0;
+ NVIC_ClearPendingIRQ(DMA_IRQn);
+ NVIC_EnableIRQ(DMA_IRQn);
+
+ printf(" AES128 dma input/output bypass test\n");
+ aes128_bypass_dma(test_key128, sizeof(test_text128), test_text128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+
+ if (dma_done_irq_occurred < 2){
+ puts ("ERROR: DMA err IRQ missing");
+ fail++;
+ } else
+ printf(" ++ DMA_DONE IRQ count = %d\n", dma_done_irq_occurred);
+
+ printf(" AES128 dma encrypt test\n");
+ aes128_encrypt_dma(test_key128, sizeof(test_text128), test_text128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_exp128);
+
+ printf(" AES128 dma decrypt test\n");
+ aes128_decrypt_dma(test_key128, sizeof(buf128), buf128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+
+ if (dma_done_irq_occurred < 6){
+ puts ("ERROR: DMA err IRQ missing");
+ fail++;
+ } else
+ printf(" ++ DMA_DONE IRQ count = %d\n", dma_done_irq_occurred);
+
+ printf(" AES128 dma unaligned pattern test\n");
+ aes128_bypass_dma(test_key128,(16*63), shift_patt, shift_buf1+3);
+ fail += aes128_buffer_verify((16*63), shift_buf1+3, shift_patt);
+
+ printf(" AES128 dma input/output pattern test\n");
+ aes128_bypass_dma(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
+ fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf1, shift_patt);
+ printf(" AES128 dma pattern encrypt test\n");
+ aes128_encrypt_dma(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
+ printf(" AES128 dma pattern decrypt test\n");
+ aes128_decrypt_dma(test_key128, sizeof(shift_patt), shift_buf1, shift_buf2);
+ fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf2, shift_patt);
+
+ if (dma_done_irq_occurred < (2*7)){
+ puts ("ERROR: DMA err IRQ missing");
+ fail++;
+ } else
+ printf(" ++ DMA_DONE IRQ count = %d\n", dma_done_irq_occurred);
+
+ // check IRQ masked by DRQs - except when Iinput buffer empty after DMA done
+ if (aes_key_irq_occurred != 0){ fail++;
+ printf(" ++ AES key request IRQ count = %d\n", aes_key_irq_occurred); }
+ if (aes_ip_irq_occurred != 7){ fail++;
+ printf(" ++ AES inp request missing: IRQ count = %d\n", aes_ip_irq_occurred); }
+ if (aes_op_irq_occurred != 0){ fail++;
+ printf(" ++ AES out request missing: IRQ count = %d\n", aes_op_irq_occurred); }
+ if (aes_err_irq_occurred != 0){ fail++;
+ printf(" ++ AES err request missing: IRQ count = %d\n", aes_err_irq_occurred); }
+
+ NVIC_DisableIRQ(DMA_IRQn);
+ NVIC_DisableIRQ(EXP0_IRQn);
+ NVIC_DisableIRQ(EXP1_IRQn);
+ NVIC_DisableIRQ(EXP2_IRQn);
+ NVIC_DisableIRQ(EXP3_IRQn);
+
+ printf ("Data retrieved from the AES is: %s\n", id_string);
+ printf ("Data expected from the AES is: %s\n", rx_char);
+ if (fail >0)
+ printf("** AES TESTS FAILED (%d) **\n", fail);
+ else
+ printf("** AES TEST PASSED **\n");
+ // End simulation
+
+
+ UartEndSimulation();
+
+ return 0;
+
+}
+
+/* --------------------------------------------------------------- */
+/* Interrupt handlers */
+/* --------------------------------------------------------------- */
+
+void DMA_Handler(void)
+{
+if ((DMA_PL230_DMAC->ERR_CLR & 1) != 0) {
+ /* DMA interrupt is caused by DMA error */
+ dma_error_irq_occurred ++;
+ DMA_PL230_DMAC->ERR_CLR = 1; /* Clear dma_err */
+ if (dma_error_irq_expected==0) {
+ puts ("ERROR : Unexpected DMA error interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ }
+else {
+ // DMA interrupt is caused by DMA done
+ dma_done_irq_occurred ++;
+ if (dma_done_irq_expected==0) {
+ puts ("ERROR : Unexpected DMA done interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ }
+}
+
+void EXP0_Handler(void)
+{
+ // AES128 interrupt is caused by Key buffer empty IRQ
+ aes_key_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_KEY_REQ_BIT;
+ if (aes_key_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Key buffer empty request interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP1_Handler(void)
+{
+ // AES128 interrupt is caused by Input buffer empty IRQ
+ aes_ip_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_IP_REQ_BIT;
+ if (aes_ip_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Input buffer empty reqest interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP2_Handler(void)
+{
+ // AES128 interrupt is caused by Output buffer full IRQ
+ aes_op_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_OP_REQ_BIT;
+ if (aes_op_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Output buffer full reqest interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP3_Handler(void)
+{
+ // AES128 interrupt is caused by Error IRQ
+ aes_err_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_ERR_REQ_BIT;
+ if (aes_err_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Error interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
diff --git a/system/testcodes/aes128_tests_dma230/makefile b/system/testcodes/aes128_tests_dma230/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..3f41cf935611a5a40a401b3830b1a433c216f8b1
--- /dev/null
+++ b/system/testcodes/aes128_tests_dma230/makefile
@@ -0,0 +1,253 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0
+
+# Shared software directory
+SOFTWARE_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = aes128_tests_dma230
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -Ospace -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget -I $(SOFTWARE_DIR)/drivers $(USER_DEFINE)
+ARM_ASM_OPTIONS =
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --no_debug --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+dma_pl230_driver.o : $(SOFTWARE_DIR)/drivers/dma_pl230_driver.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o dma_pl230_driver.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o dma_pl230_driver.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF
+ fromelf -c -d -e -s -z -v $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -I $(SOFTWARE_DIR)/drivers \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/system/testcodes/aes128_tests_memcpy/adp.cmd b/system/testcodes/aes128_tests_memcpy/adp.cmd
new file mode 100644
index 0000000000000000000000000000000000000000..8b137891791fe96927ad78e64b0aad7bded08bdc
--- /dev/null
+++ b/system/testcodes/aes128_tests_memcpy/adp.cmd
@@ -0,0 +1 @@
+
diff --git a/system/testcodes/aes128_tests_memcpy/aes128.h b/system/testcodes/aes128_tests_memcpy/aes128.h
new file mode 100644
index 0000000000000000000000000000000000000000..202adf42b9efc670fa80c6c2b5335b9352b41cd0
--- /dev/null
+++ b/system/testcodes/aes128_tests_memcpy/aes128.h
@@ -0,0 +1,71 @@
+#ifndef _AES128_H_
+#define _AES128_H_
+
+#include <stdint.h>
+
+// define the API addresses here.
+
+#define AES128_BASE (0x60000000)
+
+// byte address I/O buffers
+#define AES128_BUF_SIZE (0x4000)
+
+typedef struct {
+ __I uint32_t CORE_NAME[2]; /* 0x0000-0007 */
+ __I uint32_t CORE_VERSION; /* 0x0008-000B */
+ uint32_t RESRV0C; /* 0x000C */
+ __IO uint32_t CTRL; /* 0x0010 */
+ __O uint32_t CTRL_SET; /* 0x0014 */
+ __O uint32_t CTRLL_CLR; /* 0x0018 */
+ __I uint32_t STATUS; /* 0x001c */
+ __IO uint32_t QUAL; /* 0x0020 */
+ uint32_t RESRV24[3]; /* 0x0024 - 2F*/
+ __IO uint32_t DRQ_MSK; /* 0x0030 */
+ __O uint32_t DRQ_MSK_SET; /* 0x0034 */
+ __O uint32_t DRQ_MSK_CLR; /* 0x0038 */
+ __I uint32_t DRQ_STATUS; /* 0x003C */
+ __IO uint32_t IRQ_MSK; /* 0x0040 */
+ __O uint32_t IRQ_MSK_SET; /* 0x0044 */
+ __O uint32_t IRQ_MSK_CLR; /* 0x0048 */
+ __I uint32_t IRQ_STATUS; /* 0x004C */
+ uint8_t RESRV50[AES128_BUF_SIZE - 0x50];/* 0x0050-0x3FFC (4096-20 words) */
+ __IO uint8_t KEY128[AES128_BUF_SIZE]; /* 0x4000-7FFF (0x3FFF is last alias) */
+ __IO uint8_t TXTIP128[AES128_BUF_SIZE]; /* 0x8000-BFFF (0x3FFF is last alias) */
+ __I uint8_t TXTOP128[AES128_BUF_SIZE]; /* 0xC000-FFFF (0x3FFF is last alias) */
+} AES128_TypeDef;
+
+#define AES128 ((AES128_TypeDef *) AES128_BASE )
+
+#define AES_BLOCK_SIZE 16
+
+#define AES_KEY_LEN_128 16
+
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+
+#define AES128_CTRL_REG_WIDTH ( 8)
+#define AES128_CTRL_BIT_MAX ( (CTRL_REG_WIDTH-1)
+#define AES128_CTRL_KEY_REQ_BIT (1<<0)
+#define AES128_CTRL_IP_REQ_BIT (1<<1)
+#define AES128_CTRL_OP_REQ_BIT (1<<2)
+#define AES128_CTRL_ERR_REQ_BIT (1<<3)
+#define AES128_CTRL_BYPASS_BIT (1<<6)
+#define AES128_CTRL_ENCODE_BIT (1<<7)
+#define AES128_STAT_REG_WIDTH ( 8)
+#define AES128_STAT_KEY_REQ_BIT (1<<0)
+#define AES128_STAT_IP_REQ_BIT (1<<1)
+#define AES128_STAT_OP_REQ_BIT (1<<2)
+#define AES128_STAT_ERR_REQ_BIT (1<<3)
+#define AES128_STAT_KEYOK_BIT (1<<4)
+#define AES128_STAT_VALID_BIT (1<<5)
+#define AES128_STAT_BYPASS_BIT (1<<6)
+#define AES128_STAT_ENCODE_BIT (1<<7)
+#define AES128_KEY_REQ_BIT (1<<0)
+#define AES128_IP_REQ_BIT (1<<1)
+#define AES128_OP_REQ_BIT (1<<2)
+#define AES128_ERR_REQ_BIT (1<<3)
+#define AES128_KEYOK_BIT (1<<4)
+#define AES128_VALID_BIT (1<<5)
+#define AES128_BYPASS_BIT (1<<6)
+#define AES128_ENCODE_BIT (1<<7)
+
+#endif // _AES128_H_
diff --git a/system/testcodes/aes128_tests_memcpy/aes128_tests.c b/system/testcodes/aes128_tests_memcpy/aes128_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..36bc54900904cd499bb5b92a8bfd15ec7568479f
--- /dev/null
+++ b/system/testcodes/aes128_tests_memcpy/aes128_tests.c
@@ -0,0 +1,688 @@
+#include "CMSDK_CM0.h"
+#include "aes128.h"
+#include <string.h>
+#include "uart_stdout.h"
+#include <stdio.h>
+// memcopy implememtation
+#define os_memcpy memcpy
+#define os_memset memset
+// PL230DMA implementation
+#include "dma_pl230_driver.h"
+
+
+static volatile dma_pl230_channel_data aes_ip_chain[2];
+static volatile dma_pl230_channel_data aes_op_chain[2];
+
+// associate DMA channel numbers
+#define DMA_CHAN_AES128_IP (0)
+#define DMA_CHAN_AES128_OP (1)
+
+volatile int dma_done_irq_occurred;
+volatile int dma_done_irq_expected;
+volatile int dma_error_irq_occurred;
+volatile int dma_error_irq_expected;
+volatile int aes_key_irq_occurred;
+volatile int aes_key_irq_expected;
+volatile int aes_ip_irq_occurred;
+volatile int aes_ip_irq_expected;
+volatile int aes_op_irq_occurred;
+volatile int aes_op_irq_expected;
+volatile int aes_err_irq_occurred;
+volatile int aes_err_irq_expected;
+
+ uint8_t _test_key128[AES_KEY_LEN_128] = {
+ 0x75, 0x46, 0x20, 0x67,
+ 0x6e, 0x75, 0x4b, 0x20,
+ 0x79, 0x6d, 0x20, 0x73,
+ 0x74, 0x61, 0x68, 0x54 };
+
+ uint8_t test_key128[AES_KEY_LEN_128] = {
+ 0x54, 0x68, 0x61, 0x74,
+ 0x73, 0x20, 0x6d, 0x79,
+ 0x20, 0x4b, 0x75, 0x6e,
+ 0x67, 0x20, 0x46, 0x75 };
+
+ uint8_t buf128[AES_BLOCK_SIZE] = {
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00 };
+
+ uint8_t _test_text128[AES_BLOCK_SIZE] = {
+ 0x6f, 0x77, 0x54, 0x20,
+ 0x65, 0x6e, 0x69, 0x4e,
+ 0x20, 0x65, 0x6e, 0x4f,
+ 0x20, 0x6f, 0x77, 0x54 };
+
+ uint8_t test_text128[AES_BLOCK_SIZE] = {
+ 0x54, 0x77, 0x6f, 0x20,
+ 0x4f, 0x6e, 0x65, 0x20,
+ 0x4e, 0x69, 0x6e, 0x65,
+ 0x20, 0x54, 0x77, 0x6f };
+
+ uint8_t test_exp128[AES_BLOCK_SIZE] = {
+ 0x29, 0xc3, 0x50, 0x5f,
+ 0x57, 0x14, 0x20, 0xf6,
+ 0x40, 0x22, 0x99, 0xb3,
+ 0x1a, 0x02, 0xd7, 0x3a };
+
+// add extra block[128] with all zeros to toggle bits low
+ uint8_t shift_patt[129*16] = {
+ 0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,//127
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//128
+ };
+
+ uint8_t shift_buf1[sizeof(shift_patt)];
+ uint8_t shift_buf2[sizeof(shift_patt)];
+
+
+/* Note: Hardware supports byte, half-word or word accesses
+ So memcpy() can be used to load/save data
+ And memset() can be used to pad out data-in to 128-bits
+ mode =0 (bypass), =1 (encode) or =2 (decode)
+*/
+void aes128_driver_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input,
+ uint8_t *result, uint8_t mode)
+{
+ // Reset engine
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ AES128->QUAL = 0;
+ AES128->CTRL = AES128_CTRL_KEY_REQ_BIT | AES128_CTRL_IP_REQ_BIT | AES128_CTRL_OP_REQ_BIT | AES128_CTRL_ERR_REQ_BIT;
+
+ // Set up parameters
+ if (mode == 1)
+ AES128->CTRL_SET = AES128_ENCODE_BIT; // ENCODE mode
+ if (mode == 0)
+ AES128->CTRL_SET = AES128_BYPASS_BIT; // BYPASS mode
+
+ AES128->IRQ_MSK_SET = (AES128_ERR_REQ_BIT | AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+
+ // Program Key
+ os_memcpy((uint8_t *)AES128->KEY128, key, AES_KEY_LEN_128);
+ while (!(AES128->STATUS & AES128_KEYOK_BIT))
+ ;
+
+ /* payload */
+ while(nbytes) {
+ uint8_t len = (nbytes > AES_BLOCK_SIZE) ? AES_BLOCK_SIZE : nbytes;
+ /* Align/pad input and load into hardware */
+ os_memcpy((uint8_t *)AES128->TXTIP128, input, len);
+ //patch up any zero-padding
+ if (len < AES_BLOCK_SIZE)
+ os_memset((uint8_t *)&(AES128->TXTIP128[len]), 0, AES_BLOCK_SIZE-len);
+ /* Auto-started! - no need for manual start */
+ /* Poll until completed */
+ while (!(AES128->STATUS & AES128_VALID_BIT))
+ ;
+ os_memcpy(result, (uint8_t *)AES128->TXTOP128, AES_BLOCK_SIZE);
+ /* Accounting */
+ input += len;
+ result += len;
+ nbytes -= len;
+ AES128->IRQ_MSK_SET = (AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ }
+ AES128->CTRL = 0;
+}
+
+// wrapper functions
+
+void aes128_bypass_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_driver_memcpy(key, nbytes, input, result, 0); }
+
+void aes128_encrypt_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_driver_memcpy(key, nbytes, input, result, 1); }
+
+void aes128_decrypt_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_driver_memcpy(key, nbytes, input, result, 2); }
+
+
+int aes128_buffer_verify(uint32_t buflen, uint8_t *buf_A, uint8_t *buf_B)
+{
+ int i, j, fail = 0;
+ for (i=0 ; i < buflen; i++) {
+ if (buf_A[i] != buf_B[i]){
+ fail = 1;
+ break;
+ }
+ }
+ if (fail) {
+ j=i; // print offending block
+ for (i=(j - (j%16)) ; i < (j-(j%16)+16); i++) {
+ if (i%16==0)
+ printf(" //%03d\n", (i>>4));
+ printf("0x%02x,", buf_A[i]);
+ }
+ }
+ if (fail){
+ i=j;
+ printf("Verify compare FAIL\n EXPECTED_RESULT[%2d]= 0x%02x, ACTUAL_RESULT= 0x%02x \n",i, buf_B[i], buf_A[i]);
+ return(-1);
+ }
+ return(0);
+}
+
+void aes128_driver_aligned_dma32(uint8_t *key, uint32_t nbytes, uint8_t *input,
+ uint8_t *result, uint8_t mode)
+{
+ int c;
+ // Reset engine
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ AES128->QUAL = 0;
+ AES128->CTRL = AES128_CTRL_KEY_REQ_BIT | AES128_CTRL_IP_REQ_BIT | AES128_CTRL_OP_REQ_BIT;
+
+ // Set up parameters
+ if (mode == 1)
+ AES128->CTRL_SET = AES128_ENCODE_BIT; // ENCODE mode
+ if (mode == 0)
+ AES128->CTRL_SET = AES128_BYPASS_BIT; // BYPASS mode
+
+ dma_pl230_data_struct_init(); // initialize
+
+ // program DMA transfers in multiples of 4 words (nbytes scaled >>2 for words)
+ aes_ip_chain[0].SrcEndPointer = DMA_PL230_PTR_END(key,PL230_XFER_W,4);
+ aes_ip_chain[0].DstEndPointer = DMA_PL230_PTR_END(&(AES128->KEY128[AES128_BUF_SIZE-16]),PL230_XFER_W,4);
+ aes_ip_chain[0].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_DEV_CHAIN_ALT,PL230_XFER_W,4,PL230_CTRL_RPWR_4);
+
+ aes_ip_chain[1].SrcEndPointer = DMA_PL230_PTR_END(input,PL230_XFER_W,(nbytes>>2));
+ aes_ip_chain[1].DstEndPointer = DMA_PL230_PTR_END(&(AES128->TXTIP128[AES128_BUF_SIZE-nbytes]),PL230_XFER_W,(nbytes>>2));
+ aes_ip_chain[1].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_BASIC,PL230_XFER_W,(nbytes>>2),PL230_CTRL_RPWR_4);
+
+ c=DMA_CHAN_AES128_IP;
+ dma_pl230_table->Primary[c].SrcEndPointer = DMA_PL230_PTR_END(&(aes_ip_chain[0].SrcEndPointer), PL230_XFER_W,(2*4));
+ dma_pl230_table->Primary[c].DstEndPointer = DMA_PL230_PTR_END(&(dma_pl230_table->Alternate[c]), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].Control= DMA_PL230_CTRL_DSTFIX(PL230_CTRL_CYCLE_DEV_CHAIN_PRI,PL230_XFER_W,(2*4),PL230_CTRL_RPWR_4);
+
+ aes_op_chain[0].SrcEndPointer = DMA_PL230_PTR_END(&(AES128->TXTOP128[AES128_BUF_SIZE-nbytes]),PL230_XFER_W,(nbytes>>2));
+ aes_op_chain[0].DstEndPointer = DMA_PL230_PTR_END(result,PL230_XFER_W,(nbytes>>2));
+ aes_op_chain[0].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_BASIC,PL230_XFER_W,(nbytes>>2),PL230_CTRL_RPWR_4);
+
+ c=DMA_CHAN_AES128_OP;
+ dma_pl230_table->Primary[c].SrcEndPointer = DMA_PL230_PTR_END(&(aes_op_chain[0].SrcEndPointer), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].DstEndPointer = DMA_PL230_PTR_END(&(dma_pl230_table->Alternate[c]), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].Control= DMA_PL230_CTRL_DSTFIX(PL230_CTRL_CYCLE_DEV_CHAIN_PRI,PL230_XFER_W,(1*4),PL230_CTRL_RPWR_4);
+
+ // enable DMA controller channels
+ dma_pl230_init((1<<DMA_CHAN_AES128_OP) | (1<<DMA_CHAN_AES128_IP)); // two active
+
+ // and enable DMA requests
+ AES128->DRQ_MSK_SET = (AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ AES128->IRQ_MSK_SET = (AES128_ERR_REQ_BIT | AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ // test to ensure output DMA has started
+ while (!(dma_pl230_channel_active((1<<DMA_CHAN_AES128_OP))))
+ ;
+ while (dma_pl230_channel_active((1<<DMA_CHAN_AES128_OP)))
+ ;
+ while (dma_pl230_channel_active((1<<DMA_CHAN_AES128_OP)))
+ ;
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ DMA_PL230_DMAC->DMA_CFG = 0; /* Disable DMA controller for initialization */
+ dma_pl230_init(0); // none active
+ return;
+}
+
+void aes128_driver_dma8(uint8_t *key, uint32_t nbytes, uint8_t *input,
+ uint8_t *result, uint8_t mode)
+{
+ int c;
+ // Reset engine
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ AES128->QUAL = 0;
+ AES128->CTRL = AES128_CTRL_KEY_REQ_BIT | AES128_CTRL_IP_REQ_BIT | AES128_CTRL_OP_REQ_BIT;
+
+ // Set up parameters
+ if (mode == 1)
+ AES128->CTRL_SET = AES128_ENCODE_BIT; // ENCODE mode
+ if (mode == 0)
+ AES128->CTRL_SET = AES128_BYPASS_BIT; // BYPASS mode
+
+ dma_pl230_data_struct_init(); // initialize
+
+ // program DMA transfers in multiples of 16 bytes
+ aes_ip_chain[0].SrcEndPointer = DMA_PL230_PTR_END(key,PL230_XFER_B,16);
+ aes_ip_chain[0].DstEndPointer = DMA_PL230_PTR_END(&(AES128->KEY128[AES128_BUF_SIZE-16]),PL230_XFER_B,16);
+ aes_ip_chain[0].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_DEV_CHAIN_ALT,PL230_XFER_B,16,PL230_CTRL_RPWR_16);
+
+ aes_ip_chain[1].SrcEndPointer = DMA_PL230_PTR_END(input,PL230_XFER_B,(nbytes));
+ aes_ip_chain[1].DstEndPointer = DMA_PL230_PTR_END(&(AES128->TXTIP128[AES128_BUF_SIZE-nbytes]),PL230_XFER_B,(nbytes));
+ aes_ip_chain[1].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_BASIC,PL230_XFER_B,(nbytes),PL230_CTRL_RPWR_16);
+
+ c=DMA_CHAN_AES128_IP;
+ dma_pl230_table->Primary[c].SrcEndPointer = DMA_PL230_PTR_END(&(aes_ip_chain[0].SrcEndPointer), PL230_XFER_W, (2*4));
+ dma_pl230_table->Primary[c].DstEndPointer = DMA_PL230_PTR_END(&(dma_pl230_table->Alternate[c]), PL230_XFER_W, (1*4));
+ dma_pl230_table->Primary[c].Control= DMA_PL230_CTRL_DSTFIX(PL230_CTRL_CYCLE_DEV_CHAIN_PRI,PL230_XFER_W,(2*4),PL230_CTRL_RPWR_4);
+
+ aes_op_chain[0].SrcEndPointer = DMA_PL230_PTR_END(&(AES128->TXTOP128[AES128_BUF_SIZE-nbytes]),PL230_XFER_B,(nbytes));
+ aes_op_chain[0].DstEndPointer = DMA_PL230_PTR_END(result,PL230_XFER_B,(nbytes));
+ aes_op_chain[0].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_BASIC,PL230_XFER_B,(nbytes),PL230_CTRL_RPWR_16);
+
+ c=DMA_CHAN_AES128_OP;
+ dma_pl230_table->Primary[c].SrcEndPointer = DMA_PL230_PTR_END(&(aes_op_chain[0].SrcEndPointer), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].DstEndPointer = DMA_PL230_PTR_END(&(dma_pl230_table->Alternate[c]), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].Control= DMA_PL230_CTRL_DSTFIX(PL230_CTRL_CYCLE_DEV_CHAIN_PRI,PL230_XFER_W,(1*4),PL230_CTRL_RPWR_4);
+
+ // enable DMA controller channels
+ dma_pl230_init((1<<DMA_CHAN_AES128_OP) | (1<<DMA_CHAN_AES128_IP)); // two active
+
+ // and enable DMA requests
+ AES128->DRQ_MSK_SET = (AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ AES128->IRQ_MSK_SET = (AES128_ERR_REQ_BIT | AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ // test to ensure output DMA has started
+ while (!(dma_pl230_channel_active(1<<DMA_CHAN_AES128_OP)))
+ ;
+ while (dma_pl230_channel_active(1<<DMA_CHAN_AES128_OP))
+ ;
+ while (dma_pl230_channel_active(1<<DMA_CHAN_AES128_OP))
+ ;
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ DMA_PL230_DMAC->DMA_CFG = 0; /* Disable DMA controller for initialization */
+ dma_pl230_init(0); // none active
+ return;
+}
+
+// wrapper functions
+
+void aes128_alignchk_block_dma(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result, uint8_t mode)
+ { uint32_t dma_max = DMA_PL230_MAX_XFERS; // default to 1 K bytes
+ if (((((long)key) & 3)==0) && ((((long)input) & 3)==0) && ((((long)result) & 3)==0)) dma_max=(DMA_PL230_MAX_XFERS<<2);
+ while (nbytes >dma_max) {
+ if (dma_max == DMA_PL230_MAX_XFERS) // 1K bytes DMA
+ aes128_driver_dma8(key, dma_max, input, result, mode);
+ else // 1K words DMA
+ aes128_driver_aligned_dma32(key, dma_max, input, result, mode);
+ nbytes -= dma_max; input += dma_max; result += dma_max;
+ }
+ if (dma_max == DMA_PL230_MAX_XFERS) // up to 1K bytes remaining
+ aes128_driver_dma8(key, nbytes, input, result, mode);
+ else // up to 1K words remaining
+ aes128_driver_aligned_dma32(key, nbytes, input, result, mode);
+ }
+
+void aes128_bypass_dma(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_alignchk_block_dma (key, nbytes, input, result, 0); }
+
+void aes128_encrypt_dma(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_alignchk_block_dma (key, nbytes, input, result, 1); }
+
+void aes128_decrypt_dma(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_alignchk_block_dma (key, nbytes, input, result, 2); }
+
+
+int main(void) {
+ char rx_char [256] = "SoCLabs AES128v1"; // init to 0
+ unsigned char id_string [16] = {0};
+ int i, fail=0;
+ unsigned char * p;
+
+ UartStdOutInit();
+ printf("%s\n",rx_char);
+ printf("AES128 test program\n");
+ printf(" AES128 ID: ");
+ // iterate over 3 32-bit fields
+ p = (unsigned char *)AES128->CORE_NAME;
+ for (i = 0; i < 12; i++) {
+ id_string[i^3]=*p; // fix byte ordering per word
+ p+=1;
+ }
+ id_string[12] = 0;
+ printf("%s\n",id_string);
+
+ aes_key_irq_occurred = 0;
+ aes_key_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP0_IRQn);
+ NVIC_EnableIRQ(EXP0_IRQn);
+ aes_ip_irq_occurred = 0;
+ aes_ip_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP1_IRQn);
+ NVIC_EnableIRQ(EXP1_IRQn);
+ aes_op_irq_occurred = 0;
+ aes_op_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP2_IRQn);
+ NVIC_EnableIRQ(EXP2_IRQn);
+ aes_err_irq_occurred = 0;
+ aes_err_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP3_IRQn);
+ NVIC_EnableIRQ(EXP3_IRQn);
+
+ printf("AES128 SW (memcpy) tests...\n");
+ printf(" AES128 reference pattern test\n");
+
+ printf(" AES128 input/output bypass test\n");
+ aes128_bypass_memcpy(test_key128, sizeof(test_text128), test_text128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+
+ if (aes_key_irq_occurred != 1){ fail++;
+ printf(" ++ AES key request IRQ count = %d\n", aes_key_irq_occurred); }
+ if (aes_ip_irq_occurred != 2){ fail++;
+ printf(" ++ AES inp request missing: IRQ count = %d\n", aes_ip_irq_occurred); }
+ if (aes_op_irq_occurred != 1){ fail++;
+ printf(" ++ AES out request missing: IRQ count = %d\n", aes_op_irq_occurred); }
+ if (aes_err_irq_occurred != 0){ fail++;
+ printf(" ++ AES err request missing: IRQ count = %d\n", aes_err_irq_occurred); }
+
+ printf(" AES128 encrypt test\n");
+ aes128_encrypt_memcpy(test_key128, sizeof(test_text128), test_text128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_exp128);
+
+ printf(" AES128 decrypt test\n");
+ aes128_decrypt_memcpy(test_key128, sizeof(buf128), buf128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+
+ aes_key_irq_occurred = 0;
+ aes_ip_irq_occurred = 0;
+ aes_op_irq_occurred = 0;
+ aes_err_irq_occurred = 0;
+
+ printf(" AES128 logic toggle test\n");
+ printf(" AES128 input/output pattern test\n");
+ aes128_bypass_memcpy(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
+ fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf1, shift_patt);
+
+ if (aes_key_irq_occurred != 1){ fail++;
+ printf(" ++ AES key request IRQ count = %d\n", aes_key_irq_occurred); }
+ if (aes_ip_irq_occurred != (129+1)){ fail++;
+ printf(" ++ AES inp request missing: IRQ count = %d\n", aes_ip_irq_occurred); }
+ if (aes_op_irq_occurred != 129){ fail++;
+ printf(" ++ AES out request missing: IRQ count = %d\n", aes_op_irq_occurred); }
+ if (aes_err_irq_occurred != 0){ fail++;
+ printf(" ++ AES err request missing: IRQ count = %d\n", aes_err_irq_occurred); }
+
+ printf(" AES128 pattern encrypt test\n");
+ aes128_encrypt_memcpy(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
+ printf(" AES128 pattern decrypt test\n");
+ aes128_decrypt_memcpy(test_key128, sizeof(shift_patt), shift_buf1, shift_buf2);
+ fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf2, shift_patt);
+
+ printf("AES128 DMA tests...\n");
+
+ aes_key_irq_occurred = 0;
+ aes_ip_irq_occurred = 0;
+ aes_op_irq_occurred = 0;
+ aes_err_irq_occurred = 0;
+ dma_error_irq_expected = 0;
+ dma_error_irq_occurred = 0;
+ dma_done_irq_expected = 1;
+ dma_done_irq_occurred = 0;
+ NVIC_ClearPendingIRQ(DMA_IRQn);
+ NVIC_EnableIRQ(DMA_IRQn);
+
+ printf(" AES128 dma input/output bypass test\n");
+ aes128_bypass_dma(test_key128, sizeof(test_text128), test_text128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+
+ if (dma_done_irq_occurred < 2){
+ puts ("ERROR: DMA err IRQ missing");
+ fail++;
+ } else
+ printf(" ++ DMA_DONE IRQ count = %d\n", dma_done_irq_occurred);
+
+ printf(" AES128 dma encrypt test\n");
+ aes128_encrypt_dma(test_key128, sizeof(test_text128), test_text128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_exp128);
+
+ printf(" AES128 dma decrypt test\n");
+ aes128_decrypt_dma(test_key128, sizeof(buf128), buf128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+
+ if (dma_done_irq_occurred < 6){
+ puts ("ERROR: DMA err IRQ missing");
+ fail++;
+ } else
+ printf(" ++ DMA_DONE IRQ count = %d\n", dma_done_irq_occurred);
+
+ printf(" AES128 dma unaligned pattern test\n");
+ aes128_bypass_dma(test_key128,(16*63), shift_patt, shift_buf1+3);
+ fail += aes128_buffer_verify((16*63), shift_buf1+3, shift_patt);
+
+ printf(" AES128 dma input/output pattern test\n");
+ aes128_bypass_dma(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
+ fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf1, shift_patt);
+ printf(" AES128 dma pattern encrypt test\n");
+ aes128_encrypt_dma(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
+ printf(" AES128 dma pattern decrypt test\n");
+ aes128_decrypt_dma(test_key128, sizeof(shift_patt), shift_buf1, shift_buf2);
+ fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf2, shift_patt);
+
+ if (dma_done_irq_occurred < (2*7)){
+ puts ("ERROR: DMA err IRQ missing");
+ fail++;
+ } else
+ printf(" ++ DMA_DONE IRQ count = %d\n", dma_done_irq_occurred);
+
+ // check IRQ masked by DRQs - except when Iinput buffer empty after DMA done
+ if (aes_key_irq_occurred != 0){ fail++;
+ printf(" ++ AES key request IRQ count = %d\n", aes_key_irq_occurred); }
+ if (aes_ip_irq_occurred != 7){ fail++;
+ printf(" ++ AES inp request missing: IRQ count = %d\n", aes_ip_irq_occurred); }
+ if (aes_op_irq_occurred != 0){ fail++;
+ printf(" ++ AES out request missing: IRQ count = %d\n", aes_op_irq_occurred); }
+ if (aes_err_irq_occurred != 0){ fail++;
+ printf(" ++ AES err request missing: IRQ count = %d\n", aes_err_irq_occurred); }
+
+ NVIC_DisableIRQ(DMA_IRQn);
+ NVIC_DisableIRQ(EXP0_IRQn);
+ NVIC_DisableIRQ(EXP1_IRQn);
+ NVIC_DisableIRQ(EXP2_IRQn);
+ NVIC_DisableIRQ(EXP3_IRQn);
+
+ printf ("Data retrieved from the AES is: %s\n", id_string);
+ printf ("Data expected from the AES is: %s\n", rx_char);
+ if (fail >0)
+ printf("** AES TESTS FAILED (%d) **\n", fail);
+ else
+ printf("** AES TEST PASSED **\n");
+ // End simulation
+
+
+ UartEndSimulation();
+
+ return 0;
+
+}
+
+/* --------------------------------------------------------------- */
+/* Interrupt handlers */
+/* --------------------------------------------------------------- */
+
+void DMA_Handler(void)
+{
+if ((DMA_PL230_DMAC->ERR_CLR & 1) != 0) {
+ /* DMA interrupt is caused by DMA error */
+ dma_error_irq_occurred ++;
+ DMA_PL230_DMAC->ERR_CLR = 1; /* Clear dma_err */
+ if (dma_error_irq_expected==0) {
+ puts ("ERROR : Unexpected DMA error interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ }
+else {
+ // DMA interrupt is caused by DMA done
+ dma_done_irq_occurred ++;
+ if (dma_done_irq_expected==0) {
+ puts ("ERROR : Unexpected DMA done interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ }
+}
+
+void EXP0_Handler(void)
+{
+ // AES128 interrupt is caused by Key buffer empty IRQ
+ aes_key_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_KEY_REQ_BIT;
+ if (aes_key_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Key buffer empty request interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP1_Handler(void)
+{
+ // AES128 interrupt is caused by Input buffer empty IRQ
+ aes_ip_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_IP_REQ_BIT;
+ if (aes_ip_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Input buffer empty reqest interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP2_Handler(void)
+{
+ // AES128 interrupt is caused by Output buffer full IRQ
+ aes_op_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_OP_REQ_BIT;
+ if (aes_op_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Output buffer full reqest interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP3_Handler(void)
+{
+ // AES128 interrupt is caused by Error IRQ
+ aes_err_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_ERR_REQ_BIT;
+ if (aes_err_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Error interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
diff --git a/system/testcodes/aes128_tests_memcpy/aes128_tests_memcpy.c b/system/testcodes/aes128_tests_memcpy/aes128_tests_memcpy.c
new file mode 100644
index 0000000000000000000000000000000000000000..598d344a351959e33bb00da70b9ab533cef4a80c
--- /dev/null
+++ b/system/testcodes/aes128_tests_memcpy/aes128_tests_memcpy.c
@@ -0,0 +1,435 @@
+#include "CMSDK_CM0.h"
+#include "aes128.h"
+#include <string.h>
+#include "uart_stdout.h"
+#include <stdio.h>
+// memcopy implememtation
+#define os_memcpy memcpy
+#define os_memset memset
+
+volatile int aes_key_irq_occurred;
+volatile int aes_key_irq_expected;
+volatile int aes_ip_irq_occurred;
+volatile int aes_ip_irq_expected;
+volatile int aes_op_irq_occurred;
+volatile int aes_op_irq_expected;
+volatile int aes_err_irq_occurred;
+volatile int aes_err_irq_expected;
+
+ uint8_t _test_key128[AES_KEY_LEN_128] = {
+ 0x75, 0x46, 0x20, 0x67,
+ 0x6e, 0x75, 0x4b, 0x20,
+ 0x79, 0x6d, 0x20, 0x73,
+ 0x74, 0x61, 0x68, 0x54 };
+
+ uint8_t test_key128[AES_KEY_LEN_128] = {
+ 0x54, 0x68, 0x61, 0x74,
+ 0x73, 0x20, 0x6d, 0x79,
+ 0x20, 0x4b, 0x75, 0x6e,
+ 0x67, 0x20, 0x46, 0x75 };
+
+ uint8_t buf128[AES_BLOCK_SIZE] = {
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00 };
+
+ uint8_t _test_text128[AES_BLOCK_SIZE] = {
+ 0x6f, 0x77, 0x54, 0x20,
+ 0x65, 0x6e, 0x69, 0x4e,
+ 0x20, 0x65, 0x6e, 0x4f,
+ 0x20, 0x6f, 0x77, 0x54 };
+
+ uint8_t test_text128[AES_BLOCK_SIZE] = {
+ 0x54, 0x77, 0x6f, 0x20,
+ 0x4f, 0x6e, 0x65, 0x20,
+ 0x4e, 0x69, 0x6e, 0x65,
+ 0x20, 0x54, 0x77, 0x6f };
+
+ uint8_t test_exp128[AES_BLOCK_SIZE] = {
+ 0x29, 0xc3, 0x50, 0x5f,
+ 0x57, 0x14, 0x20, 0xf6,
+ 0x40, 0x22, 0x99, 0xb3,
+ 0x1a, 0x02, 0xd7, 0x3a };
+
+// add extra block[128] with all zeros to toggle bits low
+ uint8_t shift_patt[129*16] = {
+ 0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,//127
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//128
+ };
+
+ uint8_t shift_buf1[sizeof(shift_patt)];
+ uint8_t shift_buf2[sizeof(shift_patt)];
+
+
+/* Note: Hardware supports byte, half-word or word accesses
+ So memcpy() can be used to load/save data
+ And memset() can be used to pad out data-in to 128-bits
+ mode =0 (bypass), =1 (encode) or =2 (decode)
+*/
+void aes128_driver_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input,
+ uint8_t *result, uint8_t mode)
+{
+ // Reset engine
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ AES128->QUAL = 0;
+ AES128->CTRL = AES128_CTRL_KEY_REQ_BIT | AES128_CTRL_IP_REQ_BIT | AES128_CTRL_OP_REQ_BIT | AES128_CTRL_ERR_REQ_BIT;
+
+ // Set up parameters
+ if (mode == 1)
+ AES128->CTRL_SET = AES128_ENCODE_BIT; // ENCODE mode
+ if (mode == 0)
+ AES128->CTRL_SET = AES128_BYPASS_BIT; // BYPASS mode
+
+ AES128->IRQ_MSK_SET = (AES128_ERR_REQ_BIT | AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+
+ // Program Key
+ os_memcpy((uint8_t *)AES128->KEY128, key, AES_KEY_LEN_128);
+ while (!(AES128->STATUS & AES128_KEYOK_BIT))
+ ;
+
+ /* payload */
+ while(nbytes) {
+ uint8_t len = (nbytes > AES_BLOCK_SIZE) ? AES_BLOCK_SIZE : nbytes;
+ /* Align/pad input and load into hardware */
+ os_memcpy((uint8_t *)AES128->TXTIP128, input, len);
+ //patch up any zero-padding
+ if (len < AES_BLOCK_SIZE)
+ os_memset((uint8_t *)&(AES128->TXTIP128[len]), 0, AES_BLOCK_SIZE-len);
+ /* Auto-started! - no need for manual start */
+ /* Poll until completed */
+ while (!(AES128->STATUS & AES128_VALID_BIT))
+ ;
+ os_memcpy(result, (uint8_t *)AES128->TXTOP128, AES_BLOCK_SIZE);
+ /* Accounting */
+ input += len;
+ result += len;
+ nbytes -= len;
+ AES128->IRQ_MSK_SET = (AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ }
+ AES128->CTRL = 0;
+}
+
+// wrapper functions
+
+void aes128_bypass_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_driver_memcpy(key, nbytes, input, result, 0); }
+
+void aes128_encrypt_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_driver_memcpy(key, nbytes, input, result, 1); }
+
+void aes128_decrypt_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_driver_memcpy(key, nbytes, input, result, 2); }
+
+
+int aes128_buffer_verify(uint32_t buflen, uint8_t *buf_A, uint8_t *buf_B)
+{
+ int i, j, fail = 0;
+ for (i=0 ; i < buflen; i++) {
+ if (buf_A[i] != buf_B[i]){
+ fail = 1;
+ break;
+ }
+ }
+ if (fail) {
+ j=i; // print offending block
+ for (i=(j - (j%16)) ; i < (j-(j%16)+16); i++) {
+ if (i%16==0)
+ printf(" //%03d\n", (i>>4));
+ printf("0x%02x,", buf_A[i]);
+ }
+ }
+ if (fail){
+ i=j;
+ printf("Verify compare FAIL\n EXPECTED_RESULT[%2d]= 0x%02x, ACTUAL_RESULT= 0x%02x \n",i, buf_B[i], buf_A[i]);
+ return(-1);
+ }
+ return(0);
+}
+
+
+int main(void) {
+ char rx_char [256] = "SoCLabs AES128v1"; // init to 0
+ unsigned char id_string [16] = {0};
+ int i, fail=0;
+ unsigned char * p;
+
+ UartStdOutInit();
+ printf("%s\n",rx_char);
+ printf("AES128 test program\n");
+ printf(" AES128 ID: ");
+ // iterate over 3 32-bit fields
+ p = (unsigned char *)AES128->CORE_NAME;
+ for (i = 0; i < 12; i++) {
+ id_string[i^3]=*p; // fix byte ordering per word
+ p+=1;
+ }
+ id_string[12] = 0;
+ printf("%s\n",id_string);
+
+ aes_key_irq_occurred = 0;
+ aes_key_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP0_IRQn);
+ NVIC_EnableIRQ(EXP0_IRQn);
+ aes_ip_irq_occurred = 0;
+ aes_ip_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP1_IRQn);
+ NVIC_EnableIRQ(EXP1_IRQn);
+ aes_op_irq_occurred = 0;
+ aes_op_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP2_IRQn);
+ NVIC_EnableIRQ(EXP2_IRQn);
+ aes_err_irq_occurred = 0;
+ aes_err_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP3_IRQn);
+ NVIC_EnableIRQ(EXP3_IRQn);
+
+ printf("AES128 SW (memcpy) tests...\n");
+ printf(" AES128 reference pattern test\n");
+
+ printf(" AES128 input/output bypass test\n");
+ aes128_bypass_memcpy(test_key128, sizeof(test_text128), test_text128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+
+ if (aes_key_irq_occurred != 1){ fail++;
+ printf(" ++ AES key request IRQ count = %d\n", aes_key_irq_occurred); }
+ if (aes_ip_irq_occurred != 2){ fail++;
+ printf(" ++ AES inp request missing: IRQ count = %d\n", aes_ip_irq_occurred); }
+ if (aes_op_irq_occurred != 1){ fail++;
+ printf(" ++ AES out request missing: IRQ count = %d\n", aes_op_irq_occurred); }
+ if (aes_err_irq_occurred != 0){ fail++;
+ printf(" ++ AES err request missing: IRQ count = %d\n", aes_err_irq_occurred); }
+
+ printf(" AES128 encrypt test\n");
+ aes128_encrypt_memcpy(test_key128, sizeof(test_text128), test_text128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_exp128);
+
+ printf(" AES128 decrypt test\n");
+ aes128_decrypt_memcpy(test_key128, sizeof(buf128), buf128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+
+ aes_key_irq_occurred = 0;
+ aes_ip_irq_occurred = 0;
+ aes_op_irq_occurred = 0;
+ aes_err_irq_occurred = 0;
+
+ printf(" AES128 logic toggle test\n");
+ printf(" AES128 input/output pattern test\n");
+ aes128_bypass_memcpy(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
+ fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf1, shift_patt);
+
+ if (aes_key_irq_occurred != 1){ fail++;
+ printf(" ++ AES key request IRQ count = %d\n", aes_key_irq_occurred); }
+ if (aes_ip_irq_occurred != (129+1)){ fail++;
+ printf(" ++ AES inp request missing: IRQ count = %d\n", aes_ip_irq_occurred); }
+ if (aes_op_irq_occurred != 129){ fail++;
+ printf(" ++ AES out request missing: IRQ count = %d\n", aes_op_irq_occurred); }
+ if (aes_err_irq_occurred != 0){ fail++;
+ printf(" ++ AES err request missing: IRQ count = %d\n", aes_err_irq_occurred); }
+
+ printf(" AES128 pattern encrypt test\n");
+ aes128_encrypt_memcpy(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
+ printf(" AES128 pattern decrypt test\n");
+ aes128_decrypt_memcpy(test_key128, sizeof(shift_patt), shift_buf1, shift_buf2);
+ fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf2, shift_patt);
+
+ NVIC_DisableIRQ(EXP0_IRQn);
+ NVIC_DisableIRQ(EXP1_IRQn);
+ NVIC_DisableIRQ(EXP2_IRQn);
+ NVIC_DisableIRQ(EXP3_IRQn);
+
+ printf ("Data retrieved from the AES is: %s\n", id_string);
+ printf ("Data expected from the AES is: %s\n", rx_char);
+ if (fail >0)
+ printf("** AES TESTS FAILED (%d) **\n", fail);
+ else
+ printf("** AES TEST PASSED **\n");
+ // End simulation
+
+
+ UartEndSimulation();
+
+ return 0;
+
+}
+
+/* --------------------------------------------------------------- */
+/* Interrupt handlers */
+/* --------------------------------------------------------------- */
+
+void EXP0_Handler(void)
+{
+ // AES128 interrupt is caused by Key buffer empty IRQ
+ aes_key_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_KEY_REQ_BIT;
+ if (aes_key_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Key buffer empty request interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP1_Handler(void)
+{
+ // AES128 interrupt is caused by Input buffer empty IRQ
+ aes_ip_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_IP_REQ_BIT;
+ if (aes_ip_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Input buffer empty reqest interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP2_Handler(void)
+{
+ // AES128 interrupt is caused by Output buffer full IRQ
+ aes_op_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_OP_REQ_BIT;
+ if (aes_op_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Output buffer full reqest interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP3_Handler(void)
+{
+ // AES128 interrupt is caused by Error IRQ
+ aes_err_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_ERR_REQ_BIT;
+ if (aes_err_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Error interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
diff --git a/system/testcodes/aes128_tests_memcpy/makefile b/system/testcodes/aes128_tests_memcpy/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..ef85d4e64d70bf3df1b5cc4963a54aa7f3debddc
--- /dev/null
+++ b/system/testcodes/aes128_tests_memcpy/makefile
@@ -0,0 +1,253 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0
+
+# Shared software directory
+SOFTWARE_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = aes128_tests_memcpy
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS = -c -O3 -Ospace -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget -I $(SOFTWARE_DIR)/drivers $(USER_DEFINE)
+ARM_ASM_OPTIONS =
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --no_debug --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+dma_pl230_driver.o : $(SOFTWARE_DIR)/drivers/dma_pl230_driver.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o dma_pl230_driver.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF
+ fromelf -c -d -e -s -z -v $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -I $(SOFTWARE_DIR)/drivers \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/system/testcodes/software_list.txt b/system/testcodes/software_list.txt
new file mode 100644
index 0000000000000000000000000000000000000000..4fbf63d48a5b0ad9d218e3c2758a3c50e8484dd3
--- /dev/null
+++ b/system/testcodes/software_list.txt
@@ -0,0 +1,2 @@
+aes128_tests_memcpy
+aes128_tests_dma230
diff --git a/wrapper/regs/cregs.csv b/wrapper/regs/cregs.csv
deleted file mode 100644
index c68d8e50d14cf0175dfaf88bbf9b0a18bee5b30f..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs.csv
+++ /dev/null
@@ -1,5 +0,0 @@
-name idx nbits start access test rval desc
-
-# Wrapper Control Register
-accelerator_en 0 32 0 rw 0 0x00000000 Accelerator Enable Register
-accelerator_channel_en 1 32 0 rw 0 0x00000000 Accelerator Channel Enable Register
\ No newline at end of file
diff --git a/wrapper/regs/cregs/CREGS.h b/wrapper/regs/cregs/CREGS.h
deleted file mode 100644
index 03b467eacbb96e4976e6acf1f83b6ca41610f727..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/CREGS.h
+++ /dev/null
@@ -1,16 +0,0 @@
-// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
-#ifndef CREGS_H
-#define CREGS_H
-
-
-typedef struct
-{
- __IO uint32_t ACCELERATOR_EN; /* Offset: 0x0 (R/W) Accelerator Enable Register */
- __IO uint32_t ACCELERATOR_CHANNEL_EN; /* Offset: 0x4 (R/W) Accelerator Channel Enable Register */
-} CREGS_TypeDef;
-
-#endif
-
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
diff --git a/wrapper/regs/cregs/cregs.inst.sv b/wrapper/regs/cregs/cregs.inst.sv
deleted file mode 100644
index 1ad2ed0a83a321531c11248a382bfbff11e8a078..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/cregs.inst.sv
+++ /dev/null
@@ -1,24 +0,0 @@
-// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
-// START
-logic [31:0] accelerator_en;
-logic [31:0] accelerator_channel_en;
-
-cregs u_cregs (
-
-// clocks and resets
-.clk(pclk),
-.rstn(presetn),
-
-// Synchronous register interface
-.regbus (cregs.sink),
-
-// reg file signals
-.accelerator_en(accelerator_en[31:0]) /* idx 0 */,
-.accelerator_channel_en(accelerator_channel_en[31:0]) /* idx 1 */
-
-);
-// END
-
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
diff --git a/wrapper/regs/cregs/cregs.md b/wrapper/regs/cregs/cregs.md
deleted file mode 100644
index 9e3b82cb35ffeb7efa4fc4aff652b15099b6c5a8..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/cregs.md
+++ /dev/null
@@ -1,15 +0,0 @@
-// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
-# Programmers Model
-
-## Module: CREGS
-
-| Address Offset | Signal Name | Access | Bit width | Start bit | Description |
-| --- | --- | --- | --- | --- | --- |
-|
-| 0x0 | **ACCELERATOR_EN** | RW | 32 | 0 | Accelerator Enable Register |
-| 0x4 | **ACCELERATOR_CHANNEL_EN** | RW | 32 | 0 | Accelerator Channel Enable Register |
-
-
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
diff --git a/wrapper/regs/cregs/cregs.py b/wrapper/regs/cregs/cregs.py
deleted file mode 100644
index de7171d029c45a3c54f1d3bc642e94ae5c8eb5bd..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/cregs.py
+++ /dev/null
@@ -1,15 +0,0 @@
-# // VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
-class Cregs(object):
-
- def __init__(self,base_offset):
- self.base_offset = base_offset
-
-
- self.ACCELERATOR_EN = self.base_offset + 0x0 # Accelerator Enable Register
- self.ACCELERATOR_CHANNEL_EN = self.base_offset + 0x4 # Accelerator Channel Enable Register
- self.ACCELERATOR_CHANNEL_EN = self.base_offset + 0x4 # Accelerator Channel Enable Register
-
-
-# // VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
diff --git a/wrapper/regs/cregs/cregs.sv b/wrapper/regs/cregs/cregs.sv
deleted file mode 100644
index 8c1d454e0d75f8fd4a6516ca743defa770529d2c..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/cregs.sv
+++ /dev/null
@@ -1,138 +0,0 @@
-// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
-//-----------------------------------------------------------------------------
-// SoC Labs APB register Template
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-// VGEN: HEADER
-// Register file contents:
-//{'name': 'accelerator_en', 'idx': '0', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Enable Register'}
-//{'name': 'accelerator_channel_en', 'idx': '1', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Channel Enable Register'}
-
-
-// VGEN: MODULE NAME
-module cregs (
-
-// clocks and resets
- input logic clk,
- input logic rstn,
-
-// APB inteface
- input logic psel,
- input logic [ADDRWIDTH:0] paddr,
- input logic penable,
- input logic pwrite,
- input logic [31:0] pwdata,
-
- output logic [31:0] prdata,
- output logic pready,
- output logic pslverr,
-
-// VGEN: INPUTS TO REGS
-
-
-// VGEN: OUTPUTS FROM REGS
- output logic [31:0] accelerator_en /* idx #0: Accelerator Enable Register */,
- output logic [31:0] accelerator_channel_en /* idx #1: Accelerator Channel Enable Register */
-
-);
-
-//------------------------------------------------------------------------------
-// APB Interface
-//------------------------------------------------------------------------------
-
-logic [ADDRWIDTH-1:0] addr;
-logic read_en;
-logic write_en;
-logic [31:0] wdata;
-logic [31:0] rdata;
-
-// APB interface
-assign pready = 1'b1; //always ready. Can be customized to support waitstate if required.
-assign pslverr = 1'b0; //alwyas OKAY. Can be customized to support error response if required.
-
-
-// register read and write signal
-assign addr = paddr;
-assign read_en = psel & (~pwrite); // assert for whole apb read transfer
-assign write_en = psel & (~penable) & pwrite; // assert for 1st cycle of write transfer
- // It is also possible to change the design to perform the write in the 2nd
- // APB cycle. E.g.
- // assign write_en = psel & penable & pwrite;
- // However, if the design generate waitstate, this expression will result
- // in write_en being asserted for multiple cycles.
-assign wdata = pwdata;
-assign prdata = rdata;
-
-//------------------------------------------------------------------------------
-// Regsiter write
-//------------------------------------------------------------------------------
-
-// VGEN: REG WRITE
-// idx #0
-logic [31:0] accelerator_en_reg;
-always@(posedge clk or negedge rstn) begin
- if(~rstn) begin
- accelerator_en_reg[31:0] <= '0;
- end else begin
- if(write_en & (addr[9:2]==8'h0)) accelerator_en_reg[31:0] <= wdata[31:0];
- end
-end
-assign accelerator_en[31:0] = accelerator_en_reg[31:0];
-
-// idx #1
-logic [31:0] accelerator_channel_en_reg;
-always@(posedge clk or negedge rstn) begin
- if(~rstn) begin
- accelerator_channel_en_reg[31:0] <= '0;
- end else begin
- if(write_en & (addr[9:2]==8'h1)) accelerator_channel_en_reg[31:0] <= wdata[31:0];
- end
-end
-assign accelerator_channel_en[31:0] = accelerator_channel_en_reg[31:0];
-
-
-
-//------------------------------------------------------------------------------
-// Regsiter read
-//------------------------------------------------------------------------------
-
-
-logic [31:0] rdata_o;
-
-always @*
-begin
- if (read_en)
- begin
- rdata_o[31:0] = 32'h00000000;
-
- // VGEN: REG READ
- if(addr[9:2]==8'h0) if(addr[9:2]==8'h0) rdata_o[31:0] = accelerator_en[31:0]; // idx #0
- if(addr[9:2]==8'h1) if(addr[9:2]==8'h1) rdata_o[31:0] = accelerator_channel_en[31:0]; // idx #1
-
- end
- else
- begin
- rdata_o[31:0] = {32'h00000000};
- end
-end
-
-assign rdata[31:0] = rdata_o[31:0];
-
-
-//------------------------------------------------------------------------------
-//
-//------------------------------------------------------------------------------
-
-
-
-
-endmodule
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
diff --git a/wrapper/regs/cregs/cregs.sv.bak b/wrapper/regs/cregs/cregs.sv.bak
deleted file mode 100644
index d0ca98a27542bd6c55bb388c49d4e712213edec3..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/cregs.sv.bak
+++ /dev/null
@@ -1,139 +0,0 @@
-// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:58:58 24/03/2023
-
-//-----------------------------------------------------------------------------
-// SoC Labs APB register Template
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-// VGEN: HEADER
-// Register file contents:
-//{'name': 'accelerator_en', 'idx': '0', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Enable Register'}
-//{'name': 'accelerator_channel_en', 'idx': '1', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Channel Enable Register'}
-
-
-
-// VGEN: MODULE NAME
-module cregs (
-
-// clocks and resets
- input logic clk,
- input logic rstn,
-
-// APB inteface
- input logic psel,
- input logic [ADDRWIDTH:0] paddr,
- input logic penable,
- input logic pwrite,
- input logic [31:0] pwdata,
-
- output logic [31:0] prdata,
- output logic pready,
- output logic pslverr,
-
-// VGEN: INPUTS TO REGS
-
-
-// VGEN: OUTPUTS FROM REGS
- output logic [31:0] accelerator_en /* idx #0: Accelerator Enable Register */,
- output logic [31:0] accelerator_channel_en /* idx #1: Accelerator Channel Enable Register */
-
-);
-
-//------------------------------------------------------------------------------
-// APB Interface
-//------------------------------------------------------------------------------
-
-logic [ADDRWIDTH-1:0] addr;
-logic read_en;
-logic write_en;
-logic [31:0] wdata;
-logic [31:0] rdata;
-
-// APB interface
-assign pready = 1'b1; //always ready. Can be customized to support waitstate if required.
-assign pslverr = 1'b0; //alwyas OKAY. Can be customized to support error response if required.
-
-
-// register read and write signal
-assign addr = paddr;
-assign read_en = psel & (~pwrite); // assert for whole apb read transfer
-assign write_en = psel & (~penable) & pwrite; // assert for 1st cycle of write transfer
- // It is also possible to change the design to perform the write in the 2nd
- // APB cycle. E.g.
- // assign write_en = psel & penable & pwrite;
- // However, if the design generate waitstate, this expression will result
- // in write_en being asserted for multiple cycles.
-assign wdata = pwdata;
-assign prdata = rdata;
-
-//------------------------------------------------------------------------------
-// Regsiter write
-//------------------------------------------------------------------------------
-
-// VGEN: REG WRITE
-// idx #0
-logic [31:0] accelerator_en_reg;
-always@(posedge clk or negedge rstn) begin
- if(~rstn) begin
- accelerator_en_reg[31:0] <= '0;
- end else begin
- if(write_en & (addr[9:2]==8'h0)) accelerator_en_reg[31:0] <= wdata[31:0];
- end
-end
-assign accelerator_en[31:0] = accelerator_en_reg[31:0];
-
-// idx #1
-logic [31:0] accelerator_channel_en_reg;
-always@(posedge clk or negedge rstn) begin
- if(~rstn) begin
- accelerator_channel_en_reg[31:0] <= '0;
- end else begin
- if(write_en & (addr[9:2]==8'h1)) accelerator_channel_en_reg[31:0] <= wdata[31:0];
- end
-end
-assign accelerator_channel_en[31:0] = accelerator_channel_en_reg[31:0];
-
-
-
-//------------------------------------------------------------------------------
-// Regsiter read
-//------------------------------------------------------------------------------
-
-
-logic [31:0] rdata_o;
-
-always @*
-begin
- if (read_en)
- begin
- rdata_o[31:0] = 32'h00000000;
-
- // VGEN: REG READ
- if(addr[9:2]==8'h0) if(addr[9:2]==8'h0) rdata_o[31:0] = accelerator_en[31:0]; // idx #0
- if(addr[9:2]==8'h1) if(addr[9:2]==8'h1) rdata_o[31:0] = accelerator_channel_en[31:0]; // idx #1
-
- end
- else
- begin
- rdata_o[31:0] = {32'h00000000};
- end
-end
-
-assign rdata[31:0] = rdata_o[31:0];
-
-
-//------------------------------------------------------------------------------
-//
-//------------------------------------------------------------------------------
-
-
-
-
-endmodule
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:58:58 24/03/2023
-
diff --git a/wrapper/regs/cregs/cregs_test.c b/wrapper/regs/cregs/cregs_test.c
deleted file mode 100644
index 1e1345d7773956524a5ba397ef41b8a52ff3f2ec..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/cregs_test.c
+++ /dev/null
@@ -1,36 +0,0 @@
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
-#include "cregs_test.h"
-
-// This test is intended to check initial (reset) values of registers
-int cregs_initial_value_test(void) {
- int num_errors=0;
-
- if (SM2_CREGS->ACCELERATOR_EN != 0) {num_errors += 1; puts("ERROR: ACCELERATOR_EN");}
- if (SM2_CREGS->ACCELERATOR_CHANNEL_EN != 0) {num_errors += 1; puts("ERROR: ACCELERATOR_CHANNEL_EN");}
-
-
- return num_errors;
-
-}
-
-// This test is intended to check write read to registers
-int cregs_write_read_test(void) {
- int num_errors=0;
-
- SM2_CREGS->ACCELERATOR_EN = 0xFFFFFFFF; // write all-1s
- if (SM2_CREGS->ACCELERATOR_EN != (0xFFFFFFFF >> (32-32))) {num_errors += 1; puts("ERROR: ACCELERATOR_EN");} // check field is all-1s
- SM2_CREGS->ACCELERATOR_EN = 0x0; // clear field
- if (SM2_CREGS->ACCELERATOR_EN != 0x0) {num_errors += 1; puts("ERROR: ACCELERATOR_EN");} // check field is all-0s
- SM2_CREGS->ACCELERATOR_CHANNEL_EN = 0xFFFFFFFF; // write all-1s
- if (SM2_CREGS->ACCELERATOR_CHANNEL_EN != (0xFFFFFFFF >> (32-32))) {num_errors += 1; puts("ERROR: ACCELERATOR_CHANNEL_EN");} // check field is all-1s
- SM2_CREGS->ACCELERATOR_CHANNEL_EN = 0x0; // clear field
- if (SM2_CREGS->ACCELERATOR_CHANNEL_EN != 0x0) {num_errors += 1; puts("ERROR: ACCELERATOR_CHANNEL_EN");} // check field is all-0s
-
-
- return num_errors;
-
-}
-
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
diff --git a/wrapper/regs/cregs/cregs_test.h b/wrapper/regs/cregs/cregs_test.h
deleted file mode 100644
index eaafa6d2e5aff0be80ce411ad90268044ae87081..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/cregs_test.h
+++ /dev/null
@@ -1,18 +0,0 @@
-// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
-#ifndef CREGS_TEST_H
-#define CREGS_TEST_H
-
-
-#include "SM2_CM0.h"
-
-// This test is intended to check initial (reset) values of registers
-int cregs_initial_value_test(void);
-
-// This test is intended to check write and read to registers
-int cregs_write_read_test(void);
-
-#endif
-
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
diff --git a/wrapper/src/soclabs_ahb_aes128_ctrl.v b/wrapper/src/soclabs_ahb_aes128_ctrl.v
new file mode 100644
index 0000000000000000000000000000000000000000..63b2bc31851807b3e5122ec4a1e9f2872d41a21c
--- /dev/null
+++ b/wrapper/src/soclabs_ahb_aes128_ctrl.v
@@ -0,0 +1,583 @@
+ //-----------------------------------------------------------------------------
+// top-level soclabs example AHB interface
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (C) 2023, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module soclabs_ahb_aes128_ctrl(
+// -------------------------------------------------------
+// MCU interface
+// -------------------------------------------------------
+ input wire ahb_hclk, // Clock
+ input wire ahb_hresetn, // Reset
+ input wire ahb_hsel, // Device select
+ input wire [15:0] ahb_haddr16, // Address for byte select
+ input wire [1:0] ahb_htrans, // Transfer control
+ input wire [2:0] ahb_hsize, // Transfer size
+ input wire [3:0] ahb_hprot, // Protection control
+ input wire ahb_hwrite, // Write control
+ input wire ahb_hready, // Transfer phase done
+ input wire [31:0] ahb_hwdata, // Write data
+ output wire ahb_hreadyout, // Device ready
+ output wire [31:0] ahb_hrdata, // Read data output
+ output wire ahb_hresp, // Device response
+// stream data
+ output wire drq_ipdma128, // (to) DMAC input burst request
+ input wire dlast_ipdma128,// (from) DMAC input burst end (last transfer)
+ output wire drq_opdma128, // (to) DMAC output dma burst request
+ input wire dlast_opdma128,// (from) DMAC output burst end (last transfer)
+ output wire irq_key128,
+ output wire irq_ip128,
+ output wire irq_op128,
+ output wire irq_error,
+ output wire irq_merged // combined interrrupt request (to CPU)
+ );
+
+ //----------------------------------------------------------------
+ // Internal parameter definitions.
+ //----------------------------------------------------------------
+
+///typedef struct {
+/// __I uint32_t CORE_NAME[2]; /* 0x0000-0007 */
+/// __I uint32_t CORE_VERSION; /* 0x0008-000B */
+/// uint32_t RESRV0C; /* 0x000C */
+/// __IO uint32_t CTRL; /* 0x0010 */
+/// __O uint32_t CTRL_SET; /* 0x0014 */
+/// __O uint32_t CTRLL_CLR; /* 0x0018 */
+/// __I uint32_t STATUS; /* 0x001c */
+/// __IO uint32_t QUAL; /* 0x0020 */
+/// uint32_t RESRV24[3]; /* 0x0024 - 2F*/
+/// __IO uint32_t DRQ_MSK; /* 0x0030 */
+/// __O uint32_t DRQ_MSK_SET; /* 0x0034 */
+/// __O uint32_t DRQ_MSK_CLR; /* 0x0038 */
+/// __I uint32_t DRQ_STATUS; /* 0x003C */
+/// __IO uint32_t IRQ_MSK; /* 0x0040 */
+/// __O uint32_t IRQ_MSK_SET; /* 0x0044 */
+/// __O uint32_t IRQ_MSK_CLR; /* 0x0048 */
+/// __I uint32_t IRQ_STATUS; /* 0x004C */
+/// uint32_t RESRV50[4076]; /* 0x0050-0x3FFC (4096-20 words) */
+/// __IO uint8_t KEY128[0x4000]; /* 0x4000-7FFF (0x3FFF is last alias) */
+/// __IO uint8_t TXTIP128[0x4000]; /* 0x8000-BFFF (0x3FFF is last alias) */
+/// __I uint8_t TXTOP128[0x4000]; /* 0xC000-FFFF (0x3FFF is last alias) */
+///} AES128_TypeDef;
+
+
+// CORE ID
+ localparam ADDR_CORE_NAME0 = 16'h0000;
+ localparam ADDR_CORE_NAME1 = 16'h0004;
+ localparam ADDR_CORE_VERSION= 16'h0008;
+ localparam CORE_NAME0 = 32'h61657331; // "aes1"
+ localparam CORE_NAME1 = 32'h32382020; // "28 "
+ localparam CORE_VERSION = 32'h302e3031; // "0.01"
+
+// CTRL control register with bit-set/bit-clear options
+ localparam ADDR_CTRL = 16'h0010;
+ localparam ADDR_CTRL_SET = 16'h0014;
+ localparam ADDR_CTRL_CLR = 16'h0018;
+ localparam CTRL_REG_WIDTH = 8;
+ localparam CTRL_BIT_MAX = (CTRL_REG_WIDTH-1);
+ localparam CTRL_KEY_REQ_BIT = 0;
+ localparam CTRL_IP_REQ_BIT = 1;
+ localparam CTRL_OP_REQ_BIT = 2;
+ localparam CTRL_ERR_REQ_BIT = 3;
+ localparam CTRL_KEYOK_BIT = 4;
+ localparam CTRL_VALID_BIT = 5;
+ localparam CTRL_BYPASS_BIT = 6;
+ localparam CTRL_ENCODE_BIT = 7;
+// STAT status regisyer
+ localparam ADDR_STAT = 16'h001c;
+ localparam STAT_REG_WIDTH = 8;
+ localparam STAT_BIT_MAX = (STAT_REG_WIDTH-1);
+ localparam STAT_KEYREQ_BIT = 0;
+ localparam STAT_INPREQ_BIT = 1;
+ localparam STAT_OUTREQ_BIT = 2;
+ localparam STAT_ERROR_BIT = 3;
+ localparam STAT_KEYOK_BIT = 4;
+ localparam STAT_VALID_BIT = 5;
+
+// QUAL qualifier field
+ localparam ADDR_QUAL = 16'h0020;
+ localparam QUAL_REG_WIDTH = 32;
+ localparam QUAL_BIT_MAX = (QUAL_REG_WIDTH-1);
+
+// DREQ DMAC request control with bit-set/bit-clear options
+ localparam ADDR_DREQ = 16'h0030;
+ localparam ADDR_DREQ_SET = 16'h0034;
+ localparam ADDR_DREQ_CLR = 16'h0038;
+ localparam ADDR_DREQ_ACT = 16'h003c;
+ localparam DREQ_REG_WIDTH = 3;
+ localparam DREQ_BIT_MAX = (DREQ_REG_WIDTH-1);
+ localparam REQ_KEYBUF_BIT = 0;
+ localparam REQ_IP_BUF_BIT = 1;
+ localparam REQ_OP_BUF_BIT = 2;
+
+// IREQ CPU interrupt request control with bit-set/bit-clear options
+ localparam ADDR_IREQ = 16'h0040;
+ localparam ADDR_IREQ_SET = 16'h0044;
+ localparam ADDR_IREQ_CLR = 16'h0048;
+ localparam ADDR_IREQ_ACT = 16'h004c;
+ localparam IREQ_REG_WIDTH = 4;
+ localparam IREQ_BIT_MAX = (IREQ_REG_WIDTH-1);
+ localparam REQ_ERROR_BIT = 3;
+
+ localparam ADDR_KEY_BASE = 16'h4000;
+ localparam ADDR_KEY0 = 16'h4000;
+ localparam ADDR_KEY3 = 16'h400c;
+ localparam ADDR_KEY7 = 16'h401c;
+
+ localparam ADDR_IBUF_BASE = 16'h8000;
+ localparam ADDR_IBUF_0 = 16'h8000;
+ localparam ADDR_IBUF_3 = 16'h800c;
+
+ localparam ADDR_OBUF_BASE = 16'hc000;
+ localparam ADDR_OBUF_3 = 16'hc00c;
+
+
+ // --------------------------------------------------------------------------
+ // Internal regs/wires
+ // --------------------------------------------------------------------------
+
+ reg [15:0] addr16_r;
+ reg sel_r;
+ reg wcyc_r;
+ reg rcyc_r;
+ reg [3:0] byte4_r;
+
+ wire key128_load_ack;
+ wire ip128_load_ack;
+ wire op128_load_ack;
+
+ // --------------------------------------------------------------------------
+ // AHB slave byte buffer interface, support for unaligned data transfers
+ // --------------------------------------------------------------------------
+
+ wire [1:0] byt_adr = ahb_haddr16[1:0];
+ // generate next byte enable decodes for Word/Half/Byte CPU/DMA accesses
+ wire [3:0] byte_nxt;
+ assign byte_nxt[0] = (ahb_hsize[1])|((ahb_hsize[0])&(!byt_adr[1]))|(byt_adr[1:0]==2'b00);
+ assign byte_nxt[1] = (ahb_hsize[1])|((ahb_hsize[0])&(!byt_adr[1]))|(byt_adr[1:0]==2'b01);
+ assign byte_nxt[2] = (ahb_hsize[1])|((ahb_hsize[0])&( byt_adr[1]))|(byt_adr[1:0]==2'b10);
+ assign byte_nxt[3] = (ahb_hsize[1])|((ahb_hsize[0])&( byt_adr[1]))|(byt_adr[1:0]==2'b11);
+
+ // de-pipelined registered access signals
+ always @(posedge ahb_hclk or negedge ahb_hresetn)
+ if (!ahb_hresetn)
+ begin
+ addr16_r <= 16'h0000;
+ sel_r <= 1'b0;
+ wcyc_r <= 1'b0;
+ rcyc_r <= 1'b0;
+ byte4_r <= 4'b0000;
+ end else if (ahb_hready)
+ begin
+ addr16_r <= (ahb_hsel & ahb_htrans[1]) ? ahb_haddr16 : addr16_r;
+ sel_r <= (ahb_hsel & ahb_htrans[1]);
+ wcyc_r <= (ahb_hsel & ahb_htrans[1] & ahb_hwrite);
+ rcyc_r <= (ahb_hsel & ahb_htrans[1] & !ahb_hwrite);
+ byte4_r <= (ahb_hsel & ahb_htrans[1]) ? byte_nxt[3:0] : 4'b0000;
+ end
+
+
+// pipelined "early" last access decodes, for PL230 dma_ack timing to deassert dma requests
+// wire ahb128_last = ahb_hsel & ahb_htrans[1] & ahb_hready & ahb_haddr16[3] & ahb_haddr16[2] & byte_nxt[3];
+// wire ahb128_wlast = ahb_last & ahb_hwrite & |ahb_haddr[15:14]; // address phase of last write transfer
+// wire ahb128_rlast = ahb_last & !ahb_hwrite & |ahb_haddr[15:14]; // address phase of last read transfer
+
+ wire wlast128 = |ahb_haddr16[15:14] & addr16_r[3] & addr16_r[2] & byte4_r[3] & wcyc_r; // write last pulse
+ wire rlast128 = &ahb_haddr16[15:14] & addr16_r[3] & addr16_r[2] & byte4_r[3] & rcyc_r; // read last pulse
+
+ //----------------------------------------------------------------
+ // API register state and wiring
+ //
+ //----------------------------------------------------------------
+
+ reg [CTRL_BIT_MAX:0] control;
+ reg [QUAL_BIT_MAX:0] param;
+ reg [DREQ_BIT_MAX:0] drq_enable;
+ reg [IREQ_BIT_MAX:0] irq_enable;
+
+ wire [STAT_BIT_MAX:0] status;
+ wire [DREQ_BIT_MAX:0] drq_active;
+ wire [IREQ_BIT_MAX:0] irq_active;
+
+ wire [31:0] rd_keybuf;
+ wire [31:0] rd_ipbuf;
+ wire [31:0] rd_opbuf;
+
+ //----------------------------------------------------------------
+ // API write decoder
+ //
+ //----------------------------------------------------------------
+
+ wire sel_mode = sel_r & (addr16_r[15: 8] == 0);
+ wire sel_keybuf = sel_r & (addr16_r[15:14] == 1);
+ wire sel_ipbuf = sel_r & (addr16_r[15:14] == 2);
+ wire sel_opbuf = sel_r & (addr16_r[15:14] == 3);
+// add address map "last" transfer signalling when last (byte) of alias map is written
+ wire alast_key128 = sel_keybuf & wcyc_r & (&addr16_r[13:2]) & byte4_r[3];
+ wire alast_ip128 = sel_ipbuf & wcyc_r & (&addr16_r[13:2]) & byte4_r[3];
+ wire alast_op128 = sel_opbuf & rcyc_r & (&addr16_r[13:2]) & byte4_r[3];
+
+ always @(posedge ahb_hclk or negedge ahb_hresetn)
+ if (!ahb_hresetn) begin
+ control <= {CTRL_REG_WIDTH{1'b0}};
+ param <= {QUAL_REG_WIDTH{1'b0}};
+ drq_enable <= {DREQ_REG_WIDTH{1'b0}};
+ irq_enable <= {IREQ_REG_WIDTH{1'b0}};
+ end
+ else if (sel_mode & wcyc_r & byte4_r[0])
+ case ({addr16_r[15:2],2'b00})
+ ADDR_CTRL : control <= ahb_hwdata[CTRL_BIT_MAX:0]; // overwrite ctl reg
+ ADDR_CTRL_SET: control <= ahb_hwdata[CTRL_BIT_MAX:0] | control; // bit set ctl mask pattern
+ ADDR_CTRL_CLR: control <= ~ahb_hwdata[CTRL_BIT_MAX:0] & control; // bit clear ctl mask pattern
+ ADDR_QUAL : param <= ahb_hwdata[QUAL_BIT_MAX:0]; // write qual pattern
+ ADDR_DREQ : drq_enable <= ahb_hwdata[DREQ_BIT_MAX:0]; // overwrite dreq reg
+ ADDR_DREQ_SET: drq_enable <= ahb_hwdata[DREQ_BIT_MAX:0] | drq_enable; // bit set dreq mask pattern
+ ADDR_DREQ_CLR: drq_enable <= ~ahb_hwdata[DREQ_BIT_MAX:0] & drq_enable; // bit clear dreq mask pattern
+ ADDR_IREQ : irq_enable <= ahb_hwdata[IREQ_BIT_MAX:0]; // overwrite ireq reg
+ ADDR_IREQ_SET: irq_enable <= ahb_hwdata[IREQ_BIT_MAX:0] | irq_enable; // bit set ireq mask pattern
+ ADDR_IREQ_CLR: irq_enable <= ~ahb_hwdata[IREQ_BIT_MAX:0] & irq_enable; // bit clear ireq mask pattern
+ default: ;
+ endcase
+ else if (sel_keybuf & wcyc_r & (dlast_ipdma128 | alast_key128)) // key terminate
+ drq_enable[0] <= 1'b0;
+ else if (sel_ipbuf & wcyc_r & (dlast_ipdma128 | alast_ip128)) // ip-buffer terminate
+ drq_enable[1] <= 1'b0;
+ else if (sel_opbuf & rcyc_r & (dlast_opdma128 | alast_op128)) // op-buffer complete
+ drq_enable[2] <= 1'b0;
+
+ //----------------------------------------------------------------
+ // API read decoder
+ //
+ //----------------------------------------------------------------
+
+reg [31:0] rdata32; // mux read data
+
+ always @*
+ begin : read_decoder
+ rdata32 = 32'hbad0bad;
+ if (sel_r & rcyc_r)
+ case ({addr16_r[15:2],2'b00})
+ ADDR_CORE_NAME0 : rdata32 = CORE_NAME0;
+ ADDR_CORE_NAME1 : rdata32 = CORE_NAME1;
+ ADDR_CORE_VERSION : rdata32 = CORE_VERSION;
+ ADDR_CTRL : rdata32 = {{(32-CTRL_REG_WIDTH){1'b0}}, control};
+ ADDR_STAT : rdata32 = {{(32-STAT_REG_WIDTH){1'b0}}, status};
+ ADDR_QUAL : rdata32 = {{(32-QUAL_REG_WIDTH){1'b0}}, param};
+ ADDR_DREQ : rdata32 = {{(32-DREQ_REG_WIDTH){1'b0}}, drq_enable};
+ ADDR_DREQ_ACT : rdata32 = {{(32-DREQ_REG_WIDTH){1'b0}}, drq_active};
+ ADDR_IREQ : rdata32 = {{(32-IREQ_REG_WIDTH){1'b0}}, irq_enable};
+ ADDR_IREQ_ACT : rdata32 = {{(32-DREQ_REG_WIDTH){1'b0}}, irq_active};
+ default:
+ if (sel_keybuf) rdata32 = rd_keybuf;
+ else if (sel_ipbuf) rdata32 = rd_ipbuf;
+ else if (sel_opbuf) rdata32 = rd_opbuf;
+ endcase
+ end // read_decoder
+
+ assign ahb_hrdata = rdata32;
+
+ assign ahb_hreadyout = 1'b1; // zero wait state interface
+ assign ahb_hresp = 1'b0;
+
+ // --------------------------------------------------------------------------
+ // Key Input Buffer - keybuf
+ // --------------------------------------------------------------------------
+
+ wire [127:0] key128_be;
+
+ soclabs_iobuf_reg128
+ #(.WRITE_ONLY (1),
+ .WRITE_ZPAD (0))
+ u_reg128_key
+ (
+ .clk (ahb_hclk ), // Clock
+ .rst_b (ahb_hresetn ), // Reset
+ .sel_r (sel_keybuf ), // Bank decode select
+ .wcyc_r (wcyc_r ), // Write cycle (wdata32 valid)
+ .rcyc_r (rcyc_r ), // Read cycle (return rdata32)
+ .word2_r (addr16_r[3:2] ), // Address for word select
+ .byte4_r (byte4_r[3:0] ), // Byte select decoded (up to 4 enabled)
+ .wdata32 (ahb_hwdata[31:0]), // Write data (byte lane qualified)
+ .rdata32 (rd_keybuf ), // Read data output
+ .dma128_ack (key128_load_ack ), // DMA burst acknowledge
+ .out128_le ( ), // Big-Endian 128-bit value
+ .out128_be (key128_be ) // Big-Endian 128-bit value
+ );
+
+ // --------------------------------------------------------------------------
+ // Data Input Buffer - ipbuf
+ // --------------------------------------------------------------------------
+
+ wire [127:0] ip128_le;
+ wire [127:0] ip128_be;
+
+ soclabs_iobuf_reg128
+ #(.WRITE_ONLY (0),
+ .WRITE_ZPAD (1))
+ u_reg128_ip
+ (
+ .clk (ahb_hclk ), // Clock
+ .rst_b (ahb_hresetn ), // Reset
+ .sel_r (sel_ipbuf ), // Bank decode select
+ .wcyc_r (wcyc_r ), // Write cycle (wdata32 valid)
+ .rcyc_r (rcyc_r ), // Read cycle (return rdata32)
+ .word2_r (addr16_r[3:2] ), // Address for word select
+ .byte4_r (byte4_r[3:0] ), // Byte select decoded (up to 4 enabled)
+ .wdata32 (ahb_hwdata[31:0]), // Write data (byte lane qualified)
+ .rdata32 (rd_ipbuf ), // Read data output
+ .dma128_ack (ip128_load_ack ), // DMA burst acknowledge
+ .out128_le (ip128_le ), // Big-Endian 128-bit value
+ .out128_be (ip128_be ) // Big-Endian 128-bit value
+ );
+
+ // --------------------------------------------------------------------------
+ // Data Output Buffer - opbufsel_keybuf
+ // --------------------------------------------------------------------------
+
+ wire [127:0] op128_be;
+ wire [127:0] op128_muxed = (control[CTRL_BYPASS_BIT]) ? ip128_be : op128_be;
+
+ wire [31:0] op_slice32 [0:3];
+ assign op_slice32[3] = {op128_muxed[ 7: 0],op128_muxed[ 15: 8],op128_muxed[ 23: 16],op128_muxed[ 31: 24]};
+ assign op_slice32[2] = {op128_muxed[ 39: 32],op128_muxed[ 47: 40],op128_muxed[ 55: 48],op128_muxed[ 63: 56]};
+ assign op_slice32[1] = {op128_muxed[ 71: 64],op128_muxed[ 79: 72],op128_muxed[ 87: 80],op128_muxed[ 95: 88]};
+ assign op_slice32[0] = {op128_muxed[103: 96],op128_muxed[111:104],op128_muxed[119:112],op128_muxed[127:120]};
+
+ // 32-bit addressed read data
+ assign rd_opbuf = op_slice32[addr16_r[3:2]];
+
+ assign op128_load_ack = (sel_opbuf & rcyc_r & addr16_r[3] & addr16_r[2] & byte4_r[3]);
+
+ // --------------------------------------------------------------------------
+ // example aes128 engine timing
+ // --------------------------------------------------------------------------
+ // --------------------------------------------------------------------------
+ // AES-specific control interface
+ // --------------------------------------------------------------------------
+
+wire aes128_encode = control[CTRL_ENCODE_BIT];
+wire aes256_keysize = 1'b0;
+
+wire aes_keyloaded_pulse = key128_load_ack; // pulse on last byte load of key128
+wire aes_dataloaded_pulse= ip128_load_ack; // pulse on last byte load of text128
+wire aes_ready;
+wire aes_valid;
+
+// state machine control
+reg aes_ready_del;
+reg aes_init;
+reg aes_next;
+reg aes_key_busy;
+reg aes_key_rdy;
+reg aes_res_busy;
+reg aes_res_rdy;
+reg aes_err;
+
+ always @(posedge ahb_hclk or negedge ahb_hresetn)
+ if (!ahb_hresetn) begin
+ aes_ready_del <= 1'b0;
+ aes_init <= 1'b0;
+ aes_next <= 1'b0;
+ aes_key_busy <= 1'b0;
+ aes_key_rdy <= 1'b0;
+ aes_res_busy <= 1'b0;
+ aes_res_rdy <= 1'b0;
+ aes_err <= 1'b0;
+ end else begin
+ aes_ready_del <= aes_ready; // delay for rising edge detect
+ aes_init <= aes_keyloaded_pulse;
+ aes_next <= aes_dataloaded_pulse;
+ aes_key_busy <= (aes_init) | (aes_key_busy & !(aes_ready & !aes_ready_del)); // hold until key expansion done
+ aes_key_rdy <= (aes_key_busy & aes_ready & !aes_ready_del) // expanded key ready
+ | (aes_key_rdy & !(sel_keybuf & wcyc_r)); // hold until any key update
+ aes_res_busy <= (aes_next) | (aes_res_busy & !(aes_ready & !aes_ready_del)); // hold until block processing done
+ aes_res_rdy <= (aes_res_busy & aes_ready & !aes_ready_del) // block ready
+ | (aes_res_rdy & !op128_load_ack); // hold until output transferred
+ aes_err <= (!aes_key_rdy & ((sel_ipbuf & wcyc_r) | (sel_opbuf & rcyc_r)))
+ | (aes_err & !(sel_keybuf & wcyc_r));
+ end
+
+ assign drq_active[REQ_KEYBUF_BIT] = control[CTRL_KEY_REQ_BIT] & (!aes_keyloaded_pulse & !aes_init & !aes_key_busy & !aes_key_rdy);
+ assign drq_active[REQ_IP_BUF_BIT] = control[CTRL_IP_REQ_BIT] & (!aes_dataloaded_pulse & !aes_next & !aes_res_busy & !aes_res_rdy & aes_key_rdy);
+ assign drq_active[REQ_OP_BUF_BIT] = control[CTRL_OP_REQ_BIT] & (!aes_res_busy & aes_res_rdy);
+
+// input DMA channel shared by Key and Data-In
+ assign drq_ipdma128 = (drq_enable[REQ_KEYBUF_BIT] & drq_active[REQ_KEYBUF_BIT] & !wlast128) // if key DMA enabled
+ | (drq_enable[REQ_IP_BUF_BIT] & drq_active[REQ_IP_BUF_BIT] & !wlast128) // if ip128 DMA requested
+ ;
+
+// output DMA channel for Data-Out
+ assign drq_opdma128 = (drq_enable[REQ_OP_BUF_BIT] & drq_active[REQ_OP_BUF_BIT] & !rlast128); // if op128 DMA requested
+
+// and Interrupt requests are masked out if corresponding DMA requests are enabled
+ assign irq_active[REQ_KEYBUF_BIT] = drq_active[REQ_KEYBUF_BIT] & !drq_enable[REQ_KEYBUF_BIT];
+ assign irq_active[REQ_IP_BUF_BIT] = drq_active[REQ_IP_BUF_BIT] & !drq_enable[REQ_IP_BUF_BIT];
+ assign irq_active[REQ_OP_BUF_BIT] = drq_active[REQ_OP_BUF_BIT] & !drq_enable[REQ_OP_BUF_BIT];
+ assign irq_active[REQ_ERROR_BIT ] = control[CTRL_ERR_REQ_BIT] & aes_err; // error raised in SW
+
+ assign irq_key128 = irq_active[REQ_KEYBUF_BIT] & irq_enable[REQ_KEYBUF_BIT];
+ assign irq_ip128 = irq_active[REQ_IP_BUF_BIT] & irq_enable[REQ_IP_BUF_BIT];
+ assign irq_op128 = irq_active[REQ_OP_BUF_BIT] & irq_enable[REQ_OP_BUF_BIT];
+ assign irq_error = irq_active[REQ_ERROR_BIT ] & irq_enable[REQ_ERROR_BIT ];
+// merge and mask if not DRQ
+ assign irq_merged = irq_key128 | irq_ip128 | irq_op128 | irq_error;
+
+
+// wire up status port
+ assign status[2:0] = control [2:0];
+ assign status[STAT_ERROR_BIT] = (!aes_res_busy & !aes_key_rdy);
+ assign status[STAT_KEYOK_BIT] = aes_key_rdy;
+ assign status[STAT_VALID_BIT] = aes_res_rdy;
+ assign status[7:6] = control [7:6];
+
+ //----------------------------------------------------------------
+ // core instantiation.
+ //----------------------------------------------------------------
+ aes_core core(
+ .clk(ahb_hclk),
+ .reset_n(ahb_hresetn),
+
+ .encdec(aes128_encode),
+ .init(aes_init),
+ .next(aes_next),
+ .ready(aes_ready),
+
+ .key({key128_be,key128_be}),
+ .keylen(aes256_keysize),
+
+ .block(ip128_be),
+ .result(op128_be),
+ .result_valid(aes_valid)
+ );
+
+endmodule
+
+module soclabs_iobuf_reg128
+ #(
+ parameter WRITE_ONLY = 0,
+ parameter WRITE_ZPAD = 0
+ ) (
+// -------------------------------------------------------
+// de-pipelined register interface
+// -------------------------------------------------------
+// ahb
+ input wire clk, // Clock
+ input wire rst_b, // Reset
+ input wire sel_r, // Bank decode select
+ input wire wcyc_r, // Write cycle (wdata32 valid)
+ input wire rcyc_r, // Read cycle (return rdata32)
+ input wire [1:0] word2_r, // Address for word select
+ input wire [3:0] byte4_r, // Byte select decoded (up to 4 enabled)
+ input wire [31:0] wdata32, // Write data (byte lae qualified)
+ output wire [31:0] rdata32, // Read data output
+ output wire dma128_ack, // DMA burst acknowledge
+ output wire [127:0] out128_le, // Litte-Endian 128-bit value
+ output wire [127:0] out128_be // Big-Endian 128-bit value
+) ;
+
+ reg [7:0] byte0 [0:3];
+ reg [7:0] byte1 [0:3];
+ reg [7:0] byte2 [0:3];
+ reg [7:0] byte3 [0:3];
+ reg ack128;
+
+ wire zpad_cfg = (WRITE_ZPAD==0) ? 1'b0 : 1'b1;
+
+// byte-0 array; flush on write to word-0, byte-0
+// else addressed word byte-0 write
+ always @(posedge clk or negedge rst_b)
+ if (!rst_b)
+ begin byte0[0] <= 8'h00; byte0[1] <= 8'h00; byte0[2] <= 8'h00; byte0[3] <= 8'h00; end
+ else if (zpad_cfg & sel_r & wcyc_r & byte4_r[0] & !word2_r[1] & !word2_r[0]) // Z-PAD rest
+ begin byte0[0] <= wdata32[ 7: 0]; byte0[1] <= 8'h00; byte0[2] <= 8'h00; byte0[3] <= 8'h00; end
+ else if (sel_r & wcyc_r & byte4_r[0])
+ byte0[word2_r[1:0]] <= wdata32[ 7: 0];
+
+// byte-1 array; flush on write to word-0, byte-0 if byte-1 not also written
+// flush rest on write to word-0, byte-0 and byte-1 also written
+// else address word byte-1 write
+ always @(posedge clk or negedge rst_b)
+ if (!rst_b)
+ begin byte1[0] <= 8'h00; byte1[1] <= 8'h00; byte1[2] <= 8'h00; byte1[3] <= 8'h00; end
+ else if (zpad_cfg & sel_r & wcyc_r & !byte4_r[1] & !word2_r[1] & !word2_r[0] & byte4_r[0]) // Z-PAD
+ begin byte1[0] <= 8'h00; byte1[1] <= 8'h00; byte1[2] <= 8'h00; byte1[3] <= 8'h00; end
+ else if (zpad_cfg & sel_r & wcyc_r & byte4_r[1] & !word2_r[1] & !word2_r[0] & byte4_r[0]) // Z-PAD rest
+ begin byte1[0] <= wdata32[15: 8]; byte1[1] <= 8'h00; byte1[2] <= 8'h00; byte1[3] <= 8'h00; end
+ else if (sel_r & wcyc_r & byte4_r[1])
+ byte1[word2_r[1:0]] <= wdata32[15: 8];
+
+// byte-2 array; flush on write to word-0, byte-0 if byte-2 not also written
+// flush rest on write to word-0, byte-0 and byte-2 also written
+// else address word byte-2 write
+ always @(posedge clk or negedge rst_b)
+ if (!rst_b)
+ begin byte2[0] <= 8'h00; byte2[1] <= 8'h00; byte2[2] <= 8'h00; byte2[3] <= 8'h00; end
+ else if (zpad_cfg & sel_r & wcyc_r & !byte4_r[2] & !word2_r[1] & !word2_r[0] & byte4_r[0]) // Z-PAD
+ begin byte2[0] <= 8'h00; byte2[1] <= 8'h00; byte2[2] <= 8'h00; byte2[3] <= 8'h00; end
+ else if (zpad_cfg & sel_r & wcyc_r & byte4_r[2] & !word2_r[1] & !word2_r[0] & byte4_r[0]) // Z-PAD rest
+ begin byte2[0] <= wdata32[23:16]; byte2[1] <= 8'h00; byte2[2] <= 8'h00; byte2[3] <= 8'h00; end
+ else if (sel_r & wcyc_r & byte4_r[2])
+ byte2[word2_r[1:0]] <= wdata32[23:16];
+
+// byte-3 array; flush on write to word-0, byte-0 if byte-3 not also written
+// flush rest on write to word-0, byte-0 and byte-3 also written
+// else address word byte-3 write
+ always @(posedge clk or negedge rst_b)
+ if (!rst_b)
+ begin byte3[0] <= 8'h00; byte3[1] <= 8'h00; byte3[2] <= 8'h00; byte3[3] <= 8'h00; end
+ else if (zpad_cfg & sel_r & wcyc_r & !byte4_r[3] & !word2_r[1] & !word2_r[0] & byte4_r[0]) // Z-PAD
+ begin byte3[0] <= 8'h00; byte3[1] <= 8'h00; byte3[2] <= 8'h00; byte3[3] <= 8'h00; end
+ else if (zpad_cfg & sel_r & wcyc_r & byte4_r[3] & !word2_r[1] & !word2_r[0] & byte4_r[0]) // Z-PAD rest
+ begin byte3[0] <= wdata32[31:24]; byte3[1] <= 8'h00; byte3[2] <= 8'h00; byte3[3] <= 8'h00; end
+ else if (sel_r & wcyc_r & byte4_r[3])
+ byte3[word2_r[1:0]] <= wdata32[31:24];
+
+ // ack on write to final byte [15]
+ always @(posedge clk or negedge rst_b)
+ if (!rst_b)
+ ack128 <= 1'b0;
+ else
+ ack128 <= sel_r & wcyc_r & word2_r[1] & word2_r[0] & byte4_r[3];
+
+ assign dma128_ack = ack128;
+
+// byte reverse per word for Big Endian AES engine
+ assign out128_be = {byte0[0], byte1[0], byte2[0], byte3[0],
+ byte0[1], byte1[1], byte2[1], byte3[1],
+ byte0[2], byte1[2], byte2[2], byte3[2],
+ byte0[3], byte1[3], byte2[3], byte3[3]};
+
+// byte reverse per word for Big Endian AES engine
+ assign out128_le = {byte3[3], byte2[3], byte1[3], byte0[3],
+ byte3[2], byte2[2], byte1[2], byte0[2],
+ byte3[1], byte2[1], byte1[1], byte0[1],
+ byte3[0], byte2[0], byte1[0], byte0[0]};
+
+// little-endian read data (if not Write-Only)
+ assign rdata32 = (sel_r & rcyc_r & (WRITE_ONLY == 0))
+ ? {byte3[word2_r[1:0]], byte2[word2_r[1:0]],
+ byte1[word2_r[1:0]], byte0[word2_r[1:0]]}
+ : 32'h00000000;
+
+endmodule
+
+// include SecWorks IP but fix up default_nettype issues that breaks elsewhere
+
+`include "aes_core.v"
+`default_nettype wire
+`include "aes_encipher_block.v"
+`default_nettype wire
+`include "aes_decipher_block.v"
+`default_nettype wire
+`include "aes_key_mem.v"
+`default_nettype wire
+`include "aes_sbox.v"
+`default_nettype wire
+`include "aes_inv_sbox.v"
+`default_nettype wire
diff --git a/wrapper/src/wrapper_accelerator.sv b/wrapper/src/wrapper_accelerator.sv
deleted file mode 100644
index e90ddf717e35f9f5cf256b24335a20a3f816a0b8..0000000000000000000000000000000000000000
--- a/wrapper/src/wrapper_accelerator.sv
+++ /dev/null
@@ -1,522 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Example Accelerator Wrapper
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module wrapper_accelerator #(
- parameter AHBADDRWIDTH=12,
- parameter INPACKETWIDTH=512,
- parameter CFGSIZEWIDTH=64,
- parameter CFGSCHEMEWIDTH=2,
- parameter OUTPACKETWIDTH=256
- ) (
- input logic HCLK, // Clock
- input logic HRESETn, // Reset
-
- // AHB connection to Initiator
- input logic HSELS,
- input logic [AHBADDRWIDTH-1:0] HADDRS,
- input logic [1:0] HTRANSS,
- input logic [2:0] HSIZES,
- input logic [3:0] HPROTS,
- input logic HWRITES,
- input logic HREADYS,
- input logic [31:0] HWDATAS,
-
- output logic HREADYOUTS,
- output logic HRESPS,
- output logic [31:0] HRDATAS,
-
- // Input Data Request Signal to DMAC
- output logic in_data_req,
-
- // Output Data Request Signal to DMAC
- output logic out_data_req
- );
-
-
- //**********************************************************
- // Internal AHB Parameters
- //**********************************************************
-
- // Input Port Parameters
- localparam [AHBADDRWIDTH-1:0] INPORTADDR = 'h000;
- localparam INPORTAHBADDRWIDTH = AHBADDRWIDTH - 2;
-
- // Output Port Parameters
- localparam [AHBADDRWIDTH-1:0] OUTPORTADDR = 'h400;
- localparam OUTPORTAHBADDRWIDTH = AHBADDRWIDTH - 2;
-
- localparam OUTPACKETBYTEWIDTH = $clog2(OUTPACKETWIDTH/8); // Number of Bytes in Packet
- localparam OUTPACKETSPACEWIDTH = OUTPORTAHBADDRWIDTH-OUTPACKETBYTEWIDTH; // Number of Bits to represent all Packets in Address Space
-
- // Control and Status Register Parameters
- localparam [AHBADDRWIDTH-1:0] CSRADDR = 'h800;
- localparam CSRADDRWIDTH = AHBADDRWIDTH - 2;
-
- //**********************************************************
- // Wrapper AHB Components
- //**********************************************************
-
- //----------------------------------------------------------
- // Internal AHB Decode Logic
- //----------------------------------------------------------
-
- // AHB Target 0 - Engine Input Port
- logic hsel0;
- logic hreadyout0;
- logic hresp0;
- logic [31:0] hrdata0;
-
- // AHB Target 1 - Engine Output Port
- logic hsel1;
- logic hreadyout1;
- logic hresp1;
- logic [31:0] hrdata1;
-
- // AHB Target 2 - CSRs
- logic hsel2;
- logic hreadyout2;
- logic hresp2;
- logic [31:0] hrdata2;
-
- // AHB Target 3 - Default Target
- logic hsel3;
- logic hreadyout3;
- logic hresp3;
- logic [31:0] hrdata3;
-
- // Internal AHB Address Assignment
- assign hsel0 = ((HADDRS < OUTPORTADDR) && (HADDRS >= INPORTADDR)) ? 1'b1:1'b0; // Input Port Select
- assign hsel1 = ((HADDRS < CSRADDR) && (HADDRS >= OUTPORTADDR)) ? 1'b1:1'b0; // Output Port Select
- assign hsel2 = (HADDRS >= CSRADDR) ? 1'b1:1'b0; // CSR Select
- assign hsel3 = (hsel0 | hsel1 | hsel2) ? 1'b0:1'b1; // Default Target Select
-
- // AHB Target Multiplexer
- cmsdk_ahb_slave_mux #(
- 1, //PORT0_ENABLE
- 1, //PORT1_ENABLE
- 1, //PORT2_ENABLE
- 0, //PORT3_ENABLE
- 0, //PORT4_ENABLE
- 0, //PORT5_ENABLE
- 0, //PORT6_ENABLE
- 0, //PORT7_ENABLE
- 0, //PORT8_ENABLE
- 0 //PORT9_ENABLE
- ) u_ahb_slave_mux (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HREADY (HREADYS),
- .HSEL0 (hsel0), // Input Port 0
- .HREADYOUT0 (hreadyout0),
- .HRESP0 (hresp0),
- .HRDATA0 (hrdata0),
- .HSEL1 (hsel1), // Input Port 1
- .HREADYOUT1 (hreadyout1),
- .HRESP1 (hresp1),
- .HRDATA1 (hrdata1),
- .HSEL2 (hsel2), // Input Port 2
- .HREADYOUT2 (hreadyout2),
- .HRESP2 (hresp2),
- .HRDATA2 (hrdata2),
- .HSEL3 (hsel3), // Input Port 3
- .HREADYOUT3 (hreadyout3),
- .HRESP3 (hresp3),
- .HRDATA3 (hrdata3),
- .HSEL4 (1'b0), // Input Port 4
- .HREADYOUT4 (),
- .HRESP4 (),
- .HRDATA4 (),
- .HSEL5 (1'b0), // Input Port 5
- .HREADYOUT5 (),
- .HRESP5 (),
- .HRDATA5 (),
- .HSEL6 (1'b0), // Input Port 6
- .HREADYOUT6 (),
- .HRESP6 (),
- .HRDATA6 (),
- .HSEL7 (1'b0), // Input Port 7
- .HREADYOUT7 (),
- .HRESP7 (),
- .HRDATA7 (),
- .HSEL8 (1'b0), // Input Port 8
- .HREADYOUT8 (),
- .HRESP8 (),
- .HRDATA8 (),
- .HSEL9 (1'b0), // Input Port 9
- .HREADYOUT9 (),
- .HRESP9 (),
- .HRDATA9 (),
-
- .HREADYOUT (HREADYOUTS), // Outputs
- .HRESP (HRESPS),
- .HRDATA (HRDATAS)
- );
-
- //----------------------------------------------------------
- // Input Port Logic
- //----------------------------------------------------------
-
- // Engine Input Port Wire declarations
- logic [INPACKETWIDTH-1:0] in_packet;
- logic in_packet_last;
- logic in_packet_valid;
- logic in_packet_ready;
-
- // DMA
- logic in_dma_req_act;
-
- // Packet Constructor Instantiation
- wrapper_ahb_packet_constructor #(
- INPORTAHBADDRWIDTH,
- INPACKETWIDTH
- ) u_wrapper_data_input_port (
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .hsels (hsel0),
- .haddrs (HADDRS[INPORTAHBADDRWIDTH-1:0]),
- .htranss (HTRANSS),
- .hsizes (HSIZES),
- .hwrites (HWRITES),
- .hreadys (HREADYS),
- .hwdatas (HWDATAS),
-
- .hreadyouts (hreadyout0),
- .hresps (hresp0),
- .hrdatas (hrdata0),
-
- // Valid/Ready Interface
- .packet_data (in_packet),
- .packet_data_last (in_packet_last),
- .packet_data_valid (in_packet_valid),
- .packet_data_ready (in_packet_ready),
-
- // Input Data Request
- .data_req (in_dma_req_act)
- );
-
- //----------------------------------------------------------
- // Configuration Port Logic
- //----------------------------------------------------------
-
- // Engine Configuration Port Wire declarations
- logic [CFGSIZEWIDTH-1:0] cfg_size;
- logic [CFGSCHEMEWIDTH-1:0] cfg_scheme;
- logic cfg_last;
- logic cfg_valid;
- logic cfg_ready;
-
- // Engine Configuration Port Tied-off to fixed values
- assign cfg_size = 64'd512;
- assign cfg_scheme = 2'd0;
- assign cfg_last = 1'b1;
- assign cfg_valid = 1'b1;
-
- //----------------------------------------------------------
- // Output Port Logic
- //----------------------------------------------------------
-
- // Engine Output Port Wire declarations
- logic [OUTPACKETWIDTH-1:0] out_hash;
- logic out_hash_last;
- logic [OUTPACKETSPACEWIDTH-1:0] out_hash_remain;
- logic out_hash_valid;
- logic out_hash_ready;
-
-
- // Relative Read Address for Start of Current Block
- logic [OUTPORTAHBADDRWIDTH-1:0] block_read_addr;
-
- // DMA Request Line
- logic out_dma_req_act;
-
- // Packet Deconstructor Instantiation
- wrapper_ahb_packet_deconstructor #(
- OUTPORTAHBADDRWIDTH,
- OUTPACKETWIDTH
- ) u_wrapper_data_output_port (
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .hsels (hsel1),
- .haddrs (HADDRS[OUTPORTAHBADDRWIDTH-1:0]),
- .htranss (HTRANSS),
- .hsizes (HSIZES),
- .hwrites (HWRITES),
- .hreadys (HREADYS),
- .hwdatas (HWDATAS),
-
- .hreadyouts (hreadyout1),
- .hresps (hresp1),
- .hrdatas (hrdata1),
-
- // Valid/Ready Interface
- .packet_data (out_hash),
- .packet_data_last (out_hash_last),
- .packet_data_remain (out_hash_remain),
- .packet_data_valid (out_hash_valid),
- .packet_data_ready (out_hash_ready),
-
- // Input Data Request
- .data_req (out_dma_req_act),
-
- // Read Address Interface
- .block_read_addr (block_read_addr)
- );
-
- //----------------------------------------------------------
- // Wrapper Control and Staus Registers
- //----------------------------------------------------------
-
- // CSR APB wiring logic
- logic [CSRADDRWIDTH-1:0] CSRPADDR;
- logic CSRPENABLE;
- logic CSRPWRITE;
- logic [3:0] CSRPSTRB;
- logic [2:0] CSRPPROT;
- logic [31:0] CSRPWDATA;
- logic CSRPSEL;
-
- logic CSRAPBACTIVE;
- logic [31:0] CSRPRDATA;
- logic CSRPREADY;
- logic CSRPSLVERR;
-
- // CSR register wiring logic
- logic [CSRADDRWIDTH-1:0] csr_reg_addr;
- logic csr_reg_read_en;
- logic csr_reg_write_en;
- logic [31:0] csr_reg_wdata;
- logic [31:0] csr_reg_rdata;
-
- // AHB to APB Bridge
- cmsdk_ahb_to_apb #(
- CSRADDRWIDTH
- ) u_csr_ahb_apb_bridge (
- .HCLK (HCLK), // Clock
- .HRESETn (HRESETn), // Reset
- .PCLKEN (1'b1), // APB clock enable signal
-
- .HSEL (hsel2), // Device select
- .HADDR (HADDRS[CSRADDRWIDTH-1:0]), // Address
- .HTRANS (HTRANSS), // Transfer control
- .HSIZE (HSIZES), // Transfer size
- .HPROT (4'b1111), // Protection control
- .HWRITE (HWRITES), // Write control
- .HREADY (HREADYS), // Transfer phase done
- .HWDATA (HWDATAS), // Write data
-
- .HREADYOUT (hreadyout2), // Device ready
- .HRDATA (hrdata2), // Read data output
- .HRESP (hresp2), // Device response
-
- // APB Output
- .PADDR (CSRPADDR), // APB Address
- .PENABLE (CSRPENABLE), // APB Enable
- .PWRITE (CSRPWRITE), // APB Write
- .PSTRB (CSRPSTRB), // APB Byte Strobe
- .PPROT (CSRPPROT), // APB Prot
- .PWDATA (CSRPWDATA), // APB write data
- .PSEL (CSRPSEL), // APB Select
-
- .APBACTIVE (CSRAPBACTIVE), // APB bus is active, for clock gating
- // of APB bus
-
- // APB Input
- .PRDATA (CSRPRDATA), // Read data for each APB slave
- .PREADY (CSRPREADY), // Ready for each APB slave
- .PSLVERR (CSRPSLVERR) // Error state for each APB slave
- );
-
- // APB to Register Interface
- cmsdk_apb3_eg_slave_interface #(
- CSRADDRWIDTH
- ) u_csr_reg_inf (
-
- .pclk (HCLK), // pclk
- .presetn (HRESETn), // reset
-
- .psel (CSRPSEL), // apb interface inputs
- .paddr (CSRPADDR),
- .penable (CSRPENABLE),
- .pwrite (CSRPWRITE),
- .pwdata (CSRPWDATA),
-
- .prdata (CSRPRDATA), // apb interface outputs
- .pready (CSRPREADY),
- .pslverr (CSRPSLVERR),
-
- // Register interface
- .addr (csr_reg_addr),
- .read_en (csr_reg_read_en),
- .write_en (csr_reg_write_en),
- .wdata (csr_reg_wdata),
- .rdata (csr_reg_rdata)
- );
-
- logic ctrl_reg_write_en, ctrl_reg_read_en;
- assign ctrl_reg_write_en = csr_reg_write_en & (csr_reg_addr < 10'h100);
- assign ctrl_reg_read_en = csr_reg_read_en & (csr_reg_addr < 10'h100);
- // // Example Register Block
- // cmsdk_apb3_eg_slave_reg #(
- // CSRADDRWIDTH
- // ) u_csr_block (
- // .pclk (HCLK),
- // .presetn (HRESETn),
-
- // // Register interface
- // .addr (csr_reg_addr),
- // .read_en (csr_reg_read_en),
- // .write_en (csr_reg_write_en),
- // .wdata (csr_reg_wdata),
- // .ecorevnum (4'd0),
- // .rdata (csr_reg_rdata)
- // );
-
- //----------------------------------------------------------
- // Default AHB Target Logic
- //----------------------------------------------------------
-
- // AHB Default Target Instantiation
- cmsdk_ahb_default_slave u_ahb_default_slave(
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (hsel3),
- .HTRANS (HTRANSS),
- .HREADY (HREADYS),
- .HREADYOUT (hreadyout3),
- .HRESP (hresp3)
- );
-
- // Default Targets Data is tied off
- assign hrdata3 = {32{1'b0}};
-
- //**********************************************************
- // Wrapper Interrupt Generation
- //**********************************************************
-
- // TODO: Instantiate IRQ Generator
-
- //**********************************************************
- // Wrapper DMA Data Request Generation
- //**********************************************************
-
- wrapper_req_ctrl_reg #(
- CSRADDRWIDTH
- ) u_wrapper_req_ctrl_reg (
- .hclk (HCLK),
- .hresetn (HRESETn),
- .addr (csr_reg_addr),
- .read_en (ctrl_reg_read_en),
- .write_en (ctrl_reg_write_en),
- .wdata (csr_reg_wdata),
- .rdata (csr_reg_rdata),
-
- // Data Transfer Request Signaling
- .req_act_ch0 (in_dma_req_act),
- .req_act_ch1 (out_dma_req_act),
- .req_act_ch2 (1'b0),
- .req_act_ch3 (1'b0),
- .req_act_ch4 (1'b0),
-
- // DMA Request Output
- .drq_ch0 (in_data_req),
- .drq_ch1 (out_data_req),
- .drq_ch2 (),
- .drq_ch3 (),
- .drq_ch4 (),
-
- // Interrupt Request Output
- .irq_ch0 (),
- .irq_ch1 (),
- .irq_ch2 (),
- .irq_ch3 (),
- .irq_ch4 (),
- .irq_merged ()
- );
-
- //**********************************************************
- // Accelerator Engine
- //**********************************************************
-
- //----------------------------------------------------------
- // Accelerator Engine Logic
- //----------------------------------------------------------
-
- logic out_digest_valid;
-
- // Engine Output Port Wire declarations
- logic [OUTPACKETWIDTH-1:0] out_packet;
- logic out_packet_last;
- logic [OUTPACKETSPACEWIDTH-1:0] out_packet_remain;
- logic out_packet_valid;
- logic out_packet_ready;
-
- // Block Packets Remaining Tie-off (only ever one packet per block)
- assign out_packet_remain = {OUTPACKETSPACEWIDTH{1'b0}};
-
- // Hashing Accelerator Instatiation
- wrapper_valid_filter u_valid_filter (
- .clk (HCLK),
- .rst (~HRESETn),
-
- // Data in Channel
- .data_in_valid (in_packet_valid),
- .data_in_ready (in_packet_ready),
- .data_in_last (in_packet_last),
-
- // Data Out Channel
- .data_out_valid (out_digest_valid),
- .payload_out_valid (out_packet_valid)
- );
-
-
- // Hashing Accelerator Instatiation
- sha256_stream u_sha256_stream (
- .clk (HCLK),
- .rst (~HRESETn),
- .mode (1'b1),
-
- // Data in Channel
- .s_tdata_i (in_packet),
- .s_tvalid_i (in_packet_valid),
- .s_tready_o (in_packet_ready),
- .s_tlast_i (in_packet_last),
-
- // Data Out Channel
- .digest_o (out_packet),
- .digest_valid_o (out_digest_valid)
- );
-
- assign out_packet_last = 1'b1;
-
- // Output FIFO (Output has no handshaking)
- fifo_vr #(
- 4,
- 256
- ) u_output_fifo (
- .clk (HCLK),
- .nrst (HRESETn),
- .en (1'b1),
- .sync_rst (1'b0),
- .data_in (out_packet),
- .data_in_last (out_packet_last),
- .data_in_valid (out_packet_valid),
- .data_in_ready (),
- .data_out (out_hash),
- .data_out_valid (out_hash_valid),
- .data_out_ready (out_hash_ready),
- .data_out_last (out_hash_last),
- .status_ptr_dif ()
- );
-endmodule
diff --git a/wrapper/stimulus/ahb_input_hash_stim.fri b/wrapper/stimulus/ahb_input_hash_stim.fri
deleted file mode 100644
index a34d700c550156ba611e7d1773f8cddbf61c1392..0000000000000000000000000000000000000000
--- a/wrapper/stimulus/ahb_input_hash_stim.fri
+++ /dev/null
@@ -1,273 +0,0 @@
-;#-----------------------------------------------------------------------------
-;# SoC Labs Basic Hashing Accelerator Wrapper Input Stimulus File
-;# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-;#
-;# Contributors
-;#
-;# David Mapstone (d.a.mapstone@soton.ac.uk)
-;#
-;# Copyright 2023, SoC Labs (www.soclabs.org)
-;#-----------------------------------------------------------------------------
-;Transaction Address Data Size
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diff --git a/wrapper/stimulus/ahb_input_hash_stim.m2d b/wrapper/stimulus/ahb_input_hash_stim.m2d
deleted file mode 100644
index bd56970de251b776173764ea640dcbe5435e707d..0000000000000000000000000000000000000000
--- a/wrapper/stimulus/ahb_input_hash_stim.m2d
+++ /dev/null
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diff --git a/wrapper/stimulus/input_block_32bit_stim.csv b/wrapper/stimulus/input_block_32bit_stim.csv
deleted file mode 100644
index 3d6bce9ce480ea51c66206dc67ec9a295b6af1a0..0000000000000000000000000000000000000000
--- a/wrapper/stimulus/input_block_32bit_stim.csv
+++ /dev/null
@@ -1,320 +0,0 @@
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diff --git a/wrapper/stimulus/output_hash_32bit_ref.csv b/wrapper/stimulus/output_hash_32bit_ref.csv
deleted file mode 100644
index 76655dd804a388379f79c7d165575c0e54a31bb5..0000000000000000000000000000000000000000
--- a/wrapper/stimulus/output_hash_32bit_ref.csv
+++ /dev/null
@@ -1,80 +0,0 @@
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diff --git a/wrapper/verif/tb_wrapper_secworks_sha256.sv b/wrapper/verif/tb_wrapper_secworks_sha256.sv
deleted file mode 100644
index cbfce6e898aef9a1a5b06fa834391c259e2a901e..0000000000000000000000000000000000000000
--- a/wrapper/verif/tb_wrapper_secworks_sha256.sv
+++ /dev/null
@@ -1,263 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Testbench for Top-level AHB Wrapper
-// Modified from tb_frbm_example.v
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-------------------------------------------------------------------------
-// Abstract : Example for File Reader Bus Master
-// Testbench for the example AHB Lite slave.
-//=========================================================================--
-// `include "wrapper_secworks_sha256.sv"
-
-`timescale 1ns/1ps
-
-import "DPI-C" function string getenv(input string env_name);
-
-module tb_wrapper_secworks_sha256;
-
-parameter CLK_PERIOD = 10;
-parameter ADDRWIDTH = 12;
-
-parameter InputFileName = ("/home/dam1n19/Design/secworks-sha256-project/wrapper/stimulus/ahb_input_hash_stim.m2d");
-parameter MessageTag = "FileReader:";
-parameter StimArraySize = 10000;
-
-
-//********************************************************************************
-// Internal Wires
-//********************************************************************************
-
-// AHB Lite BUS SIGNALS
-wire hready;
-wire hresp;
-wire [31:0] hrdata;
-
-wire [1:0] htrans;
-wire [2:0] hburst;
-wire [3:0] hprot;
-wire [2:0] hsize;
-wire hwrite;
-wire hmastlock;
-wire [31:0] haddr;
-wire [31:0] hwdata;
-
-// Accelerator AHB Signals
-wire hsel0;
-wire hreadyout0;
-wire hresp0;
-wire [31:0] hrdata0;
-
-// Default Slave AHB Signals
-wire hsel1;
-wire hreadyout1;
-wire hresp1;
-wire [31:0] hrdata1;
-
-reg HCLK;
-reg HRESETn;
-
-//********************************************************************************
-// Clock and reset generation
-//********************************************************************************
-
- initial begin
- $write("env = %s\n", getenv("PWD"));
- end
-
-initial
- begin
- $dumpfile("wrapper_secworks_sha256.vcd");
- $dumpvars(0, tb_wrapper_secworks_sha256);
- HRESETn = 1'b0;
- HCLK = 1'b0;
- # (10*CLK_PERIOD);
- HRESETn = 1'b1;
- end
-
-always
- begin
- HCLK = #(CLK_PERIOD/2) ~HCLK;
- end
-
-
-//********************************************************************************
-// Address decoder, need to be changed for other configuration
-//********************************************************************************
-// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator
-// Other addresses : HSEL #1 - Default slave
-
- assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0;
- assign hsel1 = hsel0 ? 1'b0:1'b1;
-
-//********************************************************************************
-// File read bus master:
-// generate AHB Master signal by reading a file which store the AHB Operations
-//********************************************************************************
-
-cmsdk_ahb_fileread_master32 #(InputFileName,
- MessageTag,
- StimArraySize
-) u_ahb_fileread_master32 (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- .HREADY (hready),
- .HRESP ({hresp}), //AHB Lite response to AHB response
- .HRDATA (hrdata),
- .EXRESP (1'b0), // Exclusive response (tie low if not used)
-
-
- .HTRANS (htrans),
- .HBURST (hburst),
- .HPROT (hprot),
- .EXREQ (), // Exclusive access request (not used)
- .MEMATTR (), // Memory attribute (not used)
- .HSIZE (hsize),
- .HWRITE (hwrite),
- .HMASTLOCK (hmastlock),
- .HADDR (haddr),
- .HWDATA (hwdata),
-
- .LINENUM ()
-
- );
-
-
-//********************************************************************************
-// Slave multiplexer module:
-// multiplex the slave signals to master, two ports are enabled
-//********************************************************************************
-
- cmsdk_ahb_slave_mux #(
- 1, //PORT0_ENABLE
- 1, //PORT1_ENABLE
- 0, //PORT2_ENABLE
- 0, //PORT3_ENABLE
- 0, //PORT4_ENABLE
- 0, //PORT5_ENABLE
- 0, //PORT6_ENABLE
- 0, //PORT7_ENABLE
- 0, //PORT8_ENABLE
- 0 //PORT9_ENABLE
- ) u_ahb_slave_mux (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HREADY (hready),
- .HSEL0 (hsel0), // Input Port 0
- .HREADYOUT0 (hreadyout0),
- .HRESP0 (hresp0),
- .HRDATA0 (hrdata0),
- .HSEL1 (hsel1), // Input Port 1
- .HREADYOUT1 (hreadyout1),
- .HRESP1 (hresp1),
- .HRDATA1 (hrdata1),
- .HSEL2 (1'b0), // Input Port 2
- .HREADYOUT2 (),
- .HRESP2 (),
- .HRDATA2 (),
- .HSEL3 (1'b0), // Input Port 3
- .HREADYOUT3 (),
- .HRESP3 (),
- .HRDATA3 (),
- .HSEL4 (1'b0), // Input Port 4
- .HREADYOUT4 (),
- .HRESP4 (),
- .HRDATA4 (),
- .HSEL5 (1'b0), // Input Port 5
- .HREADYOUT5 (),
- .HRESP5 (),
- .HRDATA5 (),
- .HSEL6 (1'b0), // Input Port 6
- .HREADYOUT6 (),
- .HRESP6 (),
- .HRDATA6 (),
- .HSEL7 (1'b0), // Input Port 7
- .HREADYOUT7 (),
- .HRESP7 (),
- .HRDATA7 (),
- .HSEL8 (1'b0), // Input Port 8
- .HREADYOUT8 (),
- .HRESP8 (),
- .HRDATA8 (),
- .HSEL9 (1'b0), // Input Port 9
- .HREADYOUT9 (),
- .HRESP9 (),
- .HRDATA9 (),
-
- .HREADYOUT (hready), // Outputs
- .HRESP (hresp),
- .HRDATA (hrdata)
- );
-
-
-//********************************************************************************
-// Slave module 1: example AHB slave module
-//********************************************************************************
- wrapper_secworks_sha256 #(ADDRWIDTH
- ) accelerator (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .HSELS (hsel0),
- .HADDRS (haddr[ADDRWIDTH-1:0]),
- .HTRANSS (htrans),
- .HSIZES (hsize),
- .HWRITES (hwrite),
- .HREADYS (hready),
- .HWDATAS (hwdata),
-
- .HREADYOUTS (hreadyout0),
- .HRESPS (hresp0),
- .HRDATAS (hrdata0),
-
- // Input Data Request to DMAC
- .in_data_req (),
- .out_data_req ()
- );
-
-
-//********************************************************************************
-// Slave module 2: AHB default slave module
-//********************************************************************************
- cmsdk_ahb_default_slave u_ahb_default_slave(
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (hsel1),
- .HTRANS (htrans),
- .HREADY (hready),
- .HREADYOUT (hreadyout1),
- .HRESP (hresp1)
- );
-
- assign hrdata1 = {32{1'b0}}; // Default slave don't have data
-
- endmodule
\ No newline at end of file
diff --git a/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv b/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv
deleted file mode 100644
index 67579c7a6bb43ad57487c79dad7e6ae4995a8654..0000000000000000000000000000000000000000
--- a/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv
+++ /dev/null
@@ -1,256 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Testbench for Top-level AHB Wrapper
-// Modified from tb_frbm_example.v
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-------------------------------------------------------------------------
-// Abstract : Example for File Reader Bus Master
-// Testbench for the example AHB Lite slave.
-//=========================================================================--
-`include "wrapper_sha256_hashing_stream.sv"
-
-`timescale 1ns/1ps
-
-module tb_wrapper_sha256_hashing_stream;
-
-parameter CLK_PERIOD = 10;
-parameter ADDRWIDTH = 12;
-
-parameter InputFileName = ("../../wrapper/stimulus/ahb_input_hash_stim.m2d");
-parameter MessageTag = "FileReader:";
-parameter StimArraySize = 10000;
-
-
-//********************************************************************************
-// Internal Wires
-//********************************************************************************
-
-// AHB Lite BUS SIGNALS
-wire hready;
-wire hresp;
-wire [31:0] hrdata;
-
-wire [1:0] htrans;
-wire [2:0] hburst;
-wire [3:0] hprot;
-wire [2:0] hsize;
-wire hwrite;
-wire hmastlock;
-wire [31:0] haddr;
-wire [31:0] hwdata;
-
-// Accelerator AHB Signals
-wire hsel0;
-wire hreadyout0;
-wire hresp0;
-wire [31:0] hrdata0;
-
-// Default Slave AHB Signals
-wire hsel1;
-wire hreadyout1;
-wire hresp1;
-wire [31:0] hrdata1;
-
-reg HCLK;
-reg HRESETn;
-
-//********************************************************************************
-// Clock and reset generation
-//********************************************************************************
-
-initial
- begin
- $dumpfile("wrapper_sha256_hashing_stream.vcd");
- $dumpvars(0, tb_wrapper_sha256_hashing_stream);
- HRESETn = 1'b0;
- HCLK = 1'b0;
- # (10*CLK_PERIOD);
- HRESETn = 1'b1;
- end
-
-always
- begin
- HCLK = #(CLK_PERIOD/2) ~HCLK;
- end
-
-
-//********************************************************************************
-// Address decoder, need to be changed for other configuration
-//********************************************************************************
-// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator
-// Other addresses : HSEL #1 - Default slave
-
- assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0;
- assign hsel1 = hsel0 ? 1'b0:1'b1;
-
-//********************************************************************************
-// File read bus master:
-// generate AHB Master signal by reading a file which store the AHB Operations
-//********************************************************************************
-
-cmsdk_ahb_fileread_master32 #(InputFileName,
- MessageTag,
- StimArraySize
-) u_ahb_fileread_master32 (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- .HREADY (hready),
- .HRESP ({hresp}), //AHB Lite response to AHB response
- .HRDATA (hrdata),
- .EXRESP (1'b0), // Exclusive response (tie low if not used)
-
-
- .HTRANS (htrans),
- .HBURST (hburst),
- .HPROT (hprot),
- .EXREQ (), // Exclusive access request (not used)
- .MEMATTR (), // Memory attribute (not used)
- .HSIZE (hsize),
- .HWRITE (hwrite),
- .HMASTLOCK (hmastlock),
- .HADDR (haddr),
- .HWDATA (hwdata),
-
- .LINENUM ()
-
- );
-
-
-//********************************************************************************
-// Slave multiplexer module:
-// multiplex the slave signals to master, two ports are enabled
-//********************************************************************************
-
- cmsdk_ahb_slave_mux #(
- 1, //PORT0_ENABLE
- 1, //PORT1_ENABLE
- 0, //PORT2_ENABLE
- 0, //PORT3_ENABLE
- 0, //PORT4_ENABLE
- 0, //PORT5_ENABLE
- 0, //PORT6_ENABLE
- 0, //PORT7_ENABLE
- 0, //PORT8_ENABLE
- 0 //PORT9_ENABLE
- ) u_ahb_slave_mux (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HREADY (hready),
- .HSEL0 (hsel0), // Input Port 0
- .HREADYOUT0 (hreadyout0),
- .HRESP0 (hresp0),
- .HRDATA0 (hrdata0),
- .HSEL1 (hsel1), // Input Port 1
- .HREADYOUT1 (hreadyout1),
- .HRESP1 (hresp1),
- .HRDATA1 (hrdata1),
- .HSEL2 (1'b0), // Input Port 2
- .HREADYOUT2 (),
- .HRESP2 (),
- .HRDATA2 (),
- .HSEL3 (1'b0), // Input Port 3
- .HREADYOUT3 (),
- .HRESP3 (),
- .HRDATA3 (),
- .HSEL4 (1'b0), // Input Port 4
- .HREADYOUT4 (),
- .HRESP4 (),
- .HRDATA4 (),
- .HSEL5 (1'b0), // Input Port 5
- .HREADYOUT5 (),
- .HRESP5 (),
- .HRDATA5 (),
- .HSEL6 (1'b0), // Input Port 6
- .HREADYOUT6 (),
- .HRESP6 (),
- .HRDATA6 (),
- .HSEL7 (1'b0), // Input Port 7
- .HREADYOUT7 (),
- .HRESP7 (),
- .HRDATA7 (),
- .HSEL8 (1'b0), // Input Port 8
- .HREADYOUT8 (),
- .HRESP8 (),
- .HRDATA8 (),
- .HSEL9 (1'b0), // Input Port 9
- .HREADYOUT9 (),
- .HRESP9 (),
- .HRDATA9 (),
-
- .HREADYOUT (hready), // Outputs
- .HRESP (hresp),
- .HRDATA (hrdata)
- );
-
-
-//********************************************************************************
-// Slave module 1: example AHB slave module
-//********************************************************************************
- wrapper_sha256_hashing_stream #(ADDRWIDTH
- ) accelerator (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .HSELS (hsel0),
- .HADDRS (haddr[ADDRWIDTH-1:0]),
- .HTRANSS (htrans),
- .HSIZES (hsize),
- .HWRITES (hwrite),
- .HREADYS (hready),
- .HWDATAS (hwdata),
-
- .HREADYOUTS (hreadyout0),
- .HRESPS (hresp0),
- .HRDATAS (hrdata0),
-
- // Input Data Request to DMAC
- .in_data_req ()
- );
-
-
-//********************************************************************************
-// Slave module 2: AHB default slave module
-//********************************************************************************
- cmsdk_ahb_default_slave u_ahb_default_slave(
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (hsel1),
- .HTRANS (htrans),
- .HREADY (hready),
- .HREADYOUT (hreadyout1),
- .HRESP (hresp1)
- );
-
- assign hrdata1 = {32{1'b0}}; // Default slave don't have data
-
- endmodule
\ No newline at end of file
diff --git a/wrapper/verif/tb_wrapper_vr_loopback.sv b/wrapper/verif/tb_wrapper_vr_loopback.sv
deleted file mode 100644
index 5e25339e114b82463f362b5f946cc606b96feeec..0000000000000000000000000000000000000000
--- a/wrapper/verif/tb_wrapper_vr_loopback.sv
+++ /dev/null
@@ -1,260 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Testbench for Wrapper Valid-Ready Loopback Test
-// Modified from tb_frbm_example.v
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-------------------------------------------------------------------------
-// Abstract : Example for File Reader Bus Master
-// Testbench for the example AHB Lite slave.
-//=========================================================================--
-`include "cmsdk_ahb_filereadcore.v"
-`include "cmsdk_ahb_fileread_funnel.v"
-`include "cmsdk_ahb_fileread_master32.v"
-`include "cmsdk_ahb_default_slave.v"
-`include "cmsdk_ahb_slave_mux.v"
-`include "wrapper_vr_loopback.sv"
-
-`timescale 1ns/1ps
-
-module tb_wrapper_vr_loopback;
-
-parameter CLK_PERIOD = 10;
-parameter ADDRWIDTH = 12;
-
-// parameter InputFileName = "ahb_input_hash_stim.m2d";
-parameter InputFileName = ("../stimulus/ahb_input_hash_stim.m2d");
-parameter MessageTag = "FileReader:";
-parameter StimArraySize = 10000;
-
-
-//********************************************************************************
-// Internal Wires
-//********************************************************************************
-
-// AHB Lite BUS SIGNALS
-wire hready;
-wire hresp;
-wire [31:0] hrdata;
-
-wire [1:0] htrans;
-wire [2:0] hburst;
-wire [3:0] hprot;
-wire [2:0] hsize;
-wire hwrite;
-wire hmastlock;
-wire [31:0] haddr;
-wire [31:0] hwdata;
-
-// Accelerator AHB Signals
-wire hsel0;
-wire hreadyout0;
-wire hresp0;
-wire [31:0] hrdata0;
-
-// Default Slave AHB Signals
-wire hsel1;
-wire hreadyout1;
-wire hresp1;
-wire [31:0] hrdata1;
-
-reg HCLK;
-reg HRESETn;
-
-//********************************************************************************
-// Clock and reset generation
-//********************************************************************************
-
-initial
- begin
- $dumpfile("wrapper_vr_loopback.vcd");
- $dumpvars(0, tb_wrapper_vr_loopback);
- HRESETn = 1'b0;
- HCLK = 1'b0;
- # (10*CLK_PERIOD);
- HRESETn = 1'b1;
- end
-
-always
- begin
- HCLK = #(CLK_PERIOD/2) ~HCLK;
- end
-
-
-//********************************************************************************
-// Address decoder, need to be changed for other configuration
-//********************************************************************************
-// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator
-// Other addresses : HSEL #1 - Default slave
-
- assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0;
- assign hsel1 = hsel0 ? 1'b0:1'b1;
-
-//********************************************************************************
-// File read bus master:
-// generate AHB Master signal by reading a file which store the AHB Operations
-//********************************************************************************
-
-cmsdk_ahb_fileread_master32 #(InputFileName,
- MessageTag,
- StimArraySize
-) u_ahb_fileread_master32 (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- .HREADY (hready),
- .HRESP ({hresp}), //AHB Lite response to AHB response
- .HRDATA (hrdata),
- .EXRESP (1'b0), // Exclusive response (tie low if not used)
-
-
- .HTRANS (htrans),
- .HBURST (hburst),
- .HPROT (hprot),
- .EXREQ (), // Exclusive access request (not used)
- .MEMATTR (), // Memory attribute (not used)
- .HSIZE (hsize),
- .HWRITE (hwrite),
- .HMASTLOCK (hmastlock),
- .HADDR (haddr),
- .HWDATA (hwdata),
-
- .LINENUM ()
-
- );
-
-
-//********************************************************************************
-// Slave multiplexer module:
-// multiplex the slave signals to master, three ports are enabled
-//********************************************************************************
-
- cmsdk_ahb_slave_mux #(
- 1, //PORT0_ENABLE
- 1, //PORT1_ENABLE
- 1, //PORT2_ENABLE
- 0, //PORT3_ENABLE
- 0, //PORT4_ENABLE
- 0, //PORT5_ENABLE
- 0, //PORT6_ENABLE
- 0, //PORT7_ENABLE
- 0, //PORT8_ENABLE
- 0 //PORT9_ENABLE
- ) u_ahb_slave_mux (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HREADY (hready),
- .HSEL0 (hsel0), // Input Port 0
- .HREADYOUT0 (hreadyout0),
- .HRESP0 (hresp0),
- .HRDATA0 (hrdata0),
- .HSEL1 (hsel1), // Input Port 1
- .HREADYOUT1 (hreadyout1),
- .HRESP1 (hresp1),
- .HRDATA1 (hrdata1),
- .HSEL2 (1'b0), // Input Port 2
- .HREADYOUT2 (),
- .HRESP2 (),
- .HRDATA2 (),
- .HSEL3 (1'b0), // Input Port 3
- .HREADYOUT3 (),
- .HRESP3 (),
- .HRDATA3 (),
- .HSEL4 (1'b0), // Input Port 4
- .HREADYOUT4 (),
- .HRESP4 (),
- .HRDATA4 (),
- .HSEL5 (1'b0), // Input Port 5
- .HREADYOUT5 (),
- .HRESP5 (),
- .HRDATA5 (),
- .HSEL6 (1'b0), // Input Port 6
- .HREADYOUT6 (),
- .HRESP6 (),
- .HRDATA6 (),
- .HSEL7 (1'b0), // Input Port 7
- .HREADYOUT7 (),
- .HRESP7 (),
- .HRDATA7 (),
- .HSEL8 (1'b0), // Input Port 8
- .HREADYOUT8 (),
- .HRESP8 (),
- .HRDATA8 (),
- .HSEL9 (1'b0), // Input Port 9
- .HREADYOUT9 (),
- .HRESP9 (),
- .HRDATA9 (),
-
- .HREADYOUT (hready), // Outputs
- .HRESP (hresp),
- .HRDATA (hrdata)
- );
-
-
-//********************************************************************************
-// Slave module 1: example AHB slave module
-//********************************************************************************
- wrapper_vr_loopback #(ADDRWIDTH
- ) accelerator (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .HSELS (hsel0),
- .HADDRS (haddr[ADDRWIDTH-1:0]),
- .HTRANSS (htrans),
- .HSIZES (hsize),
- .HWRITES (hwrite),
- .HREADYS (hready),
- .HWDATAS (hwdata),
-
- .HREADYOUTS (hreadyout0),
- .HRESPS (hresp0),
- .HRDATAS (hrdata0)
-
- );
-
-
-//********************************************************************************
-// Slave module 2: AHB default slave module
-//********************************************************************************
- cmsdk_ahb_default_slave u_ahb_default_slave(
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (hsel1),
- .HTRANS (htrans),
- .HREADY (hready),
- .HREADYOUT (hreadyout1),
- .HRESP (hresp1)
- );
-
- assign hrdata1 = {32{1'b0}}; // Default slave don't have data
-
- endmodule
\ No newline at end of file