SOC1-167: Created new filelist structure and moved filelsits from nanosoc repo to project repo

engine/set_env.sh

-#-----------------------------------------------------------------------------
-# SoC Labs Environment Setup Script
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright  2023, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-#!/bin/bash
-
-# Get Root Location of Design Structure
-if [ -z $DESIGN_ROOT ]; then
-    # If $DESIGN_ROOT hasn't been set yet
-    DESIGN_ROOT=`git rev-parse --show-superproject-working-tree`
-
-    if [ -z $DESIGN_ROOT ]; then
-        # If not in a submodule - at root
-        DESIGN_ROOT=`git rev-parse --show-toplevel`
-    fi
-
-    # Source Top-Level Sourceme
-    source $DESIGN_ROOT/set_env.sh
-else
-    # Set Environment Variable for this Repository
-    export ACC_ENGINE_DIR="$( cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )"
-
-    # If this Repo is root of workspace
-    if [ $ACC_ENGINE_DIR = $DESIGN_ROOT ]; then
-        echo "Design Workspace: $DESIGN_ROOT" 
-        export DESIGN_ROOT
-        # Set Default Simulator
-        export SIMULATOR="ivlog"
-    fi
-
-    # Source environment variables for all submodules
-    for d in $ACC_ENGINE_DIR/* ; do
-        if [ -e "$d/.git" ]; then
-            if [ -f "$d/set_env.sh" ]; then
-            # If .git file exists - submodule
-                source $d/set_env.sh
-            fi
-        fi
-    done
-
-    # Add Scripts to Path
-    export PATH="$PATH:/$ACC_ENGINE_DIR/flow"
-fi
-

flist/corestone-101/corstone-101_ip.flist

+//-----------------------------------------------------------------------------
+// NanoSoC Corstone-101 Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm Corstone-101
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    DMA-230 search path    =============
++incdir+$(PROJECT_DIR)/system/defines/corstone101
+
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
+
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog
\ No newline at end of file

flist/corestone-101/corstone-101_vip.flist

+//-----------------------------------------------------------------------------
+// NanoSoC Corstone-101 VIP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm Corstone-101 VIP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    DMA-230 search path    =============
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
+
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
\ No newline at end of file

flist/cortex-m0/cortex-m0_ip.flist

+//-----------------------------------------------------------------------------
+// NanoSoC Cortex-M0 Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm Cortex-M0
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    Accelerator Module search path    =============
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
+
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog

flist/debug/adp-control_ip.flist

+//-----------------------------------------------------------------------------
+// NanoSoC ADP Control Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for ADP Control IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    ADP Control search path    =============
+$(NANOSOC_TECH_DIR)/IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v
+$(NANOSOC_TECH_DIR)/IPLIB/ADPcontrol_v1_0/ADPmanager.v
\ No newline at end of file

flist/debug/ft1248_vip.flist

+//-----------------------------------------------------------------------------
+// NanoSoC FT1248 VIP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for FT1248 IO VIP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    FT1248 VIP search path    =============
+$(NANOSOC_TECH_DIR)/IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
\ No newline at end of file

flist/debug/usrt_ip.flist

+//-----------------------------------------------------------------------------
+// NanoSoC APB USRT Control Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for APB USRT IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============   APB USRT search path    =============
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_apb_usrt.v
\ No newline at end of file

flist/dma-230/pl230_ip.flist

+//-----------------------------------------------------------------------------
+// NanoSoC DMA-230 Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm DMA-230
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    DMA-230 search path    =============
++incdir+$(PROJECT_DIR)/system/defines/pl230
+
+$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_ahb_ctrl.v
+$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_apb_regs.v
+$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_dma_data.v
+$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_udma.v
+$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_undefs.v
+

flist/generic_lib/generic_lib.flist

+//-----------------------------------------------------------------------------
+// Generic Library Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Generic Library
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    Accelerator Module search path    =============
+$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
+$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VDDIO.v
+$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VSSIO.v
+$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VDDSOC.v
+$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VSS.v
+$(NANOSOC_TECH_DIR)/GLIB/mem/verilog/SROM_Ax32.v
+$(NANOSOC_TECH_DIR)/GLIB/sync/verilog/SYNCHRONIZER_EDGES.v
\ No newline at end of file

flist/nanosoc/nanosoc_matrix_ip.flist

+//-----------------------------------------------------------------------------
+// NanoSoC Bus Matrix IP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Bus Matrix IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    NanoSoC Bus Matrix IP search path    =============
++incdir+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built
+
+-y $(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built
\ No newline at end of file

flist/nanosoc/nanosoc_vip.flist

+//-----------------------------------------------------------------------------
+// NanoSoC Testbench Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Testbench
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    DMA-230 search path    =============
++incdir+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/
+
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v

flist/wrapper_ip.flist → flist/wrapper/wrapper_ip.flist

@@ -25,7 +25,6 @@ $(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_deconstructor.sv
 $(WRAPPER_TECH_DIR)/hdl/src/wrapper_addr_calc.sv
 $(WRAPPER_TECH_DIR)/hdl/src/wrapper_data_req.sv
 $(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
-// $(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_vr_interface.sv
 $(WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_construct.sv
 $(WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_deconstruct.sv
 $(WRAPPER_TECH_DIR)/hdl/src/wrapper_req_ctrl_reg.sv

nanosoc @ e63f4b85

-Subproject commit 3b65f6f388136905c590e9e067222e5f3679e90e
+Subproject commit e63f4b85974feff6ea93e768c78a4a479f60b513