From cbeeec65d5061485dc996be2caa1b3ec7aa6a09c Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Wed, 26 Apr 2023 11:51:43 +0100
Subject: [PATCH] SOC1-167: Created new filelist structure and moved filelsits
from nanosoc repo to project repo
---
engine/set_env.sh | 50 -----
flist/{ => ahb}/ahb_ip.flist | 0
flist/{ => ahb}/ahb_vip.flist | 0
flist/{ => apb}/apb_ip.flist | 0
flist/corestone-101/corstone-101_ip.flist | 38 ++++
flist/corestone-101/corstone-101_vip.flist | 25 +++
flist/cortex-m0/cortex-m0_ip.flist | 31 +++
flist/debug/adp-control_ip.flist | 20 ++
flist/debug/ft1248_vip.flist | 19 ++
flist/debug/usrt_ip.flist | 19 ++
flist/dma-230/pl230_ip.flist | 26 +++
flist/generic_lib/generic_lib.flist | 25 +++
flist/nanosoc/nanosoc_matrix_ip.flist | 21 ++
flist/nanosoc/nanosoc_vip.flist | 21 ++
flist/{ => primatives}/primatives.flist | 0
.../secworks_sha256_stream.flist} | 0
flist/{ => project}/system.flist | 0
flist/{ => project}/wrapper.flist | 0
flist/{ => wrapper}/wrapper_ip.flist | 1 -
nanosoc | 2 +-
system/defines/pl230/pl230_defs.v | 189 ++++++++++++++++++
system/defines/pl230/pl230_undefs.v | 178 +++++++++++++++++
system/src/nanosoc_exp.v | 41 ++--
wrapper/src/wrapper_secworks_sha256.sv | 5 +-
24 files changed, 640 insertions(+), 71 deletions(-)
delete mode 100755 engine/set_env.sh
rename flist/{ => ahb}/ahb_ip.flist (100%)
rename flist/{ => ahb}/ahb_vip.flist (100%)
rename flist/{ => apb}/apb_ip.flist (100%)
create mode 100644 flist/corestone-101/corstone-101_ip.flist
create mode 100644 flist/corestone-101/corstone-101_vip.flist
create mode 100644 flist/cortex-m0/cortex-m0_ip.flist
create mode 100644 flist/debug/adp-control_ip.flist
create mode 100644 flist/debug/ft1248_vip.flist
create mode 100644 flist/debug/usrt_ip.flist
create mode 100644 flist/dma-230/pl230_ip.flist
create mode 100644 flist/generic_lib/generic_lib.flist
create mode 100644 flist/nanosoc/nanosoc_matrix_ip.flist
create mode 100644 flist/nanosoc/nanosoc_vip.flist
rename flist/{ => primatives}/primatives.flist (100%)
rename flist/{secworks_sha25_stream.flist => project/secworks_sha256_stream.flist} (100%)
rename flist/{ => project}/system.flist (100%)
rename flist/{ => project}/wrapper.flist (100%)
rename flist/{ => wrapper}/wrapper_ip.flist (95%)
create mode 100644 system/defines/pl230/pl230_defs.v
create mode 100644 system/defines/pl230/pl230_undefs.v
diff --git a/engine/set_env.sh b/engine/set_env.sh
deleted file mode 100755
index 1d911c6..0000000
--- a/engine/set_env.sh
+++ /dev/null
@@ -1,50 +0,0 @@
-#-----------------------------------------------------------------------------
-# SoC Labs Environment Setup Script
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright 2023, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-#!/bin/bash
-
-# Get Root Location of Design Structure
-if [ -z $DESIGN_ROOT ]; then
- # If $DESIGN_ROOT hasn't been set yet
- DESIGN_ROOT=`git rev-parse --show-superproject-working-tree`
-
- if [ -z $DESIGN_ROOT ]; then
- # If not in a submodule - at root
- DESIGN_ROOT=`git rev-parse --show-toplevel`
- fi
-
- # Source Top-Level Sourceme
- source $DESIGN_ROOT/set_env.sh
-else
- # Set Environment Variable for this Repository
- export ACC_ENGINE_DIR="$( cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )"
-
- # If this Repo is root of workspace
- if [ $ACC_ENGINE_DIR = $DESIGN_ROOT ]; then
- echo "Design Workspace: $DESIGN_ROOT"
- export DESIGN_ROOT
- # Set Default Simulator
- export SIMULATOR="ivlog"
- fi
-
- # Source environment variables for all submodules
- for d in $ACC_ENGINE_DIR/* ; do
- if [ -e "$d/.git" ]; then
- if [ -f "$d/set_env.sh" ]; then
- # If .git file exists - submodule
- source $d/set_env.sh
- fi
- fi
- done
-
- # Add Scripts to Path
- export PATH="$PATH:/$ACC_ENGINE_DIR/flow"
-fi
-
diff --git a/flist/ahb_ip.flist b/flist/ahb/ahb_ip.flist
similarity index 100%
rename from flist/ahb_ip.flist
rename to flist/ahb/ahb_ip.flist
diff --git a/flist/ahb_vip.flist b/flist/ahb/ahb_vip.flist
similarity index 100%
rename from flist/ahb_vip.flist
rename to flist/ahb/ahb_vip.flist
diff --git a/flist/apb_ip.flist b/flist/apb/apb_ip.flist
similarity index 100%
rename from flist/apb_ip.flist
rename to flist/apb/apb_ip.flist
diff --git a/flist/corestone-101/corstone-101_ip.flist b/flist/corestone-101/corstone-101_ip.flist
new file mode 100644
index 0000000..4420f26
--- /dev/null
+++ b/flist/corestone-101/corstone-101_ip.flist
@@ -0,0 +1,38 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Corstone-101 Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm Corstone-101
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= DMA-230 search path =============
++incdir+$(PROJECT_DIR)/system/defines/corstone101
+
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
+
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog
\ No newline at end of file
diff --git a/flist/corestone-101/corstone-101_vip.flist b/flist/corestone-101/corstone-101_vip.flist
new file mode 100644
index 0000000..1c64fa5
--- /dev/null
+++ b/flist/corestone-101/corstone-101_vip.flist
@@ -0,0 +1,25 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Corstone-101 VIP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm Corstone-101 VIP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= DMA-230 search path =============
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
+
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
\ No newline at end of file
diff --git a/flist/cortex-m0/cortex-m0_ip.flist b/flist/cortex-m0/cortex-m0_ip.flist
new file mode 100644
index 0000000..49a5afa
--- /dev/null
+++ b/flist/cortex-m0/cortex-m0_ip.flist
@@ -0,0 +1,31 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Cortex-M0 Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm Cortex-M0
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= Accelerator Module search path =============
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
+
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
diff --git a/flist/debug/adp-control_ip.flist b/flist/debug/adp-control_ip.flist
new file mode 100644
index 0000000..89ef0af
--- /dev/null
+++ b/flist/debug/adp-control_ip.flist
@@ -0,0 +1,20 @@
+//-----------------------------------------------------------------------------
+// NanoSoC ADP Control Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for ADP Control IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= ADP Control search path =============
+$(NANOSOC_TECH_DIR)/IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v
+$(NANOSOC_TECH_DIR)/IPLIB/ADPcontrol_v1_0/ADPmanager.v
\ No newline at end of file
diff --git a/flist/debug/ft1248_vip.flist b/flist/debug/ft1248_vip.flist
new file mode 100644
index 0000000..870fbbf
--- /dev/null
+++ b/flist/debug/ft1248_vip.flist
@@ -0,0 +1,19 @@
+//-----------------------------------------------------------------------------
+// NanoSoC FT1248 VIP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for FT1248 IO VIP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= FT1248 VIP search path =============
+$(NANOSOC_TECH_DIR)/IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
\ No newline at end of file
diff --git a/flist/debug/usrt_ip.flist b/flist/debug/usrt_ip.flist
new file mode 100644
index 0000000..d2e8c5d
--- /dev/null
+++ b/flist/debug/usrt_ip.flist
@@ -0,0 +1,19 @@
+//-----------------------------------------------------------------------------
+// NanoSoC APB USRT Control Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for APB USRT IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= APB USRT search path =============
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_apb_usrt.v
\ No newline at end of file
diff --git a/flist/dma-230/pl230_ip.flist b/flist/dma-230/pl230_ip.flist
new file mode 100644
index 0000000..978f427
--- /dev/null
+++ b/flist/dma-230/pl230_ip.flist
@@ -0,0 +1,26 @@
+//-----------------------------------------------------------------------------
+// NanoSoC DMA-230 Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm DMA-230
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= DMA-230 search path =============
++incdir+$(PROJECT_DIR)/system/defines/pl230
+
+$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_ahb_ctrl.v
+$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_apb_regs.v
+$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_dma_data.v
+$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_udma.v
+$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_undefs.v
+
diff --git a/flist/generic_lib/generic_lib.flist b/flist/generic_lib/generic_lib.flist
new file mode 100644
index 0000000..dd57578
--- /dev/null
+++ b/flist/generic_lib/generic_lib.flist
@@ -0,0 +1,25 @@
+//-----------------------------------------------------------------------------
+// Generic Library Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Generic Library
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= Accelerator Module search path =============
+$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
+$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VDDIO.v
+$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VSSIO.v
+$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VDDSOC.v
+$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VSS.v
+$(NANOSOC_TECH_DIR)/GLIB/mem/verilog/SROM_Ax32.v
+$(NANOSOC_TECH_DIR)/GLIB/sync/verilog/SYNCHRONIZER_EDGES.v
\ No newline at end of file
diff --git a/flist/nanosoc/nanosoc_matrix_ip.flist b/flist/nanosoc/nanosoc_matrix_ip.flist
new file mode 100644
index 0000000..b03107a
--- /dev/null
+++ b/flist/nanosoc/nanosoc_matrix_ip.flist
@@ -0,0 +1,21 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Bus Matrix IP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Bus Matrix IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= NanoSoC Bus Matrix IP search path =============
++incdir+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built
+
+-y $(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built
\ No newline at end of file
diff --git a/flist/nanosoc/nanosoc_vip.flist b/flist/nanosoc/nanosoc_vip.flist
new file mode 100644
index 0000000..54a1236
--- /dev/null
+++ b/flist/nanosoc/nanosoc_vip.flist
@@ -0,0 +1,21 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Testbench Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Testbench
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= DMA-230 search path =============
++incdir+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/
+
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v
diff --git a/flist/primatives.flist b/flist/primatives/primatives.flist
similarity index 100%
rename from flist/primatives.flist
rename to flist/primatives/primatives.flist
diff --git a/flist/secworks_sha25_stream.flist b/flist/project/secworks_sha256_stream.flist
similarity index 100%
rename from flist/secworks_sha25_stream.flist
rename to flist/project/secworks_sha256_stream.flist
diff --git a/flist/system.flist b/flist/project/system.flist
similarity index 100%
rename from flist/system.flist
rename to flist/project/system.flist
diff --git a/flist/wrapper.flist b/flist/project/wrapper.flist
similarity index 100%
rename from flist/wrapper.flist
rename to flist/project/wrapper.flist
diff --git a/flist/wrapper_ip.flist b/flist/wrapper/wrapper_ip.flist
similarity index 95%
rename from flist/wrapper_ip.flist
rename to flist/wrapper/wrapper_ip.flist
index 373f79d..3304718 100644
--- a/flist/wrapper_ip.flist
+++ b/flist/wrapper/wrapper_ip.flist
@@ -25,7 +25,6 @@ $(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_deconstructor.sv
$(WRAPPER_TECH_DIR)/hdl/src/wrapper_addr_calc.sv
$(WRAPPER_TECH_DIR)/hdl/src/wrapper_data_req.sv
$(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
-// $(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_vr_interface.sv
$(WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_construct.sv
$(WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_deconstruct.sv
$(WRAPPER_TECH_DIR)/hdl/src/wrapper_req_ctrl_reg.sv
diff --git a/nanosoc b/nanosoc
index 3b65f6f..e63f4b8 160000
--- a/nanosoc
+++ b/nanosoc
@@ -1 +1 @@
-Subproject commit 3b65f6f388136905c590e9e067222e5f3679e90e
+Subproject commit e63f4b85974feff6ea93e768c78a4a479f60b513
diff --git a/system/defines/pl230/pl230_defs.v b/system/defines/pl230/pl230_defs.v
new file mode 100644
index 0000000..dcf4f10
--- /dev/null
+++ b/system/defines/pl230/pl230_defs.v
@@ -0,0 +1,189 @@
+//-----------------------------------------------------------------------------
+// customised example Cortex-M0 controller DMA230 configuration
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2021, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+// (C) COPYRIGHT 2006-2007 ARM Limited.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+// File Name : pl230_defs.v
+// Checked In : $Date: 2007-06-06 21:55:22 +0530 (Wed, 06 Jun 2007) $
+// Revision : $Revision: 13823 $
+// State : $state: PL230-DE-98007-r0p0-02rel0 $
+//
+//-----------------------------------------------------------------------------
+// Purpose : Peripheral specific macro definitions
+//
+//-----------------------------------------------------------------------------
+
+
+`ifdef ARM_TIMESCALE_DEFINED
+ `timescale 1ns/1ps
+`endif
+
+// Set the number of channels implemented
+`define PL230_CHNLS 2
+`define PL230_CHNL_BITS 1
+//`define PL230_ONE_CHNL
+
+// Include Integration Test Logic
+`define PL230_INCLUDE_TEST
+
+
+// AHB Interface
+`define PL230_AHB_TRANS_IDLE 2'b00
+`define PL230_AHB_TRANS_NONSEQ 2'b10
+`define PL230_AHB_READ 1'b0
+`define PL230_AHB_WRITE 1'b1
+`define PL230_AHB_SIZE_BYTE 3'b000
+`define PL230_AHB_SIZE_HWORD 3'b001
+`define PL230_AHB_SIZE_WORD 3'b010
+
+// PrimeCell Configuration
+`define PL230_PERIPH_ID_0 8'h30
+`define PL230_PERIPH_ID_1 8'hB2
+`define PL230_PERIPH_ID_2 8'h0B
+`define PL230_PERIPH_ID_3 8'h00
+`define PL230_PERIPH_ID_4 8'h04
+`define PL230_PCELL_ID_0 8'h0D
+`define PL230_PCELL_ID_1 8'hF0
+`define PL230_PCELL_ID_2 8'h05
+`define PL230_PCELL_ID_3 8'hB1
+
+// Memory Mapped Registers
+// Controller Configuration Registers
+`define PL230_ADDR_DMA_STATUS 12'h000
+`define PL230_ADDR_DMA_CFG 12'h004
+`define PL230_ADDR_CTRL_BASE_PTR 12'h008
+`define PL230_ADDR_ALT_CTRL_BASE_PTR 12'h00C
+`define PL230_ADDR_DMA_WAITONREQ_STATUS 12'h010
+`define PL230_ADDR_CHNL_SW_REQUEST 12'h014
+`define PL230_ADDR_CHNL_USEBURST_SET 12'h018
+`define PL230_ADDR_CHNL_USEBURST_CLR 12'h01C
+`define PL230_ADDR_CHNL_REQ_MASK_SET 12'h020
+`define PL230_ADDR_CHNL_REQ_MASK_CLR 12'h024
+`define PL230_ADDR_CHNL_ENABLE_SET 12'h028
+`define PL230_ADDR_CHNL_ENABLE_CLR 12'h02C
+`define PL230_ADDR_CHNL_PRI_ALT_SET 12'h030
+`define PL230_ADDR_CHNL_PRI_ALT_CLR 12'h034
+`define PL230_ADDR_CHNL_PRIORITY_SET 12'h038
+`define PL230_ADDR_CHNL_PRIORITY_CLR 12'h03C
+// Reserved 12'h040
+// Reserved 12'h044
+// Reserved 12'h048
+`define PL230_ADDR_ERR_CLR 12'h04C
+// Integration Test Registers
+`define PL230_ADDR_INTEGRATION_CFG 12'hE00
+// Reserved 12'hE04
+`define PL230_ADDR_STALL_STATUS 12'hE08
+// Reserved 12'hE0C
+`define PL230_ADDR_DMA_REQ_STATUS 12'hE10
+// Reserved 12'hE14
+`define PL230_ADDR_DMA_SREQ_STATUS 12'hE18
+// Reserved 12'hE1C
+`define PL230_ADDR_DMA_DONE_SET 12'hE20
+`define PL230_ADDR_DMA_DONE_CLR 12'hE24
+`define PL230_ADDR_DMA_ACTIVE_SET 12'hE28
+`define PL230_ADDR_DMA_ACTIVE_CLR 12'hE2C
+// Reserved 12'hE30
+// Reserved 12'hE34
+// Reserved 12'hE38
+// Reserved 12'hE3C
+// Reserved 12'hE40
+// Reserved 12'hE44
+`define PL230_ADDR_ERR_SET 12'hE48
+// Reserved 12'hE4C
+// PrimeCell Configuration Registers
+`define PL230_ADDR_PERIPH_ID_4 12'hFD0
+// Reserved 12'hFD4
+// Reserved 12'hFD8
+// Reserved 12'hFDC
+`define PL230_ADDR_PERIPH_ID_0 12'hFE0
+`define PL230_ADDR_PERIPH_ID_1 12'hFE4
+`define PL230_ADDR_PERIPH_ID_2 12'hFE8
+`define PL230_ADDR_PERIPH_ID_3 12'hFEC
+`define PL230_ADDR_PCELL_ID_0 12'hFF0
+`define PL230_ADDR_PCELL_ID_1 12'hFF4
+`define PL230_ADDR_PCELL_ID_2 12'hFF8
+`define PL230_ADDR_PCELL_ID_3 12'hFFC
+
+
+// Bit vector definitions for channel_cfg
+`define PL230_CHANNEL_CFG_BITS 20
+// Destination address increment
+`define PL230_CHANNEL_CFG_DST_INC channel_cfg[19:18]
+`define PL230_HRDATA_DST_INC hrdata[31:30]
+// Destination transfer size
+// Source and destination sizes must match
+// so the same bits as the src_size are used
+`define PL230_CHANNEL_CFG_DST_SIZE channel_cfg[15:14]
+`define PL230_HRDATA_DST_SIZE hrdata[29:28]
+// Source address increment
+`define PL230_CHANNEL_CFG_SRC_INC channel_cfg[17:16]
+`define PL230_HRDATA_SRC_INC hrdata[27:26]
+// Source transfer size
+`define PL230_CHANNEL_CFG_SRC_SIZE channel_cfg[15:14]
+`define PL230_HRDATA_SRC_SIZE hrdata[25:24]
+// Destination AHB protection control
+`define PL230_CHANNEL_CFG_DST_PROT_CTRL channel_cfg[13:11]
+`define PL230_HRDATA_DST_PROT_CTRL hrdata[23:21]
+// Source AHB protection control
+`define PL230_CHANNEL_CFG_SRC_PROT_CTRL channel_cfg[10:8]
+`define PL230_HRDATA_SRC_PROT_CTRL hrdata[20:18]
+// Power of two transactions per request
+`define PL230_CHANNEL_CFG_R channel_cfg[7:4]
+`define PL230_HRDATA_R hrdata[17:14]
+// Number of bits in the N counter - hrdata[13:4]
+`define PL230_N_COUNT_BITS 10
+// Lsb bit offset for n_minus_1
+`define PL230_N_COUNT_OFFSET 4
+// Set chnl_useburst_status
+`define PL230_CHANNEL_CFG_NEXT_USEBURST channel_cfg[3]
+`define PL230_HRDATA_NEXT_USEBURST hrdata[3]
+// DMA cycle control
+`define PL230_CHANNEL_CFG_CYCLE_CTRL channel_cfg[2:0]
+`define PL230_HRDATA_CYCLE_CTRL hrdata[2:0]
+
+
+// Number of bits for the statemachine
+`define PL230_STATE_BITS 4
+// Statemachine state encoding
+`define PL230_ST_IDLE 4'h0
+`define PL230_ST_RD_CTRL 4'h1
+`define PL230_ST_RD_SPTR 4'h2
+`define PL230_ST_RD_DPTR 4'h3
+`define PL230_ST_RD_SDAT 4'h4
+`define PL230_ST_WR_DDAT 4'h5
+`define PL230_ST_WAIT 4'h6
+`define PL230_ST_WR_CTRL 4'h7
+`define PL230_ST_STALL 4'h8
+`define PL230_ST_DONE 4'h9
+`define PL230_ST_PSGP 4'hA
+`define PL230_ST_RESVD_0 4'hB
+`define PL230_ST_RESVD_1 4'hC
+`define PL230_ST_RESVD_2 4'hD
+`define PL230_ST_RESVD_3 4'hE
+`define PL230_ST_RESVD_4 4'hF
+
+`define PL230_SIZE_BYTE 2'b00
+`define PL230_SIZE_HWORD 2'b01
+`define PL230_SIZE_WORD 2'b10
+`define PL230_SIZE_RESVD 2'b11
+
+// pl230_defs.v end
diff --git a/system/defines/pl230/pl230_undefs.v b/system/defines/pl230/pl230_undefs.v
new file mode 100644
index 0000000..0722386
--- /dev/null
+++ b/system/defines/pl230/pl230_undefs.v
@@ -0,0 +1,178 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+// (C) COPYRIGHT 2006-2007 ARM Limited.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+// File Name : pl230_undefs.v
+// Checked In : $Date: 2007-03-15 15:17:04 +0530 (Thu, 15 Mar 2007) $
+// Revision : $Revision: 10866 $
+// State : $state: PL230-DE-98007-r0p0-02rel0 $
+//
+//-----------------------------------------------------------------------------
+// Purpose : Undefine peripheral specific macro definitions
+//
+//-----------------------------------------------------------------------------
+
+
+
+
+
+
+// Set the number of channels implemented
+`undef PL230_CHNLS
+`undef PL230_CHNL_BITS
+`undef PL230_ONE_CHNL
+
+// Include Integration Test Logic
+`undef PL230_INCLUDE_TEST
+
+
+// AHB Interface
+`undef PL230_AHB_TRANS_IDLE
+`undef PL230_AHB_TRANS_NONSEQ
+`undef PL230_AHB_READ
+`undef PL230_AHB_WRITE
+`undef PL230_AHB_SIZE_BYTE
+`undef PL230_AHB_SIZE_HWORD
+`undef PL230_AHB_SIZE_WORD
+
+// PrimeCell Configuration
+`undef PL230_PERIPH_ID_0
+`undef PL230_PERIPH_ID_1
+`undef PL230_PERIPH_ID_2
+`undef PL230_PERIPH_ID_3
+`undef PL230_PERIPH_ID_4
+`undef PL230_PCELL_ID_0
+`undef PL230_PCELL_ID_1
+`undef PL230_PCELL_ID_2
+`undef PL230_PCELL_ID_3
+
+// Memory Mapped Registers
+// Controller Configuration Registers
+`undef PL230_ADDR_DMA_STATUS
+`undef PL230_ADDR_DMA_CFG
+`undef PL230_ADDR_CTRL_BASE_PTR
+`undef PL230_ADDR_ALT_CTRL_BASE_PTR
+`undef PL230_ADDR_DMA_WAITONREQ_STATUS
+`undef PL230_ADDR_CHNL_SW_REQUEST
+`undef PL230_ADDR_CHNL_USEBURST_SET
+`undef PL230_ADDR_CHNL_USEBURST_CLR
+`undef PL230_ADDR_CHNL_REQ_MASK_SET
+`undef PL230_ADDR_CHNL_REQ_MASK_CLR
+`undef PL230_ADDR_CHNL_ENABLE_SET
+`undef PL230_ADDR_CHNL_ENABLE_CLR
+`undef PL230_ADDR_CHNL_PRI_ALT_SET
+`undef PL230_ADDR_CHNL_PRI_ALT_CLR
+`undef PL230_ADDR_CHNL_PRIORITY_SET
+`undef PL230_ADDR_CHNL_PRIORITY_CLR
+// Reserved
+// Reserved
+// Reserved
+`undef PL230_ADDR_ERR_CLR
+// Integration Test Registers
+`undef PL230_ADDR_INTEGRATION_CFG
+// Reserved
+`undef PL230_ADDR_STALL_STATUS
+// Reserved
+`undef PL230_ADDR_DMA_REQ_STATUS
+// Reserved
+`undef PL230_ADDR_DMA_SREQ_STATUS
+// Reserved
+`undef PL230_ADDR_DMA_DONE_SET
+`undef PL230_ADDR_DMA_DONE_CLR
+`undef PL230_ADDR_DMA_ACTIVE_SET
+`undef PL230_ADDR_DMA_ACTIVE_CLR
+// Reserved
+// Reserved
+// Reserved
+// Reserved
+// Reserved
+// Reserved
+`undef PL230_ADDR_ERR_SET
+// Reserved
+// PrimeCell Configuration Registers
+`undef PL230_ADDR_PERIPH_ID_4
+// Reserved
+// Reserved
+// Reserved
+`undef PL230_ADDR_PERIPH_ID_0
+`undef PL230_ADDR_PERIPH_ID_1
+`undef PL230_ADDR_PERIPH_ID_2
+`undef PL230_ADDR_PERIPH_ID_3
+`undef PL230_ADDR_PCELL_ID_0
+`undef PL230_ADDR_PCELL_ID_1
+`undef PL230_ADDR_PCELL_ID_2
+`undef PL230_ADDR_PCELL_ID_3
+
+
+// Bit vector definitions for channel_cfg
+`undef PL230_CHANNEL_CFG_BITS
+// Destination address increment
+`undef PL230_CHANNEL_CFG_DST_INC
+`undef PL230_HRDATA_DST_INC
+// Destination transfer size
+// Source and destination sizes must match
+// so the same bits as the src_size are used
+`undef PL230_CHANNEL_CFG_DST_SIZE
+`undef PL230_HRDATA_DST_SIZE
+// Source address increment
+`undef PL230_CHANNEL_CFG_SRC_INC
+`undef PL230_HRDATA_SRC_INC
+// Source transfer size
+`undef PL230_CHANNEL_CFG_SRC_SIZE
+`undef PL230_HRDATA_SRC_SIZE
+// Destination AHB protection control
+`undef PL230_CHANNEL_CFG_DST_PROT_CTRL
+`undef PL230_HRDATA_DST_PROT_CTRL
+// Source AHB protection control
+`undef PL230_CHANNEL_CFG_SRC_PROT_CTRL
+`undef PL230_HRDATA_SRC_PROT_CTRL
+// Power of two transactions per request
+`undef PL230_CHANNEL_CFG_R
+`undef PL230_HRDATA_R
+// Number of bits in the N counter - hrdata[13:4]
+`undef PL230_N_COUNT_BITS
+// Lsb bit offset for n_minus_1
+`undef PL230_N_COUNT_OFFSET
+// Set chnl_useburst_status
+`undef PL230_CHANNEL_CFG_NEXT_USEBURST
+`undef PL230_HRDATA_NEXT_USEBURST
+// DMA cycle control
+`undef PL230_CHANNEL_CFG_CYCLE_CTRL
+`undef PL230_HRDATA_CYCLE_CTRL
+
+
+// Number of bits for the statemachine
+`undef PL230_STATE_BITS
+// Statemachine state encoding
+`undef PL230_ST_IDLE
+`undef PL230_ST_RD_CTRL
+`undef PL230_ST_RD_SPTR
+`undef PL230_ST_RD_DPTR
+`undef PL230_ST_RD_SDAT
+`undef PL230_ST_WR_DDAT
+`undef PL230_ST_WAIT
+`undef PL230_ST_WR_CTRL
+`undef PL230_ST_STALL
+`undef PL230_ST_DONE
+`undef PL230_ST_PSGP
+`undef PL230_ST_RESVD_0
+`undef PL230_ST_RESVD_1
+`undef PL230_ST_RESVD_2
+`undef PL230_ST_RESVD_3
+`undef PL230_ST_RESVD_4
+
+`undef PL230_SIZE_BYTE
+`undef PL230_SIZE_HWORD
+`undef PL230_SIZE_WORD
+`undef PL230_SIZE_RESVD
+
+// pl230_undefs.v end
diff --git a/system/src/nanosoc_exp.v b/system/src/nanosoc_exp.v
index 229f756..9558e5e 100644
--- a/system/src/nanosoc_exp.v
+++ b/system/src/nanosoc_exp.v
@@ -12,7 +12,7 @@
`include "cmsdk_ahb_slave_mux.v"
module nanosoc_exp #(
- parameter ADDRWIDTH=29, // Region Address Width
+ parameter ADDRWIDTH=29, // Region Address Width
parameter ACCEL_ADDRWIDTH=12 // Region Address Width
)(
input wire HCLK, // Clock
@@ -23,13 +23,17 @@ module nanosoc_exp #(
input wire [ADDRWIDTH-1:0] HADDRS,
input wire [1:0] HTRANSS,
input wire [2:0] HSIZES,
+ input wire [3:0] HPROTS,
input wire HWRITES,
input wire HREADYS,
input wire [31:0] HWDATAS,
output wire HREADYOUTS,
output wire HRESPS,
- output wire [31:0] HRDATAS
+ output wire [31:0] HRDATAS,
+
+ output wire ip_data_req,
+ output wire op_data_req
);
//********************************************************************************
@@ -127,23 +131,26 @@ cmsdk_ahb_slave_mux #(
//********************************************************************************
// Slave module 1: Accelerator AHB target module
//********************************************************************************
- wrapper_sha256_hashing_stream #(ACCEL_ADDRWIDTH
- ) accelerator (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
+ wrapper_sha256_secworks_sha256 #(ACCEL_ADDRWIDTH
+ ) u_accelerator (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
// Input target port: 32 bit data bus interface
- .HSELS (HSEL0),
- .HADDRS (HADDRS[ACCEL_ADDRWIDTH-1:0]),
- .HTRANSS (HTRANSS),
- .HSIZES (HSIZES),
- .HWRITES (HWRITES),
- .HREADYS (HREADYS),
- .HWDATAS (HWDATAS),
-
- .HREADYOUTS (HREADYOUT0),
- .HRESPS (HRESP0),
- .HRDATAS (HRDATA0)
+ .HSELS (HSEL0),
+ .HADDRS (HADDRS[ACCEL_ADDRWIDTH-1:0]),
+ .HTRANSS (HTRANSS),
+ .HSIZES (HSIZES),
+ .HPROTS (HPROTS),
+ .HWRITES (HWRITES),
+ .HREADYS (HREADYS),
+ .HWDATAS (HWDATAS),
+
+ .HREADYOUTS (HREADYOUT0),
+ .HRESPS (HRESP0),
+ .HRDATAS (HRDATA0),
+ .in_data_req (ip_data_req),
+ .out_data_req (op_data_req)
);
diff --git a/wrapper/src/wrapper_secworks_sha256.sv b/wrapper/src/wrapper_secworks_sha256.sv
index 70d5c7f..269fad9 100644
--- a/wrapper/src/wrapper_secworks_sha256.sv
+++ b/wrapper/src/wrapper_secworks_sha256.sv
@@ -24,6 +24,7 @@ module wrapper_secworks_sha256 #(
input logic [AHBADDRWIDTH-1:0] HADDRS,
input logic [1:0] HTRANSS,
input logic [2:0] HSIZES,
+ input logic [3:0] HPROTS,
input logic HWRITES,
input logic HREADYS,
input logic [31:0] HWDATAS,
@@ -33,10 +34,10 @@ module wrapper_secworks_sha256 #(
output logic [31:0] HRDATAS,
// Input Data Request Signal to DMAC
- output logic in_data_req,
+ output logic in_data_req,
// Output Data Request Signal to DMAC
- output logic out_data_req
+ output logic out_data_req
);
--
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