Update .gitlab-ci.yml file

.gitlab-ci.yml

@@ -19,7 +19,7 @@
 stages:          # List of stages for jobs, and their order of execution
   - simulate
   - build
-  #- deploy
+  - deploy
   
 variables:
   GIT_SUBMODULE_STRATEGY: normal
@@ -165,11 +165,11 @@ deploy-job-ZCU104:      # This job runs in the deploy stage.
     - screen -r zynq -X stuff "./ZCU104_connect.sh\n"
     - sleep 10
     # use scp to copy over bit files and python script
-    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/nanosoc/fpga_imp/CI_verification/load_bitfile.py ./ \n"
+    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/aes-128-project/nanosoc_tech/fpga/ci_tools/load_bitfile.py ./ \n"
     - sleep 2
-    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/nanosoc/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit ./pynq/overlays/soclabs/design_1.bit \n"
+    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/aes-128-project/imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit ./pynq/overlays/soclabs/design_1.bit \n"
     - sleep 2
-    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/nanosoc/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh ./pynq/overlays/soclabs/design_1.hwh \n"
+    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/aes-128-project/imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.hwh ./pynq/overlays/soclabs/design_1.hwh \n"
     - sleep 2
     # Need root access to load the overlay onto the FPGA
     - screen -r zynq -X stuff "sudo su\n"