Skip to content
Snippets Groups Projects
Commit a944a29a authored by dwn1c21's avatar dwn1c21
Browse files

Update .gitlab-ci.yml file

parent fb9474f0
Branches
No related tags found
1 merge request!1Changed set_env flow to source script in soctools and breadcrumb left in...
...@@ -17,30 +17,14 @@ ...@@ -17,30 +17,14 @@
# https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml # https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml
stages: # List of stages for jobs, and their order of execution stages: # List of stages for jobs, and their order of execution
- compile
- simulate - simulate
- build - build
- deploy #- deploy
variables: variables:
GIT_SUBMODULE_STRATEGY: normal GIT_SUBMODULE_STRATEGY: normal
GIT_SUBMODULE_FORCE_HTTPS: "true" GIT_SUBMODULE_FORCE_HTTPS: "true"
compile-bootrom:
stage: compile
script:
- source ./set_env.sh
- mkdir -p $SOCLABS_NANOSOC_TECH_DIR/system/src/bootrom
- cd $SOCLABS_NANOSOC_TECH_DIR
- make bootrom SIM_TOP_DIR=$SOCLABS_NANOSOC_TECH_DIR/sim BOOTROM_BUILD_DIR=$SOCLABS_NANOSOC_TECH_DIR/system/src/bootrom TOOL_CHAIN=ds5
artifacts:
paths:
- ./sim/bootloader/bootloader.hex
- ./nanosoc/testcodes/bootloader/bootloader.hex
- ./nanosoc/system/src/bootrom/verilog/bootrom.v
- ./nanosoc/system/src/bootrom/bintxt/bootrom.bintxt
tags:
- ds5
simulate-nanosoc: simulate-nanosoc:
stage: simulate stage: simulate
...@@ -55,10 +39,11 @@ build-job-Z2: # This job runs in the build stage, which runs first. ...@@ -55,10 +39,11 @@ build-job-Z2: # This job runs in the build stage, which runs first.
stage: build stage: build
script: script:
# move to fpga_imp directory and run the fpga build script for pynq z2 # move to fpga_imp directory and run the fpga build script for pynq z2
- cd .nanosoc_tech/fpga_imp/
- source ../set_env.sh - source ../set_env.sh
- if source ./build_fpga_pynq_z2.scr; then echo "Vivado Finished"; fi - git pull --recurse-submodules
- FILE=./pynq_export/pz2/pynq/overlays/soclabs/design_1.bit - cd ./nanosoc_tech/fpga/
- make build_fpga FPGA=z2
- FILE=../imp/fpga/output/pynq_z2/overlays/nanosoc_design.bit
- if test -f "$FILE"; then - if test -f "$FILE"; then
- echo "Build successful" - echo "Build successful"
- else - else
...@@ -68,8 +53,8 @@ build-job-Z2: # This job runs in the build stage, which runs first. ...@@ -68,8 +53,8 @@ build-job-Z2: # This job runs in the build stage, which runs first.
artifacts: artifacts:
paths: paths:
# Keep the generated bit and hwh file from fpga build script # Keep the generated bit and hwh file from fpga build script
- ./nanosoc_tech/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit - ./imp/fpga/output/pynq_z2/overlays/nanosoc_design.bit
- ./nanosoc_tech/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh - ./imp/fpga/output/pynq_z2/overlays/nanosoc_design.hwh
tags: tags:
- Vivado2021.1 - Vivado2021.1
...@@ -77,10 +62,11 @@ build-job-ZCU104: # This job runs in the build stage, which runs first. ...@@ -77,10 +62,11 @@ build-job-ZCU104: # This job runs in the build stage, which runs first.
stage: build stage: build
script: script:
# move to fpga_imp directory and run the fpga build script for pynq z2 # move to fpga_imp directory and run the fpga build script for pynq z2
- cd ./nanosoc_tech/fpga_imp/
- source ../../set_env.sh - source ../../set_env.sh
- if source ./build_fpga_pynq_zcu104.scr; then echo "Vivado Finished"; fi - git pull --recurse-submodules
- FILE=./pynq_export/pz104/pynq/overlays/soclabs/design_1.bit - cd ./nanosoc_tech/fpga
- make build_fpga FPGA=zcu104
- FILE=../imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit
- if test -f "$FILE"; then - if test -f "$FILE"; then
- echo "Build successful" - echo "Build successful"
- else - else
...@@ -90,8 +76,8 @@ build-job-ZCU104: # This job runs in the build stage, which runs first. ...@@ -90,8 +76,8 @@ build-job-ZCU104: # This job runs in the build stage, which runs first.
artifacts: artifacts:
paths: paths:
# Keep the generated bit and hwh file from fpga build script # Keep the generated bit and hwh file from fpga build script
- ./nanosoc_tech/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit - ./imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit
- ./nanosoc_tech/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh - ./imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.hwh
tags: tags:
- Vivado2021.1 - Vivado2021.1
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment