Update .gitlab-ci.yml file

.gitlab-ci.yml

@@ -17,30 +17,14 @@
 # https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml
 
 stages:          # List of stages for jobs, and their order of execution
-  - compile
   - simulate
   - build
-  - deploy
+  #- deploy
   
 variables:
   GIT_SUBMODULE_STRATEGY: normal
   GIT_SUBMODULE_FORCE_HTTPS: "true"
 
-compile-bootrom:
-  stage: compile
-  script:
-    - source ./set_env.sh
-    - mkdir -p $SOCLABS_NANOSOC_TECH_DIR/system/src/bootrom
-    - cd $SOCLABS_NANOSOC_TECH_DIR
-    - make bootrom SIM_TOP_DIR=$SOCLABS_NANOSOC_TECH_DIR/sim BOOTROM_BUILD_DIR=$SOCLABS_NANOSOC_TECH_DIR/system/src/bootrom TOOL_CHAIN=ds5
-  artifacts:
-    paths:
-      - ./sim/bootloader/bootloader.hex
-      - ./nanosoc/testcodes/bootloader/bootloader.hex
-      - ./nanosoc/system/src/bootrom/verilog/bootrom.v
-      - ./nanosoc/system/src/bootrom/bintxt/bootrom.bintxt
-  tags:
-    - ds5
 
 simulate-nanosoc:
   stage: simulate
@@ -55,10 +39,11 @@ build-job-Z2:       # This job runs in the build stage, which runs first.
   stage: build
   script:
     # move to fpga_imp directory and run the fpga build script for pynq z2
-    - cd .nanosoc_tech/fpga_imp/
     - source ../set_env.sh
-    - if source ./build_fpga_pynq_z2.scr; then echo "Vivado Finished"; fi
-    - FILE=./pynq_export/pz2/pynq/overlays/soclabs/design_1.bit 
+    - git pull --recurse-submodules
+    - cd ./nanosoc_tech/fpga/
+    - make build_fpga FPGA=z2
+    - FILE=../imp/fpga/output/pynq_z2/overlays/nanosoc_design.bit 
     - if test -f "$FILE"; then
     -   echo "Build successful"
     - else
@@ -68,8 +53,8 @@ build-job-Z2:       # This job runs in the build stage, which runs first.
   artifacts:
     paths:
       # Keep the generated bit and hwh file from fpga build script
-      - ./nanosoc_tech/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit
-      - ./nanosoc_tech/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh
+      - ./imp/fpga/output/pynq_z2/overlays/nanosoc_design.bit 
+      - ./imp/fpga/output/pynq_z2/overlays/nanosoc_design.hwh
   tags:
     - Vivado2021.1
 
@@ -77,10 +62,11 @@ build-job-ZCU104:       # This job runs in the build stage, which runs first.
   stage: build
   script:
    # move to fpga_imp directory and run the fpga build script for pynq z2 
-    - cd ./nanosoc_tech/fpga_imp/
     - source ../../set_env.sh
-    - if source ./build_fpga_pynq_zcu104.scr; then echo "Vivado Finished"; fi
-    - FILE=./pynq_export/pz104/pynq/overlays/soclabs/design_1.bit 
+    - git pull --recurse-submodules
+    - cd ./nanosoc_tech/fpga
+    - make build_fpga FPGA=zcu104
+    - FILE=../imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit 
     - if test -f "$FILE"; then
     -   echo "Build successful"
     - else
@@ -90,8 +76,8 @@ build-job-ZCU104:       # This job runs in the build stage, which runs first.
   artifacts:
     paths:
     # Keep the generated bit and hwh file from fpga build script
-      - ./nanosoc_tech/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit
-      - ./nanosoc_tech/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh
+      - ./imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit 
+      - ./imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.hwh 
   tags:
     - Vivado2021.1