Initial update for 65nm and 28nm flows and addition of Synopsys SLM

asic_lib_tech @ 28d17f2a

-Subproject commit ddda4a64c07b133b6d60c539ac403fb6644bb55f
+Subproject commit 28d17f2aa58ecf27e8168e8c5874457caaf29f4f

flist/project/top_ASIC.flist

@@ -34,5 +34,5 @@
 $(SOCLABS_PROJECT_DIR)/system/src/defines/gen_defines.v
 
 // the chosen DMA controller
--f $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb.flist
+//-f $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb.flist
 //-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist

nanosoc.config

@@ -28,4 +28,13 @@ DMA350_BIG :=
 ADC_0_INCLUDE:= 
 ADC_1_INCLUDE:= 
 ADC_2_INCLUDE:=
-ADC_3_INCLUDE:=
\ No newline at end of file
+ADC_3_INCLUDE:=
+
+SNPS_PVT_TS_0_INCLUDE:=
+SNPS_PVT_TS_1_INCLUDE:=
+SNPS_PVT_TS_2_INCLUDE:=
+SNPS_PVT_TS_3_INCLUDE:=
+SNPS_PVT_TS_4_INCLUDE:=
+SNPS_PVT_TS_5_INCLUDE:=
+SNPS_PVT_PD_0_INCLUDE:=
+SNPS_PVT_VM_0_INCLUDE:=
\ No newline at end of file

nanosoc_tech @ b48b1671

-Subproject commit 0aad87ad6fc7d93028fc5202388356d2b31afdf5
+Subproject commit b48b1671f3d0a80b93072878d9fce1856153bc55