Merge branch accelerator-project:main into main

.gitmodules

@@ -22,7 +22,3 @@
 	path = rtl_primitives_tech
 	url = https://git.soton.ac.uk/soclabs/rtl_primitives_tech.git
 	branch = main
-[submodule "secworks-aes"]
-	path = secworks-aes
-	url = https://github.com/secworks/aes.git
-	branch = master

README.md

@@ -30,6 +30,16 @@ Once you have run a `source set_env.sh` in your current terminal, you are then a
 
 This runs a git pull on all repositories in your project.
 
+# Project Structure
+
+The core of the SoC is NanoSoC. This is an example, configurable system that is the main framework. It has many different memory-mapped regions, one of which is designed for the connection of accelerator subsystems called the expansion region.
+
+The expansion region is able to instantiate an accelerator_subsystem by default. This means that anyone using NanoSoC as a platform for accelerator experimentation will need to build an `accelerator_subsystem` rtl module.
+
+`accelerator_subsystem` can either directly contain an accelerator (or multiple) or can instantiate accelerator wrappers which in turn instantiate accelerators.
+
+This module is expected to be found in `system/src/accelerator_subsystem.v`.
+
 ## Running the simulation
 
 This design instantiates a custom (AMBA-AHB) wrapper around the AES core to implement a memory-mapped 128-bit AES encrypt/decrypt accelerator that can be used as a software-driven peripheral or a semi-autonomous DMA subystem when 128-bit keys and variable length data payloads can be set up as scatter/gather descriptor chains for background processing.

env/dependency_env.sh

@@ -15,7 +15,7 @@
 #-----------------------------------------------------------------------------
 
 # Accelerator Engine -- Add Your Accelerator Environment Variable HERE!
-export ACCELERATOR_DIR="$SOCLABS_PROJECT_DIR/secworks-aes"
+#export ACCELERATOR_DIR="$SOCLABS_PROJECT_DIR/youraccelerator"
 
 # Accelerator Wrapper
 export SOCLABS_WRAPPER_TECH_DIR="$SOCLABS_PROJECT_DIR/accelerator_wrapper_tech"

flist/project/accelerator.flist

@@ -14,10 +14,10 @@
 // =============    Accelerator Module search path    =============
 
 // ! Point this to your Accelerator RTL
-+incdir+$(ACCELERATOR_DIR)/src/rtl
+//+incdir+$(ACCELERATOR_DIR)/src/rtl
 
 // ! Point this to your Wrapper RTL
-$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
+//$(SOCLABS_PROJECT_DIR)/wrapper/src/your_wrapper.v
 
 // ! Point this to your Subsystem RTL
-$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
\ No newline at end of file
+//$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
\ No newline at end of file

projbranch

@@ -11,7 +11,6 @@
 # Each Repo needs to have its branch set manually in here - they will defaultly be checked out to main
 # Project Repository Subrepository Branch Index
 # Add your Accelerator Repository here
-secworks-aes: master
 
 nanosoc_tech: main
 accelerator_wrapper_tech: main

secworks-aes @ b9a3f196

-Subproject commit b9a3f1965b4e0568f0ca9b2d575ce6ea6fec2f36

system/src/accelerator_subsystem.v

-//-----------------------------------------------------------------------------
-// SoC Labs Accelerator Subsystem for SecWorks AES-128 Accelerator
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-// David Flynn    (d.w.flynn@soton.ac.uk)
-//
-// Copyright (C) 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module accelerator_subsystem #(
-  parameter SYS_ADDR_W = 32,
-  parameter SYS_DATA_W = 32,
-  parameter ACC_ADDR_W = 16,
-  parameter IRQ_NUM    = 4
-) (
-  input  wire                      HCLK,       // Clock
-  input  wire                      HRESETn,    // Reset
-
-  // AHB connection to Initiator
-  input  wire                      HSEL,
-  input  wire   [SYS_ADDR_W-1:0]   HADDR,
-  input  wire   [1:0]              HTRANS,
-  input  wire   [2:0]              HSIZE,
-  input  wire   [3:0]              HPROT,
-  input  wire                      HWRITE,
-  input  wire                      HREADY,
-  input  wire   [SYS_DATA_W-1:0]   HWDATA,
-
-  output wire                      HREADYOUT,
-  output wire                      HRESP,
-  output wire   [SYS_DATA_W-1:0]   HRDATA,
-
-  // Data Request Signal to DMAC
-  output wire   [1:0]              EXP_DRQ,
-  input  wire   [1:0]              EXP_DLAST,
-  
-  // Interrupts
-  output wire   [IRQ_NUM-1:0]      EXP_IRQ
-);
-  
-  //--------------------------------------
-  // AES Accelerator Wrapper
-  //--------------------------------------
-  soclabs_ahb_aes128_ctrl u_exp_aes128 (
-    .ahb_hclk        (HCLK),
-    .ahb_hresetn     (HRESETn),
-    .ahb_hsel        (HSEL),
-    .ahb_haddr16     (HADDR[ACC_ADDR_W-1:0]),
-    .ahb_htrans      (HTRANS),
-    .ahb_hwrite      (HWRITE),
-    .ahb_hsize       (HSIZE),
-    .ahb_hprot       (HPROT),
-    .ahb_hwdata      (HWDATA),
-    .ahb_hready      (HREADY),
-    .ahb_hrdata      (HRDATA),
-    .ahb_hreadyout   (HREADYOUT),
-    .ahb_hresp       (HRESP),
-    .drq_ipdma128    (EXP_DRQ[0]),
-    .dlast_ipdma128  (EXP_DLAST[0]),
-    .drq_opdma128    (EXP_DRQ[1]),
-    .dlast_opdma128  (EXP_DLAST[1]),
-    .irq_key128      (EXP_IRQ[0]),
-    .irq_ip128       (EXP_IRQ[1]),
-    .irq_op128       (EXP_IRQ[2]),
-    .irq_error       (EXP_IRQ[3]),
-    .irq_merged      ( )
-  );
-
-endmodule