Update ASIC flow

flist/project/system_ASIC.flist

+//-----------------------------------------------------------------------------
+// Accelerator System Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Top-level Accelerator System
+//-----------------------------------------------------------------------------
+
+// =============    Accelerator Module search path    =============
+// ! Point this to your accelerator subsystem filelist
+
+// =============    System Component Filelist      ================
+// - Custom Accelerator Filelist
+-f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist
+
+// - Primitives IP
+-f $(SOCLABS_PRIMITIVES_TECH_DIR)/flist/rtl_primitives_ip.flist
+
+// - Generic Pad Library
+-f $(SOCLABS_GENERIC_LIB_TECH_DIR)/flist/generic_lib_ip.flist
+
+// - FPGA sram
+-f $(SOCLABS_ASIC_LIB_TECH_DIR)/flist/asic_lib_mem_ip.flist
+
+// - Accelerator Wrapper IP
+-f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
+
+// - Bootrom Code RTL
+$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file

flist/project/top_ASIC.flist

@@ -21,7 +21,7 @@
 // - Defines RTL
 +incdir+$(SOCLABS_PROJECT_DIR)/system/src/defines
 
--f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/project/system_ASIC.flist
 
 // =============    Arm-IP Specific Filelists      =========================
 // - NanoSoC Chip IP

nanosoc_tech @ 714bca67

-Subproject commit 4dbe52d4b0b282a788bc79b5b9954db8aae0b184
+Subproject commit 714bca67dcb1c6442d123dc48ad97c5d832c9c83