From 81e11c0325133222390eaba34f13d6dc0952abfd Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Wed, 19 Jul 2023 13:29:58 +0100
Subject: [PATCH] Update ASIC flow

---
 flist/project/system_ASIC.flist | 35 +++++++++++++++++++++++++++++++++
 flist/project/top_ASIC.flist    |  2 +-
 nanosoc_tech                    |  2 +-
 3 files changed, 37 insertions(+), 2 deletions(-)
 create mode 100644 flist/project/system_ASIC.flist

diff --git a/flist/project/system_ASIC.flist b/flist/project/system_ASIC.flist
new file mode 100644
index 0000000..ccfe21c
--- /dev/null
+++ b/flist/project/system_ASIC.flist
@@ -0,0 +1,35 @@
+//-----------------------------------------------------------------------------
+// Accelerator System Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Top-level Accelerator System
+//-----------------------------------------------------------------------------
+
+// =============    Accelerator Module search path    =============
+// ! Point this to your accelerator subsystem filelist
+
+// =============    System Component Filelist      ================
+// - Custom Accelerator Filelist
+-f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist
+
+// - Primitives IP
+-f $(SOCLABS_PRIMITIVES_TECH_DIR)/flist/rtl_primitives_ip.flist
+
+// - Generic Pad Library
+-f $(SOCLABS_GENERIC_LIB_TECH_DIR)/flist/generic_lib_ip.flist
+
+// - FPGA sram
+-f $(SOCLABS_ASIC_LIB_TECH_DIR)/flist/asic_lib_mem_ip.flist
+
+// - Accelerator Wrapper IP
+-f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
+
+// - Bootrom Code RTL
+$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file
diff --git a/flist/project/top_ASIC.flist b/flist/project/top_ASIC.flist
index 75a4489..b39d667 100644
--- a/flist/project/top_ASIC.flist
+++ b/flist/project/top_ASIC.flist
@@ -21,7 +21,7 @@
 // - Defines RTL
 +incdir+$(SOCLABS_PROJECT_DIR)/system/src/defines
 
--f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/project/system_ASIC.flist
 
 // =============    Arm-IP Specific Filelists      =========================
 // - NanoSoC Chip IP
diff --git a/nanosoc_tech b/nanosoc_tech
index 4dbe52d..714bca6 160000
--- a/nanosoc_tech
+++ b/nanosoc_tech
@@ -1 +1 @@
-Subproject commit 4dbe52d4b0b282a788bc79b5b9954db8aae0b184
+Subproject commit 714bca67dcb1c6442d123dc48ad97c5d832c9c83
-- 
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