Redistrubuting filelists

accelerator_wrapper_tech @ 0748aa7d

-Subproject commit 33b0a1afab0d8d3279e9f6156a18d7b4954f9f5f
+Subproject commit 0748aa7d6c1186bf8195557eef230a95d2a7c53c

flist/primitives/primitives.flist

-//-----------------------------------------------------------------------------
-// Primitives Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for RTL Primitives
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// =============    RTL Primitives search path    =============
-$(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/fifo_vr.sv

flist/project/accelerator.flist

 //-----------------------------------------------------------------------------
-// Accelerator Filelist
+// Accelerator Subsystem Filelist
 //-----------------------------------------------------------------------------
 //-----------------------------------------------------------------------------
 // Abstract : This file contains a list of files and directories related to
-//            your accelerator.
+//            your accelerator. PLEASE MODIFY!!!
 //-----------------------------------------------------------------------------
 
-// DESIGN_TOP accelerator
+// DESIGN_TOP accelerator_subsystem
 
 // ============= Verilog library extensions ===========
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
+
+// ! Point this to your Accelerator RTL
 +incdir+$(ACCELERATOR_DIR)/src/rtl
-$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
-$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
+
+// ! Point this to your Wrapper RTL
\ No newline at end of file
+$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
+
+// ! Point this to your Subsystem RTL
+$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
\ No newline at end of file

flist/project/system.flist

@@ -13,16 +13,14 @@
 //-----------------------------------------------------------------------------
 
 // =============    Accelerator Module search path    =============
-// ! Point this to your accelerator filelist
--f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist
-
-// =============    Wrapper Filelist      =========================
--f $(SOCLABS_PROJECT_DIR)/flist/project/wrapper.flist
+// ! Point this to your accelerator subsystem filelist
 
 // =============    System Component Filelist      ================
+// - Custom Accelerator Filelist
+-f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist
 
 // - Primitives IP
--f $(SOCLABS_PROJECT_DIR)/flist/primitives/primitives.flist
+-f $(SOCLABS_PRIMITIVES_TECH_DIR)/flist/rtl_primitives_ip.flist
 
 // - Generic Pad Library
 -f $(SOCLABS_PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist
@@ -30,5 +28,8 @@
 // - FPGA sram
 -f $(SOCLABS_PROJECT_DIR)/flist/mem/fpga_mem.flist
 
-// =============    Bootrom Filelist      ================
+// - Accelerator Wrapper IP
+-f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
+
+// - Bootrom Code RTL
 $(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file

flist/project/wrapper.flist

-//-----------------------------------------------------------------------------
-// Accelerator Wrapper Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Top-level Accelerator Wrapper
-//-----------------------------------------------------------------------------
-
-// DESIGN_TOP your_wrapper
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// =============    Wrapper IP Filelist    ========================
--f $(SOCLABS_PROJECT_DIR)/flist/wrapper/wrapper_ip.flist
-
-// =============    Accelerator Module search path    =============
-
-// Add the source files related to your custom wrapper
-// $(SOCLABS_PROJECT_DIR)/wrapper/src/your_wrapper.v

flist/wrapper/wrapper_ip.flist

-//-----------------------------------------------------------------------------
-// Accelerator Wrapper Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Accelerator Wrapper IP
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// =============    Accelerator Module search path    =============
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_constructor.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_deconstructor.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_addr_calc.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_data_req.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_construct.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_deconstruct.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_req_ctrl_reg.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_dmac_req.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_valid_filter.sv

rtl_primitives_tech @ a2e3f406

-Subproject commit ce27da6f556a7dd20bcce213278e6f29b8d66332
+Subproject commit a2e3f406afbdfb4a7a38438e2356c16a8756158e

simulate/socsim/wrapper_secworks_sha256.sh

@@ -24,7 +24,7 @@ xrun \
     -sv \
     -timescale 1ps/1ps \
     +access+r \
-    -f $SOCLABS_PROJECT_DIR/flist/primatives.flist \
+    -f $SOCLABS_PRIMITIVES_TECH_DIR/flist/primatives.flist \
     -f $SOCLABS_PROJECT_DIR/flist/wrapper_ip.flist \
     -f $SOCLABS_PROJECT_DIR/flist/ahb_ip.flist \
     -f $SOCLABS_PROJECT_DIR/flist/apb_ip.flist \