From 63b05b0a4c65b96c2fc6eeb12883f86eb225fb00 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Fri, 30 Jun 2023 10:58:52 +0100
Subject: [PATCH] Redistrubuting filelists
---
accelerator_wrapper_tech | 2 +-
flist/primitives/primitives.flist | 19 ---------------
flist/project/accelerator.flist | 16 +++++++++----
flist/project/system.flist | 15 ++++++------
flist/project/wrapper.flist | 26 --------------------
flist/wrapper/wrapper_ip.flist | 28 ----------------------
rtl_primitives_tech | 2 +-
simulate/socsim/wrapper_secworks_sha256.sh | 2 +-
8 files changed, 22 insertions(+), 88 deletions(-)
delete mode 100644 flist/primitives/primitives.flist
delete mode 100644 flist/project/wrapper.flist
delete mode 100644 flist/wrapper/wrapper_ip.flist
diff --git a/accelerator_wrapper_tech b/accelerator_wrapper_tech
index 33b0a1a..0748aa7 160000
--- a/accelerator_wrapper_tech
+++ b/accelerator_wrapper_tech
@@ -1 +1 @@
-Subproject commit 33b0a1afab0d8d3279e9f6156a18d7b4954f9f5f
+Subproject commit 0748aa7d6c1186bf8195557eef230a95d2a7c53c
diff --git a/flist/primitives/primitives.flist b/flist/primitives/primitives.flist
deleted file mode 100644
index 30a7272..0000000
--- a/flist/primitives/primitives.flist
+++ /dev/null
@@ -1,19 +0,0 @@
-//-----------------------------------------------------------------------------
-// Primitives Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for RTL Primitives
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= RTL Primitives search path =============
-$(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/fifo_vr.sv
diff --git a/flist/project/accelerator.flist b/flist/project/accelerator.flist
index 1b868a8..2bf1f3c 100644
--- a/flist/project/accelerator.flist
+++ b/flist/project/accelerator.flist
@@ -1,17 +1,23 @@
//-----------------------------------------------------------------------------
-// Accelerator Filelist
+// Accelerator Subsystem Filelist
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : This file contains a list of files and directories related to
-// your accelerator.
+// your accelerator. PLEASE MODIFY!!!
//-----------------------------------------------------------------------------
-// DESIGN_TOP accelerator
+// DESIGN_TOP accelerator_subsystem
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= Accelerator Module search path =============
+
+// ! Point this to your Accelerator RTL
+incdir+$(ACCELERATOR_DIR)/src/rtl
-$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
-$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
\ No newline at end of file
+
+// ! Point this to your Wrapper RTL
+$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
+
+// ! Point this to your Subsystem RTL
+$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
\ No newline at end of file
diff --git a/flist/project/system.flist b/flist/project/system.flist
index 325f00f..92465d1 100644
--- a/flist/project/system.flist
+++ b/flist/project/system.flist
@@ -13,16 +13,14 @@
//-----------------------------------------------------------------------------
// ============= Accelerator Module search path =============
-// ! Point this to your accelerator filelist
--f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist
-
-// ============= Wrapper Filelist =========================
--f $(SOCLABS_PROJECT_DIR)/flist/project/wrapper.flist
+// ! Point this to your accelerator subsystem filelist
// ============= System Component Filelist ================
+// - Custom Accelerator Filelist
+-f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist
// - Primitives IP
--f $(SOCLABS_PROJECT_DIR)/flist/primitives/primitives.flist
+-f $(SOCLABS_PRIMITIVES_TECH_DIR)/flist/rtl_primitives_ip.flist
// - Generic Pad Library
-f $(SOCLABS_PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist
@@ -30,5 +28,8 @@
// - FPGA sram
-f $(SOCLABS_PROJECT_DIR)/flist/mem/fpga_mem.flist
-// ============= Bootrom Filelist ================
+// - Accelerator Wrapper IP
+-f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
+
+// - Bootrom Code RTL
$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file
diff --git a/flist/project/wrapper.flist b/flist/project/wrapper.flist
deleted file mode 100644
index 0c715b2..0000000
--- a/flist/project/wrapper.flist
+++ /dev/null
@@ -1,26 +0,0 @@
-//-----------------------------------------------------------------------------
-// Accelerator Wrapper Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Top-level Accelerator Wrapper
-//-----------------------------------------------------------------------------
-
-// DESIGN_TOP your_wrapper
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= Wrapper IP Filelist ========================
--f $(SOCLABS_PROJECT_DIR)/flist/wrapper/wrapper_ip.flist
-
-// ============= Accelerator Module search path =============
-
-// Add the source files related to your custom wrapper
-// $(SOCLABS_PROJECT_DIR)/wrapper/src/your_wrapper.v
diff --git a/flist/wrapper/wrapper_ip.flist b/flist/wrapper/wrapper_ip.flist
deleted file mode 100644
index f41d660..0000000
--- a/flist/wrapper/wrapper_ip.flist
+++ /dev/null
@@ -1,28 +0,0 @@
-//-----------------------------------------------------------------------------
-// Accelerator Wrapper Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Accelerator Wrapper IP
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= Accelerator Module search path =============
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_constructor.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_deconstructor.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_addr_calc.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_data_req.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_construct.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_deconstruct.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_req_ctrl_reg.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_dmac_req.sv
-$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_valid_filter.sv
diff --git a/rtl_primitives_tech b/rtl_primitives_tech
index ce27da6..a2e3f40 160000
--- a/rtl_primitives_tech
+++ b/rtl_primitives_tech
@@ -1 +1 @@
-Subproject commit ce27da6f556a7dd20bcce213278e6f29b8d66332
+Subproject commit a2e3f406afbdfb4a7a38438e2356c16a8756158e
diff --git a/simulate/socsim/wrapper_secworks_sha256.sh b/simulate/socsim/wrapper_secworks_sha256.sh
index 2ac6f86..47ddc17 100755
--- a/simulate/socsim/wrapper_secworks_sha256.sh
+++ b/simulate/socsim/wrapper_secworks_sha256.sh
@@ -24,7 +24,7 @@ xrun \
-sv \
-timescale 1ps/1ps \
+access+r \
- -f $SOCLABS_PROJECT_DIR/flist/primatives.flist \
+ -f $SOCLABS_PRIMITIVES_TECH_DIR/flist/primatives.flist \
-f $SOCLABS_PROJECT_DIR/flist/wrapper_ip.flist \
-f $SOCLABS_PROJECT_DIR/flist/ahb_ip.flist \
-f $SOCLABS_PROJECT_DIR/flist/apb_ip.flist \
--
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