Updated filelist to point to nanosoc filelists

env/dependency_env.sh

@@ -23,6 +23,12 @@ export SOCLABS_WRAPPER_TECH_DIR="$SOCLABS_PROJECT_DIR/accelerator_wrapper_tech"
 # NanoSoC
 export SOCLABS_NANOSOC_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech"
 
+# SoCDebug
+export SOCLABS_SOCDEBUG_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech/system/socdebug_tech"
+
+# SLCore M0
+export SOCLABS_SLCOREM0_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech/system/slcore_m0_tech"
+
 # Primtives
 export SOCLABS_PRIMITIVES_TECH_DIR="$SOCLABS_PROJECT_DIR/rtl_primitives_tech"
 

flist/mem/fpga_mem.flist

+//-----------------------------------------------------------------------------
+// FPGA Memory Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Testbench
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    NanoSoC Testbench search path    =============
++incdir+$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/
+
+// - Top-level testbench
+$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v
\ No newline at end of file

flist/nanosoc/nanosoc_tb.flist

@@ -16,18 +16,19 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Testbench search path    =============
-+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/
++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/
 
 // - Top-level testbench
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_tb.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_tb.v
 
 // - Testbench components
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_clkreset.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_uart_capture.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_clkreset.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_uart_capture.v
 
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_track_tb_iostream.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_track.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
\ No newline at end of file
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_track_tb_iostream.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_ft1248x1_track.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_dma_log_to_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_acc_log_to_file.v
\ No newline at end of file

flist/nanosoc/nanosoc_test_io_ip.flist

@@ -16,6 +16,6 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Chip Test Interface IP Filelists   =============
-$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_adp_control_v1_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_adp_manager.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v
\ No newline at end of file
+$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/socket/verilog/axi_stream_io_v1_0_axi_s.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/socket/verilog/axi_stream_io_v1_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/socket/verilog/ft232h_ft1248_x1.v
\ No newline at end of file

flist/project/system.flist

@@ -34,10 +34,7 @@
 -f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip.flist
 
 // - NanoSoC Chip IP
--f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_chip_ip.flist
-
-// - NanoSoC Bus Matrix
--f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_matrix_ip.flist
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc.flist
 
 // - NanoSoc Test Interface IP
 -f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_test_io_ip.flist
@@ -63,5 +60,8 @@ $(SOCLABS_PROJECT_DIR)/system/src/nanosoc_exp.v
 // - Top level
 -f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist
 
+// - FPGA sram
+-f $(SOCLABS_PROJECT_DIR)/flist/mem/fpga_mem.flist
+
 // =============    Bootrom Filelist      ================
 $(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file

fpga_lib_tech @ 3e6eea8f

-Subproject commit c51fa197a1d89ed556653fd7743c4aba20383b39
+Subproject commit 3e6eea8f70104378841ddb7032399cebcf43686f

nanosoc_tech @ be8c5137

-Subproject commit 91ce5d7d85e099cdaf3194a97795c439c27fdd1c
+Subproject commit be8c5137ae9d04a798e6d6bdfa42b522397a1457