From 5a14961b582571ce86f579da71ccc57ae393284c Mon Sep 17 00:00:00 2001 From: dam1n19 <dam1n19@soton.ac.uk> Date: Thu, 22 Jun 2023 09:16:13 +0100 Subject: [PATCH] Updated filelist to point to nanosoc filelists --- env/dependency_env.sh | 6 ++++++ flist/mem/fpga_mem.flist | 22 ++++++++++++++++++++++ flist/nanosoc/nanosoc_tb.flist | 21 +++++++++++---------- flist/nanosoc/nanosoc_test_io_ip.flist | 6 +++--- flist/project/system.flist | 8 ++++---- fpga_lib_tech | 2 +- nanosoc_tech | 2 +- 7 files changed, 48 insertions(+), 19 deletions(-) create mode 100644 flist/mem/fpga_mem.flist diff --git a/env/dependency_env.sh b/env/dependency_env.sh index f76f37f..0b274cd 100755 --- a/env/dependency_env.sh +++ b/env/dependency_env.sh @@ -23,6 +23,12 @@ export SOCLABS_WRAPPER_TECH_DIR="$SOCLABS_PROJECT_DIR/accelerator_wrapper_tech" # NanoSoC export SOCLABS_NANOSOC_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech" +# SoCDebug +export SOCLABS_SOCDEBUG_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech/system/socdebug_tech" + +# SLCore M0 +export SOCLABS_SLCOREM0_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech/system/slcore_m0_tech" + # Primtives export SOCLABS_PRIMITIVES_TECH_DIR="$SOCLABS_PROJECT_DIR/rtl_primitives_tech" diff --git a/flist/mem/fpga_mem.flist b/flist/mem/fpga_mem.flist new file mode 100644 index 0000000..2df4506 --- /dev/null +++ b/flist/mem/fpga_mem.flist @@ -0,0 +1,22 @@ +//----------------------------------------------------------------------------- +// FPGA Memory Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for NanoSoC Testbench +//----------------------------------------------------------------------------- + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= NanoSoC Testbench search path ============= ++incdir+$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/ + +// - Top-level testbench +$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v \ No newline at end of file diff --git a/flist/nanosoc/nanosoc_tb.flist b/flist/nanosoc/nanosoc_tb.flist index 893b1b2..4c7b31c 100644 --- a/flist/nanosoc/nanosoc_tb.flist +++ b/flist/nanosoc/nanosoc_tb.flist @@ -16,18 +16,19 @@ +libext+.v+.vlib // ============= NanoSoC Testbench search path ============= -+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/ ++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/ // - Top-level testbench -$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_tb.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_tb.v // - Testbench components -$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_clkreset.v -$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_uart_capture.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_clkreset.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_uart_capture.v -$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v -$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v -$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v -$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_track_tb_iostream.v -$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_track.v -$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v \ No newline at end of file +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_track_tb_iostream.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_ft1248x1_track.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_dma_log_to_file.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_acc_log_to_file.v \ No newline at end of file diff --git a/flist/nanosoc/nanosoc_test_io_ip.flist b/flist/nanosoc/nanosoc_test_io_ip.flist index 5df3c3d..8cf68ee 100644 --- a/flist/nanosoc/nanosoc_test_io_ip.flist +++ b/flist/nanosoc/nanosoc_test_io_ip.flist @@ -16,6 +16,6 @@ +libext+.v+.vlib // ============= NanoSoC Chip Test Interface IP Filelists ============= -$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_adp_control_v1_0.v -$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_adp_manager.v -$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v \ No newline at end of file +$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/socket/verilog/axi_stream_io_v1_0_axi_s.v +$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/socket/verilog/axi_stream_io_v1_0.v +$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/socket/verilog/ft232h_ft1248_x1.v \ No newline at end of file diff --git a/flist/project/system.flist b/flist/project/system.flist index 2262842..ec9d812 100644 --- a/flist/project/system.flist +++ b/flist/project/system.flist @@ -34,10 +34,7 @@ -f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip.flist // - NanoSoC Chip IP --f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_chip_ip.flist - -// - NanoSoC Bus Matrix --f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_matrix_ip.flist +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc.flist // - NanoSoc Test Interface IP -f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_test_io_ip.flist @@ -63,5 +60,8 @@ $(SOCLABS_PROJECT_DIR)/system/src/nanosoc_exp.v // - Top level -f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist +// - FPGA sram +-f $(SOCLABS_PROJECT_DIR)/flist/mem/fpga_mem.flist + // ============= Bootrom Filelist ================ $(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v \ No newline at end of file diff --git a/fpga_lib_tech b/fpga_lib_tech index c51fa19..3e6eea8 160000 --- a/fpga_lib_tech +++ b/fpga_lib_tech @@ -1 +1 @@ -Subproject commit c51fa197a1d89ed556653fd7743c4aba20383b39 +Subproject commit 3e6eea8f70104378841ddb7032399cebcf43686f diff --git a/nanosoc_tech b/nanosoc_tech index 91ce5d7..be8c513 160000 --- a/nanosoc_tech +++ b/nanosoc_tech @@ -1 +1 @@ -Subproject commit 91ce5d7d85e099cdaf3194a97795c439c27fdd1c +Subproject commit be8c5137ae9d04a798e6d6bdfa42b522397a1457 -- GitLab