Updated filelists to support quickstart

flist/ahb/ahb_ip.flist

@@ -17,7 +17,7 @@
 
 // =============    Accelerator Module search path    =============
 // CMSDK AHB Slave Mux IP
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v
 
 // CMSDK AHB Default Slave IP
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
\ No newline at end of file
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
\ No newline at end of file

flist/ahb/ahb_ip_qs.flist

+//-----------------------------------------------------------------------------
+// Accelerator Wrapper CMSDK Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Accelerator CMSDK AHB IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    Accelerator Module search path    =============
+// CMSDK AHB Slave Mux IP
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v
+
+// CMSDK AHB Default Slave IP
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
\ No newline at end of file

flist/ahb/ahb_vip.flist

@@ -16,7 +16,7 @@
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_filereadcore.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_funnel.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master32.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master64.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_filereadcore.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_funnel.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master32.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master64.v

flist/ahb/ahb_vip_qs.flist

+//-----------------------------------------------------------------------------
+// Accelerator Wrapper CMSDK Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Accelerator CMSDK AHB VIP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    Accelerator Module search path    =============
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_filereadcore.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_funnel.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master32.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master64.v

flist/apb/apb_ip.flist

@@ -16,7 +16,7 @@
 +libext+.v+.vlib
 
 // =============    CMSDK APB IP search path    =============
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave.v

flist/apb/apb_ip_qs.flist

+//-----------------------------------------------------------------------------
+// CMSDK APB IP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Accelerator CMSDK AHB IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    CMSDK APB IP search path    =============
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave.v

flist/mem/fpga_mem.flist

@@ -16,7 +16,7 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Testbench search path    =============
-// -incdir $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/
+// +incdir+$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/
 
 // - Top-level testbench
 $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v
\ No newline at end of file

flist/nanosoc/nanosoc_tb.flist

@@ -16,7 +16,7 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Testbench search path    =============
--incdir $(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/
++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/
 
 // - Top-level testbench
 $(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_tb.v

flist/nanosoc/nanosoc_tb_qs.flist

+//-----------------------------------------------------------------------------
+// NanoSoC Testbench Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Testbench
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    NanoSoC Testbench search path    =============
++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/
+
+// - Top-level testbench
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_tb_qs.v
+
+// - Testbench components
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_clkreset.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_uart_capture.v
+
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_track_tb_iostream.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_ft1248x1_track.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_dma_log_to_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_acc_log_to_file.v
\ No newline at end of file

flist/project/system.flist

@@ -12,11 +12,6 @@
 // Abstract : Verilog Command File for Top-level Accelerator System
 //-----------------------------------------------------------------------------
 
-// DESIGN_TOP nanosoc_chip
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
 // =============    Accelerator Module search path    =============
 // ! Point this to your accelerator filelist
 // -f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist
@@ -29,13 +24,6 @@
 // - Primitives IP
 -f $(SOCLABS_PROJECT_DIR)/flist/primitives/primitives.flist
 
-// - CMSDK IP
--f $(SOCLABS_PROJECT_DIR)/flist/ahb/ahb_ip.flist
--f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip.flist
-
-// - NanoSoC Chip IP
--f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_ip.flist
-
 // - NanoSoc Test Interface IP
 -f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_test_io_ip.flist
 

flist/project/system_tb.flist → flist/project/top.flist

 //-----------------------------------------------------------------------------
-// Accelerator System Filelist
+// Project Top-level Filelist System Filelist
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
@@ -12,19 +12,22 @@
 // Abstract : Verilog Command File for Top-level Accelerator System
 //-----------------------------------------------------------------------------
 
-// DESIGN_TOP nanosoc_tb
+// DESIGN_TOP nanosoc_chip
 
 // ============= Verilog library extensions ===========
 +libext+.v+.vlib
 
-// =============    System Component Filelist      ================
-
-// - CMSDK VIP
--f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist
-
-// - Design
+// =============    System Filelist      =========================
 -f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist
 
-// - Top level
+// Testbench
 -f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist
+
+// =============    Arm-IP Specific Filelists      =========================
+// - NanoSoC Chip IP
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc.flist
 
+// - CMSDK IP
+-f $(SOCLABS_PROJECT_DIR)/flist/ahb/ahb_ip.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip.flist
\ No newline at end of file

flist/project/top_qs.flist

+//-----------------------------------------------------------------------------
+// Project Top-level Filelist System Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Top-level Accelerator System
+//-----------------------------------------------------------------------------
+
+// DESIGN_TOP nanosoc_chip
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    System Filelist      =========================
+-f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist
+
+// Testbench
+-f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb_qs.flist
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip_qs.flist
+
+// =============    Arm-IP Specific Filelists      =========================
+// - NanoSoC Chip IP
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_qs.flist
+
+// - CMSDK IP
+-f $(SOCLABS_PROJECT_DIR)/flist/ahb/ahb_ip_qs.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip_qs.flist
\ No newline at end of file

nanosoc_tech @ a2e3324d

-Subproject commit 2b8513fb3346d193280916fb5eb11db90c7dfce9
+Subproject commit a2e3324d42d4cad8725c3ea746119cccc094dbcf

proj-branch

@@ -13,6 +13,9 @@
 # Add your Accelerator Repository here
 # accelerator_repo: main
 nanosoc_tech: feat_nanosoc_regions
+slcorem0_tech: main
+sldma230_tech: main
+socdebug_tech: main
 accelerator_wrapper_tech: main
 fpga_lib_tech: main
 generic_lib_tech: main

soctools_flow @ 74d6c1bb

-Subproject commit 1c706759aebfbd539a9f035e94737975e00dd5dd
+Subproject commit 74d6c1bb134143547eedccefb6393f3759f13fae