diff --git a/flist/ahb/ahb_ip.flist b/flist/ahb/ahb_ip.flist index 99ae333bcb7ad585a6cb6bb85aaee8bd416b3336..25495b56bbab3fba6304e6bd5aec6f1b17822815 100644 --- a/flist/ahb/ahb_ip.flist +++ b/flist/ahb/ahb_ip.flist @@ -17,7 +17,7 @@ // ============= Accelerator Module search path ============= // CMSDK AHB Slave Mux IP -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v +//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v // CMSDK AHB Default Slave IP -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v \ No newline at end of file +//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v \ No newline at end of file diff --git a/flist/ahb/ahb_ip_qs.flist b/flist/ahb/ahb_ip_qs.flist new file mode 100644 index 0000000000000000000000000000000000000000..086b01d88eb25b4fff13804474bc0ce8dbbe10ef --- /dev/null +++ b/flist/ahb/ahb_ip_qs.flist @@ -0,0 +1,23 @@ +//----------------------------------------------------------------------------- +// Accelerator Wrapper CMSDK Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for Accelerator CMSDK AHB IP +//----------------------------------------------------------------------------- + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= Accelerator Module search path ============= +// CMSDK AHB Slave Mux IP +//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v + +// CMSDK AHB Default Slave IP +//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v \ No newline at end of file diff --git a/flist/ahb/ahb_vip.flist b/flist/ahb/ahb_vip.flist index 0dc7b6755241f38442386dcae2230b931f1e50f9..162f68d5fd167523de2b5fad580e43ead87516f1 100644 --- a/flist/ahb/ahb_vip.flist +++ b/flist/ahb/ahb_vip.flist @@ -16,7 +16,7 @@ +libext+.v+.vlib // ============= Accelerator Module search path ============= -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_filereadcore.v -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_funnel.v -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master32.v -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master64.v +//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_filereadcore.v +//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_funnel.v +//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master32.v +//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master64.v diff --git a/flist/ahb/ahb_vip_qs.flist b/flist/ahb/ahb_vip_qs.flist new file mode 100644 index 0000000000000000000000000000000000000000..1789500ab765a93dc220bc974b73b8b44b46f093 --- /dev/null +++ b/flist/ahb/ahb_vip_qs.flist @@ -0,0 +1,22 @@ +//----------------------------------------------------------------------------- +// Accelerator Wrapper CMSDK Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for Accelerator CMSDK AHB VIP +//----------------------------------------------------------------------------- + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= Accelerator Module search path ============= +//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_filereadcore.v +//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_funnel.v +//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master32.v +//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master64.v diff --git a/flist/apb/apb_ip.flist b/flist/apb/apb_ip.flist index cd12720cd2c874bed7fff76c1d2d6e906e09fb8b..5c4d72466ffa9a70fa35427fe1263805b1d7cf5c 100644 --- a/flist/apb/apb_ip.flist +++ b/flist/apb/apb_ip.flist @@ -16,7 +16,7 @@ +libext+.v+.vlib // ============= CMSDK APB IP search path ============= -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v -$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave.v +//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v +//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v +//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v +//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave.v diff --git a/flist/apb/apb_ip_qs.flist b/flist/apb/apb_ip_qs.flist new file mode 100644 index 0000000000000000000000000000000000000000..dcf0915f90edb2e689ac8a86c4a9ef1fe3fbde13 --- /dev/null +++ b/flist/apb/apb_ip_qs.flist @@ -0,0 +1,22 @@ +//----------------------------------------------------------------------------- +// CMSDK APB IP Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for Accelerator CMSDK AHB IP +//----------------------------------------------------------------------------- + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= CMSDK APB IP search path ============= +//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v +//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v +//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v +//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave.v diff --git a/flist/mem/fpga_mem.flist b/flist/mem/fpga_mem.flist index c59cc67ad8c2aef5623aad61fe35ae814b1379f1..75aeb75736b7372825f3b4e7dbc86806ef6b14d0 100644 --- a/flist/mem/fpga_mem.flist +++ b/flist/mem/fpga_mem.flist @@ -16,7 +16,7 @@ +libext+.v+.vlib // ============= NanoSoC Testbench search path ============= -// -incdir $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/ +// +incdir+$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/ // - Top-level testbench $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v \ No newline at end of file diff --git a/flist/nanosoc/nanosoc_tb.flist b/flist/nanosoc/nanosoc_tb.flist index 043c56417e7613c29301186fedbd00fdf4aa9695..4c7b31c13ccc093e4bce684453d2a6e62eb54192 100644 --- a/flist/nanosoc/nanosoc_tb.flist +++ b/flist/nanosoc/nanosoc_tb.flist @@ -16,7 +16,7 @@ +libext+.v+.vlib // ============= NanoSoC Testbench search path ============= --incdir $(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/ ++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/ // - Top-level testbench $(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_tb.v diff --git a/flist/nanosoc/nanosoc_tb_qs.flist b/flist/nanosoc/nanosoc_tb_qs.flist new file mode 100644 index 0000000000000000000000000000000000000000..acbe0b5463252821fdf4c02432f1619b035d3e67 --- /dev/null +++ b/flist/nanosoc/nanosoc_tb_qs.flist @@ -0,0 +1,34 @@ +//----------------------------------------------------------------------------- +// NanoSoC Testbench Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for NanoSoC Testbench +//----------------------------------------------------------------------------- + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= NanoSoC Testbench search path ============= ++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/ + +// - Top-level testbench +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_tb_qs.v + +// - Testbench components +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_clkreset.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_uart_capture.v + +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_track_tb_iostream.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_ft1248x1_track.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_dma_log_to_file.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_acc_log_to_file.v \ No newline at end of file diff --git a/flist/project/system.flist b/flist/project/system.flist index bc981cd7ad0918b1c599adcc92d41a25c836e60e..c70ea933b3b331539fb21e89c5ae7e94e41c2231 100644 --- a/flist/project/system.flist +++ b/flist/project/system.flist @@ -12,11 +12,6 @@ // Abstract : Verilog Command File for Top-level Accelerator System //----------------------------------------------------------------------------- -// DESIGN_TOP nanosoc_chip - -// ============= Verilog library extensions =========== -+libext+.v+.vlib - // ============= Accelerator Module search path ============= // ! Point this to your accelerator filelist // -f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist @@ -29,13 +24,6 @@ // - Primitives IP -f $(SOCLABS_PROJECT_DIR)/flist/primitives/primitives.flist -// - CMSDK IP --f $(SOCLABS_PROJECT_DIR)/flist/ahb/ahb_ip.flist --f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip.flist - -// - NanoSoC Chip IP --f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_ip.flist - // - NanoSoc Test Interface IP -f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_test_io_ip.flist diff --git a/flist/project/system_tb.flist b/flist/project/top.flist similarity index 67% rename from flist/project/system_tb.flist rename to flist/project/top.flist index f71578841f31e570cfe807088ecff6fa907d70ab..bb6e50fdc3b39ea7926d16740818679c6e113d66 100644 --- a/flist/project/system_tb.flist +++ b/flist/project/top.flist @@ -1,5 +1,5 @@ //----------------------------------------------------------------------------- -// Accelerator System Filelist +// Project Top-level Filelist System Filelist // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // // Contributors @@ -12,19 +12,22 @@ // Abstract : Verilog Command File for Top-level Accelerator System //----------------------------------------------------------------------------- -// DESIGN_TOP nanosoc_tb +// DESIGN_TOP nanosoc_chip // ============= Verilog library extensions =========== +libext+.v+.vlib -// ============= System Component Filelist ================ - -// - CMSDK VIP --f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist - -// - Design +// ============= System Filelist ========================= -f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist -// - Top level +// Testbench -f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist + +// ============= Arm-IP Specific Filelists ========================= +// - NanoSoC Chip IP +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc.flist +// - CMSDK IP +-f $(SOCLABS_PROJECT_DIR)/flist/ahb/ahb_ip.flist +-f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip.flist \ No newline at end of file diff --git a/flist/project/top_qs.flist b/flist/project/top_qs.flist new file mode 100644 index 0000000000000000000000000000000000000000..9ae87c02213c5b8f44ecac73455cb1ba8f57f9ee --- /dev/null +++ b/flist/project/top_qs.flist @@ -0,0 +1,33 @@ +//----------------------------------------------------------------------------- +// Project Top-level Filelist System Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for Top-level Accelerator System +//----------------------------------------------------------------------------- + +// DESIGN_TOP nanosoc_chip + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= System Filelist ========================= +-f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist + +// Testbench +-f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb_qs.flist +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip_qs.flist + +// ============= Arm-IP Specific Filelists ========================= +// - NanoSoC Chip IP +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_qs.flist + +// - CMSDK IP +-f $(SOCLABS_PROJECT_DIR)/flist/ahb/ahb_ip_qs.flist +-f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip_qs.flist \ No newline at end of file diff --git a/nanosoc_tech b/nanosoc_tech index 2b8513fb3346d193280916fb5eb11db90c7dfce9..a2e3324d42d4cad8725c3ea746119cccc094dbcf 160000 --- a/nanosoc_tech +++ b/nanosoc_tech @@ -1 +1 @@ -Subproject commit 2b8513fb3346d193280916fb5eb11db90c7dfce9 +Subproject commit a2e3324d42d4cad8725c3ea746119cccc094dbcf diff --git a/proj-branch b/proj-branch index d004de05b26fb96b51721b15900d36c666fb80c3..8768ce662ff422c287b835a3653ea91aebcbd05a 100644 --- a/proj-branch +++ b/proj-branch @@ -13,6 +13,9 @@ # Add your Accelerator Repository here # accelerator_repo: main nanosoc_tech: feat_nanosoc_regions +slcorem0_tech: main +sldma230_tech: main +socdebug_tech: main accelerator_wrapper_tech: main fpga_lib_tech: main generic_lib_tech: main diff --git a/soctools_flow b/soctools_flow index 1c706759aebfbd539a9f035e94737975e00dd5dd..74d6c1bb134143547eedccefb6393f3759f13fae 160000 --- a/soctools_flow +++ b/soctools_flow @@ -1 +1 @@ -Subproject commit 1c706759aebfbd539a9f035e94737975e00dd5dd +Subproject commit 74d6c1bb134143547eedccefb6393f3759f13fae