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SoCLabs
Accelerator Project
Commits
1ed60a5a
Commit
1ed60a5a
authored
1 year ago
by
dwn1c21
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CI add socpull to stages
parent
0c4195da
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Pipeline
#10260
failed
1 year ago
Stage: compile
Stage: simulate
Stage: simulate_qs
Stage: build
Stage: deploy
Changes
1
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1
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1 changed file
.gitlab-ci.yml
+10
-3
10 additions, 3 deletions
.gitlab-ci.yml
with
10 additions
and
3 deletions
.gitlab-ci.yml
+
10
−
3
View file @
1ed60a5a
...
...
@@ -34,6 +34,7 @@ compile-software:
-
git submodule foreach --recursive git submodule init
-
git fetch --recurse-submodules
-
source set_env.sh
-
socpull
-
cd $SOCLABS_NANOSOC_TECH_DIR
-
make compile_all_code
artifacts
:
...
...
@@ -56,6 +57,7 @@ simulate_regression:
script
:
-
echo "Simulation phase started"
-
source set_env.sh
-
socpull
-
socsim clean all
-
socsim regression_nanosoc
tags
:
...
...
@@ -66,6 +68,7 @@ simulate_quickstart-hello:
script
:
-
echo "Simulation phase started"
-
source set_env.sh
-
socpull
-
socsim clean all
-
socsim test_nanosoc TESTNAME=hello QUICKSTART=yes
tags
:
...
...
@@ -89,8 +92,9 @@ build-job-Z2: # This job runs in the build stage, which runs first.
-
git submodule foreach --recursive git submodule init
-
git fetch --recurse-submodules
-
source set_env.sh
-
socpull
-
cd $SOCLABS_NANOSOC_TECH_DIR
-
make build_fpga FPGA=z2
-
make build_fpga FPGA=z2
ACCELERATOR=no
-
FILE=$SOCLABS_DESIGN_ROOT/imp/fpga/output/pynq_z2/overlays/nanosoc_design.bit
-
if test -f "$FILE"; then
-
echo "Build successful"
...
...
@@ -113,8 +117,9 @@ build-job-ZCU104: # This job runs in the build stage, which runs first.
-
git submodule foreach --recursive git submodule init
-
git fetch --recurse-submodules
-
source set_env.sh
-
socpull
-
cd $SOCLABS_NANOSOC_TECH_DIR
-
make build_fpga FPGA=zcu104
-
make build_fpga FPGA=zcu104
ACCELERATOR=no
-
FILE=$SOCLABS_DESIGN_ROOT/imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit
-
if test -f "$FILE"; then
-
echo "Build successful"
...
...
@@ -204,6 +209,8 @@ deploy-job-ZCU104: # This job runs in the deploy stage.
environment
:
production
script
:
-
echo "Deploying application to ZCU104"
-
source set_env.sh
-
socpull
# list all tests and write list to fpga_tests file
-
find nanosoc_tech/testcodes/*/*.hex > fpga_tests
# start a detached terminal so that the xilinx environment can be opened without interferring w
...
...
@@ -216,7 +223,7 @@ deploy-job-ZCU104: # This job runs in the deploy stage.
-
screen -r zynq -X stuff "./ZCU104_connect.sh\n"
-
sleep
10
# use scp to copy over bit files and python script
-
screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/accelerator-project/nanosoc_tech/fpga/ci_tools/* ./ \n"
-
screen -r zynq -X stuff "scp
-rp
-i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/accelerator-project/nanosoc_tech/fpga/ci_tools/* ./ \n"
-
sleep
2
-
screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/accelerator-project/imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.* ./pynq/overlays/soclabs/ \n"
-
sleep
2
...
...
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