diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index e73ecf7bb42da595c408c54ca34a38795e15661b..011fd9b251e643036df8dbda363a4d8c86cb6459 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -34,6 +34,7 @@ compile-software:
     - git submodule foreach --recursive git submodule init
     - git fetch --recurse-submodules
     - source set_env.sh
+    - socpull
     - cd $SOCLABS_NANOSOC_TECH_DIR
     - make compile_all_code
   artifacts:
@@ -56,6 +57,7 @@ simulate_regression:
   script:
     - echo "Simulation phase started"
     - source set_env.sh
+    - socpull
     - socsim clean all
     - socsim regression_nanosoc
   tags:
@@ -66,6 +68,7 @@ simulate_quickstart-hello:
   script:
     - echo "Simulation phase started"
     - source set_env.sh
+    - socpull
     - socsim clean all
     - socsim test_nanosoc TESTNAME=hello QUICKSTART=yes
   tags:
@@ -89,8 +92,9 @@ build-job-Z2:       # This job runs in the build stage, which runs first.
     - git submodule foreach --recursive git submodule init
     - git fetch --recurse-submodules
     - source set_env.sh
+    - socpull
     - cd $SOCLABS_NANOSOC_TECH_DIR
-    - make build_fpga FPGA=z2
+    - make build_fpga FPGA=z2 ACCELERATOR=no
     - FILE=$SOCLABS_DESIGN_ROOT/imp/fpga/output/pynq_z2/overlays/nanosoc_design.bit 
     - if test -f "$FILE"; then
     -   echo "Build successful"
@@ -113,8 +117,9 @@ build-job-ZCU104:       # This job runs in the build stage, which runs first.
     - git submodule foreach --recursive git submodule init
     - git fetch --recurse-submodules
     - source set_env.sh
+    - socpull
     - cd $SOCLABS_NANOSOC_TECH_DIR
-    - make build_fpga FPGA=zcu104
+    - make build_fpga FPGA=zcu104 ACCELERATOR=no
     - FILE=$SOCLABS_DESIGN_ROOT/imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit 
     - if test -f "$FILE"; then
     -   echo "Build successful"
@@ -204,6 +209,8 @@ deploy-job-ZCU104:      # This job runs in the deploy stage.
   environment: production
   script:
     - echo "Deploying application to ZCU104"
+    - source set_env.sh
+    - socpull
     # list all tests and write list to fpga_tests file
     - find nanosoc_tech/testcodes/*/*.hex > fpga_tests
     # start a detached terminal so that the xilinx environment can be opened without interferring w
@@ -216,7 +223,7 @@ deploy-job-ZCU104:      # This job runs in the deploy stage.
     - screen -r zynq -X stuff "./ZCU104_connect.sh\n"
     - sleep 10
     # use scp to copy over bit files and python script
-    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/accelerator-project/nanosoc_tech/fpga/ci_tools/* ./ \n"
+    - screen -r zynq -X stuff "scp -rp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/accelerator-project/nanosoc_tech/fpga/ci_tools/* ./ \n"
     - sleep 2
     - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/accelerator-project/imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.* ./pynq/overlays/soclabs/ \n"
     - sleep 2