Started moving files across

.gitmodules

@@ -16,3 +16,6 @@ url = https://git.soton.ac.uk/soclabs/nanosoc_tech.git
 [submodule "rtl_primitives_tech"]
 	path = rtl_primitives_tech
 	url = https://git.soton.ac.uk/soclabs/rtl_primitives_tech.git
+[submodule "secworks-aes"]
+	path = secworks-aes
+	url = https://github.com/secworks/aes.git

env/dependency_env.sh

@@ -15,7 +15,7 @@
 #-----------------------------------------------------------------------------
 
 # Accelerator Engine -- Add Your Accelerator Environment Variable HERE!
-# export YOUR_ACCELERATOR_DIR="$SOCLABS_PROJECT_DIR/your_accelerator"
+export ACCELERATOR_DIR="$SOCLABS_PROJECT_DIR/secworks-aes"
 
 # Accelerator Wrapper
 export SOCLABS_WRAPPER_TECH_DIR="$SOCLABS_PROJECT_DIR/accelerator_wrapper_tech"

secworks-aes @ b9a3f196

+Subproject commit b9a3f1965b4e0568f0ca9b2d575ce6ea6fec2f36

simulate/socsim/system_secworks_aes128.sh

+#-----------------------------------------------------------------------------
+# SoC Labs Simulation script for system level verification
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright  2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#!/usr/bin/env bash
+
+# Get simulation name from name of script
+SIM_NAME=`basename -s .sh "$0"`
+
+# Directory to put simulation files
+SIM_DIR=$SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
+
+# Create Directory to put simulation files
+mkdir -p $SIM_DIR
+cd $SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
+
+# Compile Simulation
+# Call makefile in NanoSoC Repo with options
+echo ${2}
+make -C $SOCLABS_NANOSOC_TECH_DIR run_xm \
+    SIM_DIR=$SIM_DIR \
+    ${@:2}
+

system/src/nanosoc_acc_wrapper.v

+//-----------------------------------------------------------------------------
+// SoC Labs Basic Example Accelerator Wrapper
+// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+// David Flynn    (d.w.flynn@soton.ac.uk)
+//
+// Copyright (C) 2023; SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_exp_wrapper #(
+  parameter AHBADDRWIDTH=16,
+  parameter INPACKETWIDTH=128,
+  parameter CFGSIZEWIDTH=64,
+  parameter CFGSCHEMEWIDTH=2,
+  parameter OUTPACKETWIDTH=128,
+  parameter CFGNUMIRQ=4
+  ) (
+    input  wire                      HCLK,       // Clock
+    input  wire                      HRESETn,    // Reset
+
+    // AHB connection to Initiator
+    input  wire                      HSEL_i,
+    input  wire   [AHBADDRWIDTH-1:0] HADDR_i,
+    input  wire   [1:0]              HTRANS_i,
+    input  wire   [2:0]              HSIZE_i,
+    input  wire   [3:0]              HPROT_i,
+    input  wire                      HWRITE_i,
+    input  wire                      HREADY_i,
+    input  wire   [31:0]             HWDATA_i,
+
+    output wire                      HREADYOUT_o,
+    output wire                      HRESP_o,
+    output wire   [31:0]             HRDATA_o,
+
+    // Input Data Request Signal to DMAC
+    output wire                      exp_drq_ip_o,
+    input  wire                      exp_dlast_ip_i,
+
+    // Output Data Request Signal to DMAC
+    output wire                      exp_drq_op_o,
+    input  wire                      exp_dlast_op_i,
+    
+    // Interrupts
+    output wire   [CFGNUMIRQ-1:0]    exp_irq_o
+
+  );
+  
+  soclabs_ahb_aes128_ctrl u_exp_aes128 (
+    .ahb_hclk        (HCLK),
+    .ahb_hresetn     (HRESETn),
+    .ahb_hsel        (HSEL_i),
+    .ahb_haddr16     (HADDR_i[15:0]),
+    .ahb_htrans      (HTRANS_i),
+    .ahb_hwrite      (HWRITE_i),
+    .ahb_hsize       (HSIZE_i),
+    .ahb_hprot       (HPROT_i),
+    .ahb_hwdata      (HWDATA_i),
+    .ahb_hready      (HREADY_i),
+    .ahb_hrdata      (HRDATA_o),
+    .ahb_hreadyout   (HREADYOUT_o),
+    .ahb_hresp       (HRESP_o),
+    .drq_ipdma128    (exp_drq_ip_o),
+    .dlast_ipdma128  (1'b0),
+    .drq_opdma128    (exp_drq_op_o),
+    .dlast_opdma128  (1'b0),
+    .irq_key128      (exp_irq_o[0]),
+    .irq_ip128       (exp_irq_o[1]),
+    .irq_op128       (exp_irq_o[2]),
+    .irq_error       (exp_irq_o[3]),
+    .irq_merged      ( )
+  );
+
+endmodule

system/src/nanosoc_exp_wrapper.v

+//-----------------------------------------------------------------------------
+// SoC Labs Basic Example Accelerator Wrapper
+// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+// David Flynn    (d.w.flynn@soton.ac.uk)
+//
+// Copyright (C) 2023; SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_exp_wrapper #(
+  parameter AHBADDRWIDTH=16,
+  parameter INPACKETWIDTH=128,
+  parameter CFGSIZEWIDTH=64,
+  parameter CFGSCHEMEWIDTH=2,
+  parameter OUTPACKETWIDTH=128,
+  parameter CFGNUMIRQ=4
+  ) (
+    input  wire                      HCLK,       // Clock
+    input  wire                      HRESETn,    // Reset
+
+    // AHB connection to Initiator
+    input  wire                      HSEL_i,
+    input  wire   [AHBADDRWIDTH-1:0] HADDR_i,
+    input  wire   [1:0]              HTRANS_i,
+    input  wire   [2:0]              HSIZE_i,
+    input  wire   [3:0]              HPROT_i,
+    input  wire                      HWRITE_i,
+    input  wire                      HREADY_i,
+    input  wire   [31:0]             HWDATA_i,
+
+    output wire                      HREADYOUT_o,
+    output wire                      HRESP_o,
+    output wire   [31:0]             HRDATA_o,
+
+    // Input Data Request Signal to DMAC
+    output wire                      exp_drq_ip_o,
+    input  wire                      exp_dlast_ip_i,
+
+    // Output Data Request Signal to DMAC
+    output wire                      exp_drq_op_o,
+    input  wire                      exp_dlast_op_i,
+    
+    // Interrupts
+    output wire   [CFGNUMIRQ-1:0]    exp_irq_o
+
+  );
+  
+  soclabs_ahb_aes128_ctrl u_exp_aes128 (
+    .ahb_hclk        (HCLK),
+    .ahb_hresetn     (HRESETn),
+    .ahb_hsel        (HSEL_i),
+    .ahb_haddr16     (HADDR_i[15:0]),
+    .ahb_htrans      (HTRANS_i),
+    .ahb_hwrite      (HWRITE_i),
+    .ahb_hsize       (HSIZE_i),
+    .ahb_hprot       (HPROT_i),
+    .ahb_hwdata      (HWDATA_i),
+    .ahb_hready      (HREADY_i),
+    .ahb_hrdata      (HRDATA_o),
+    .ahb_hreadyout   (HREADYOUT_o),
+    .ahb_hresp       (HRESP_o),
+    .drq_ipdma128    (exp_drq_ip_o),
+    .dlast_ipdma128  (1'b0),
+    .drq_opdma128    (exp_drq_op_o),
+    .dlast_opdma128  (1'b0),
+    .irq_key128      (exp_irq_o[0]),
+    .irq_ip128       (exp_irq_o[1]),
+    .irq_op128       (exp_irq_o[2]),
+    .irq_error       (exp_irq_o[3]),
+    .irq_merged      ( )
+  );
+
+endmodule