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Commit 0dd8a2a6 authored by dam1n19's avatar dam1n19
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Started redistributing filelists to repos

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1 merge request!1Changed set_env flow to source script in soctools and breadcrumb left in...
//-----------------------------------------------------------------------------
// NanoSoC Testbench Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for NanoSoC Testbench
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= NanoSoC Testbench search path =============
+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/
// - Top-level testbench
$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/nanosoc_tb.v
// - Testbench components
$(SOCLABS_NANOSOC_TECH_DIR)/verif/control/verilog/nanosoc_clkreset.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_uart_capture.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_track_tb_iostream.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_track.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_dma_log_to_file.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_accelerator_ss_logger.v
\ No newline at end of file
//-----------------------------------------------------------------------------
// NanoSoC Testbench Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for NanoSoC Testbench
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= NanoSoC Testbench search path =============
+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/
// - Top-level testbench
$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_tb_qs.v
// - Testbench components
$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_clkreset.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_uart_capture.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_track_tb_iostream.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_ft1248x1_track.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_dma_log_to_file.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_acc_log_to_file.v
\ No newline at end of file
//-----------------------------------------------------------------------------
// NanoSoC Chip Test Interface IP Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for NanoSoC Chip Test Interface IP
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= NanoSoC Chip Test Interface IP Filelists =============
$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/socket/verilog/axi_stream_io_v1_0_axi_s.v
$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/socket/verilog/axi_stream_io_v1_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/socket/verilog/ft232h_ft1248_x1.v
\ No newline at end of file
...@@ -24,15 +24,9 @@ ...@@ -24,15 +24,9 @@
// - Primitives IP // - Primitives IP
-f $(SOCLABS_PROJECT_DIR)/flist/primitives/primitives.flist -f $(SOCLABS_PROJECT_DIR)/flist/primitives/primitives.flist
// - NanoSoc Test Interface IP
-f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_test_io_ip.flist
// - Generic Pad Library // - Generic Pad Library
-f $(SOCLABS_PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist -f $(SOCLABS_PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist
// - NanoSoC Custom Expansion Region
//$(SOCLABS_PROJECT_DIR)/system/src/nanosoc_exp.v
// - FPGA sram // - FPGA sram
-f $(SOCLABS_PROJECT_DIR)/flist/mem/fpga_mem.flist -f $(SOCLABS_PROJECT_DIR)/flist/mem/fpga_mem.flist
......
...@@ -20,9 +20,8 @@ ...@@ -20,9 +20,8 @@
// ============= System Filelist ========================= // ============= System Filelist =========================
-f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist -f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist
// Testbench // NanoSoC Testbench
-f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist -f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_tb.flist
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist
// ============= Arm-IP Specific Filelists ========================= // ============= Arm-IP Specific Filelists =========================
// - NanoSoC Chip IP // - NanoSoC Chip IP
......
...@@ -20,9 +20,8 @@ ...@@ -20,9 +20,8 @@
// ============= System Filelist ========================= // ============= System Filelist =========================
-f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist -f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist
// Testbench // NanoSoC Testbench
-f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb_qs.flist -f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_tb_qs.flist
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip_qs.flist
// ============= Arm-IP Specific Filelists ========================= // ============= Arm-IP Specific Filelists =========================
// - NanoSoC Chip IP // - NanoSoC Chip IP
......
Subproject commit 916c2ada153b3b45abf65b88727e3cb9528322a1 Subproject commit a975485547e457621b7605d147b055833b5e67d5
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