From 0dd8a2a6a4c777371e3c121700119e935a320d80 Mon Sep 17 00:00:00 2001 From: dam1n19 <dam1n19@soton.ac.uk> Date: Fri, 30 Jun 2023 10:44:30 +0100 Subject: [PATCH] Started redistributing filelists to repos --- flist/nanosoc/nanosoc_tb.flist | 35 -------------------------- flist/nanosoc/nanosoc_tb_qs.flist | 34 ------------------------- flist/nanosoc/nanosoc_test_io_ip.flist | 21 ---------------- flist/project/system.flist | 6 ----- flist/project/top.flist | 5 ++-- flist/project/top_qs.flist | 5 ++-- nanosoc_tech | 2 +- 7 files changed, 5 insertions(+), 103 deletions(-) delete mode 100644 flist/nanosoc/nanosoc_tb.flist delete mode 100644 flist/nanosoc/nanosoc_tb_qs.flist delete mode 100644 flist/nanosoc/nanosoc_test_io_ip.flist diff --git a/flist/nanosoc/nanosoc_tb.flist b/flist/nanosoc/nanosoc_tb.flist deleted file mode 100644 index 2126968..0000000 --- a/flist/nanosoc/nanosoc_tb.flist +++ /dev/null @@ -1,35 +0,0 @@ -//----------------------------------------------------------------------------- -// NanoSoC Testbench Filelist -// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. -// -// Contributors -// -// David Mapstone (d.a.mapstone@soton.ac.uk) -// -// Copyright � 2021-3, SoC Labs (www.soclabs.org) -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -// Abstract : Verilog Command File for NanoSoC Testbench -//----------------------------------------------------------------------------- - -// ============= Verilog library extensions =========== -+libext+.v+.vlib - -// ============= NanoSoC Testbench search path ============= -+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/ - -// - Top-level testbench -$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/nanosoc_tb.v - -// - Testbench components -$(SOCLABS_NANOSOC_TECH_DIR)/verif/control/verilog/nanosoc_clkreset.v - - -$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_uart_capture.v -$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v -$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v -$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v -$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_track_tb_iostream.v -$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_track.v -$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_dma_log_to_file.v -$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_accelerator_ss_logger.v \ No newline at end of file diff --git a/flist/nanosoc/nanosoc_tb_qs.flist b/flist/nanosoc/nanosoc_tb_qs.flist deleted file mode 100644 index acbe0b5..0000000 --- a/flist/nanosoc/nanosoc_tb_qs.flist +++ /dev/null @@ -1,34 +0,0 @@ -//----------------------------------------------------------------------------- -// NanoSoC Testbench Filelist -// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. -// -// Contributors -// -// David Mapstone (d.a.mapstone@soton.ac.uk) -// -// Copyright � 2021-3, SoC Labs (www.soclabs.org) -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -// Abstract : Verilog Command File for NanoSoC Testbench -//----------------------------------------------------------------------------- - -// ============= Verilog library extensions =========== -+libext+.v+.vlib - -// ============= NanoSoC Testbench search path ============= -+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/ - -// - Top-level testbench -$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_tb_qs.v - -// - Testbench components -$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_clkreset.v -$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_uart_capture.v - -$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v -$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v -$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v -$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_track_tb_iostream.v -$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_ft1248x1_track.v -$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_dma_log_to_file.v -$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_acc_log_to_file.v \ No newline at end of file diff --git a/flist/nanosoc/nanosoc_test_io_ip.flist b/flist/nanosoc/nanosoc_test_io_ip.flist deleted file mode 100644 index 8cf68ee..0000000 --- a/flist/nanosoc/nanosoc_test_io_ip.flist +++ /dev/null @@ -1,21 +0,0 @@ -//----------------------------------------------------------------------------- -// NanoSoC Chip Test Interface IP Filelist -// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. -// -// Contributors -// -// David Mapstone (d.a.mapstone@soton.ac.uk) -// -// Copyright � 2021-3, SoC Labs (www.soclabs.org) -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -// Abstract : Verilog Command File for NanoSoC Chip Test Interface IP -//----------------------------------------------------------------------------- - -// ============= Verilog library extensions =========== -+libext+.v+.vlib - -// ============= NanoSoC Chip Test Interface IP Filelists ============= -$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/socket/verilog/axi_stream_io_v1_0_axi_s.v -$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/socket/verilog/axi_stream_io_v1_0.v -$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/socket/verilog/ft232h_ft1248_x1.v \ No newline at end of file diff --git a/flist/project/system.flist b/flist/project/system.flist index c03340d..325f00f 100644 --- a/flist/project/system.flist +++ b/flist/project/system.flist @@ -24,15 +24,9 @@ // - Primitives IP -f $(SOCLABS_PROJECT_DIR)/flist/primitives/primitives.flist -// - NanoSoc Test Interface IP --f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_test_io_ip.flist - // - Generic Pad Library -f $(SOCLABS_PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist -// - NanoSoC Custom Expansion Region -//$(SOCLABS_PROJECT_DIR)/system/src/nanosoc_exp.v - // - FPGA sram -f $(SOCLABS_PROJECT_DIR)/flist/mem/fpga_mem.flist diff --git a/flist/project/top.flist b/flist/project/top.flist index bb6e50f..921ee5e 100644 --- a/flist/project/top.flist +++ b/flist/project/top.flist @@ -20,9 +20,8 @@ // ============= System Filelist ========================= -f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist -// Testbench --f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist --f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist +// NanoSoC Testbench +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_tb.flist // ============= Arm-IP Specific Filelists ========================= // - NanoSoC Chip IP diff --git a/flist/project/top_qs.flist b/flist/project/top_qs.flist index 9ae87c0..5903d2e 100644 --- a/flist/project/top_qs.flist +++ b/flist/project/top_qs.flist @@ -20,9 +20,8 @@ // ============= System Filelist ========================= -f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist -// Testbench --f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb_qs.flist --f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip_qs.flist +// NanoSoC Testbench +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_tb_qs.flist // ============= Arm-IP Specific Filelists ========================= // - NanoSoC Chip IP diff --git a/nanosoc_tech b/nanosoc_tech index 916c2ad..a975485 160000 --- a/nanosoc_tech +++ b/nanosoc_tech @@ -1 +1 @@ -Subproject commit 916c2ada153b3b45abf65b88727e3cb9528322a1 +Subproject commit a975485547e457621b7605d147b055833b5e67d5 -- GitLab