Verified Commit e2c9a347 authored by Minyong Li's avatar Minyong Li 💬
Browse files

core.ControlWord: add data memory write en signal

parent eb9acceb
...@@ -10,6 +10,7 @@ class ControlWord(addrWidth: Int, immWidth: Int = 8) extends Bundle { ...@@ -10,6 +10,7 @@ class ControlWord(addrWidth: Int, immWidth: Int = 8) extends Bundle {
val absoluteBranch = Bool() val absoluteBranch = Bool()
val relativeBranch = Bool() val relativeBranch = Bool()
val ramReadAddress = Vec(2, UInt(addrWidth.W)) val ramReadAddress = Vec(2, UInt(addrWidth.W))
val ramWriteEnable = Bool()
val ramWriteAddress = UInt(addrWidth.W) val ramWriteAddress = UInt(addrWidth.W)
val fillConstants = Bool() val fillConstants = Bool()
val incrementBlockCount = Bool() val incrementBlockCount = Bool()
......
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