From e2c9a3476c1fba89c929f9f1144bc5008ecdccbc Mon Sep 17 00:00:00 2001 From: Minyong Li <ml10g20@soton.ac.uk> Date: Sat, 26 Jun 2021 23:18:36 +0100 Subject: [PATCH] core.ControlWord: add data memory write en signal --- src/main/scala/uk/ac/soton/ecs/can/core/ControlWord.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/ControlWord.scala b/src/main/scala/uk/ac/soton/ecs/can/core/ControlWord.scala index 5a4e3da..32838e9 100644 --- a/src/main/scala/uk/ac/soton/ecs/can/core/ControlWord.scala +++ b/src/main/scala/uk/ac/soton/ecs/can/core/ControlWord.scala @@ -10,6 +10,7 @@ class ControlWord(addrWidth: Int, immWidth: Int = 8) extends Bundle { val absoluteBranch = Bool() val relativeBranch = Bool() val ramReadAddress = Vec(2, UInt(addrWidth.W)) + val ramWriteEnable = Bool() val ramWriteAddress = UInt(addrWidth.W) val fillConstants = Bool() val incrementBlockCount = Bool() -- GitLab