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core.{Program,Data}Memory{,Test}: add syncMem config
This allows switching between Mem (usually synthesized into register groups) and SyncReadMem (usually synthesized into FPGA block memories).
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- src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala 9 additions, 3 deletionssrc/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
- src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala 9 additions, 3 deletionssrc/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
- src/test/scala/uk/ac/soton/ecs/can/core/ProgramMemoryTest.scala 13 additions, 0 deletions...st/scala/uk/ac/soton/ecs/can/core/ProgramMemoryTest.scala
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