Verified Commit 3fb7fb0a authored by Minyong Li's avatar Minyong Li 💬
Browse files

core.{Program,Data}Memory{,Test}: add syncMem config

This allows switching between Mem (usually synthesized into
register groups) and SyncReadMem (usually synthesized into FPGA
block memories).
parent 0ed01c1d
...@@ -5,8 +5,12 @@ package uk.ac.soton.ecs.can.core ...@@ -5,8 +5,12 @@ package uk.ac.soton.ecs.can.core
import chisel3._ import chisel3._
class DataMemory(addrWidth: Int, dataWidth: Int, size: Int) class DataMemory(
extends MultiIOModule { addrWidth: Int,
dataWidth: Int,
size: Int,
syncMem: Boolean = true
) extends MultiIOModule {
val read = IO(new Bundle { val read = IO(new Bundle {
val addr = Input(UInt(addrWidth.W)) val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(dataWidth.W)) val data = Output(UInt(dataWidth.W))
...@@ -17,7 +21,9 @@ class DataMemory(addrWidth: Int, dataWidth: Int, size: Int) ...@@ -17,7 +21,9 @@ class DataMemory(addrWidth: Int, dataWidth: Int, size: Int)
val data = Input(UInt(dataWidth.W)) val data = Input(UInt(dataWidth.W))
}) })
val mem = SyncReadMem(size, UInt(dataWidth.W)) val mem =
if (syncMem) SyncReadMem(size, UInt(dataWidth.W))
else Mem(size, UInt(dataWidth.W))
read.data := mem(read.addr) read.data := mem(read.addr)
......
...@@ -5,8 +5,12 @@ package uk.ac.soton.ecs.can.core ...@@ -5,8 +5,12 @@ package uk.ac.soton.ecs.can.core
import chisel3._ import chisel3._
class ProgramMemory(addrWidth: Int, cwWidth: Int, size: Int) class ProgramMemory(
extends MultiIOModule { addrWidth: Int,
cwWidth: Int,
size: Int,
syncMem: Boolean = true
) extends MultiIOModule {
val br = IO(new Bundle { val br = IO(new Bundle {
val abs = Input(Bool()) val abs = Input(Bool())
val rel = Input(Bool()) val rel = Input(Bool())
...@@ -19,7 +23,9 @@ class ProgramMemory(addrWidth: Int, cwWidth: Int, size: Int) ...@@ -19,7 +23,9 @@ class ProgramMemory(addrWidth: Int, cwWidth: Int, size: Int)
val data = Input(UInt(cwWidth.W)) val data = Input(UInt(cwWidth.W))
}) })
val mem = SyncReadMem(size, UInt(cwWidth.W)) val mem =
if (syncMem) SyncReadMem(size, UInt(cwWidth.W))
else Mem(size, UInt(cwWidth.W))
val pc = RegInit(0.U(addrWidth.W)) val pc = RegInit(0.U(addrWidth.W))
when(write.en) { when(write.en) {
......
...@@ -60,6 +60,19 @@ class ProgramMemoryTest extends FlatSpec with ChiselScalatestTester { ...@@ -60,6 +60,19 @@ class ProgramMemoryTest extends FlatSpec with ChiselScalatestTester {
c.clock.step() c.clock.step()
} }
} }
test(new ProgramMemory(addrWidth, cwWidth, size, false)) { c =>
c.br.abs.poke(false.B)
c.br.rel.poke(false.B)
c.br.addr.poke(0.U(addrWidth.W))
initMemory(c)
memMap.foreach { m =>
c.cw.expect(m._2)
c.clock.step()
}
}
} }
it should "do relative branching correctly" in { it should "do relative branching correctly" in {
......
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