From 3fb7fb0ade0359c0e4ea8f646bb83b6de2b9ef0f Mon Sep 17 00:00:00 2001
From: Minyong Li <ml10g20@soton.ac.uk>
Date: Thu, 24 Jun 2021 20:08:56 +0100
Subject: [PATCH] core.{Program,Data}Memory{,Test}: add syncMem config
This allows switching between Mem (usually synthesized into
register groups) and SyncReadMem (usually synthesized into FPGA
block memories).
---
.../scala/uk/ac/soton/ecs/can/core/DataMemory.scala | 12 +++++++++---
.../uk/ac/soton/ecs/can/core/ProgramMemory.scala | 12 +++++++++---
.../ac/soton/ecs/can/core/ProgramMemoryTest.scala | 13 +++++++++++++
3 files changed, 31 insertions(+), 6 deletions(-)
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
index 50925df..8d726db 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
@@ -5,8 +5,12 @@ package uk.ac.soton.ecs.can.core
import chisel3._
-class DataMemory(addrWidth: Int, dataWidth: Int, size: Int)
- extends MultiIOModule {
+class DataMemory(
+ addrWidth: Int,
+ dataWidth: Int,
+ size: Int,
+ syncMem: Boolean = true
+) extends MultiIOModule {
val read = IO(new Bundle {
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(dataWidth.W))
@@ -17,7 +21,9 @@ class DataMemory(addrWidth: Int, dataWidth: Int, size: Int)
val data = Input(UInt(dataWidth.W))
})
- val mem = SyncReadMem(size, UInt(dataWidth.W))
+ val mem =
+ if (syncMem) SyncReadMem(size, UInt(dataWidth.W))
+ else Mem(size, UInt(dataWidth.W))
read.data := mem(read.addr)
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
index c43f54c..1575d7f 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
@@ -5,8 +5,12 @@ package uk.ac.soton.ecs.can.core
import chisel3._
-class ProgramMemory(addrWidth: Int, cwWidth: Int, size: Int)
- extends MultiIOModule {
+class ProgramMemory(
+ addrWidth: Int,
+ cwWidth: Int,
+ size: Int,
+ syncMem: Boolean = true
+) extends MultiIOModule {
val br = IO(new Bundle {
val abs = Input(Bool())
val rel = Input(Bool())
@@ -19,7 +23,9 @@ class ProgramMemory(addrWidth: Int, cwWidth: Int, size: Int)
val data = Input(UInt(cwWidth.W))
})
- val mem = SyncReadMem(size, UInt(cwWidth.W))
+ val mem =
+ if (syncMem) SyncReadMem(size, UInt(cwWidth.W))
+ else Mem(size, UInt(cwWidth.W))
val pc = RegInit(0.U(addrWidth.W))
when(write.en) {
diff --git a/src/test/scala/uk/ac/soton/ecs/can/core/ProgramMemoryTest.scala b/src/test/scala/uk/ac/soton/ecs/can/core/ProgramMemoryTest.scala
index 50025d8..0ac5312 100644
--- a/src/test/scala/uk/ac/soton/ecs/can/core/ProgramMemoryTest.scala
+++ b/src/test/scala/uk/ac/soton/ecs/can/core/ProgramMemoryTest.scala
@@ -60,6 +60,19 @@ class ProgramMemoryTest extends FlatSpec with ChiselScalatestTester {
c.clock.step()
}
}
+
+ test(new ProgramMemory(addrWidth, cwWidth, size, false)) { c =>
+ c.br.abs.poke(false.B)
+ c.br.rel.poke(false.B)
+ c.br.addr.poke(0.U(addrWidth.W))
+
+ initMemory(c)
+
+ memMap.foreach { m =>
+ c.cw.expect(m._2)
+ c.clock.step()
+ }
+ }
}
it should "do relative branching correctly" in {
--
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