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Commit c184cbce authored by ks6n19's avatar ks6n19
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Update software/code/main.c 

Deleted behavioural/ahb_pixel_memory.sv.bak, behavioural/de0_wrapper.sv, behavioural/de1_soc_wrapper.sv.bak, behavioural/ncverilog.history, behavioural/new file, behavioural/ncverilog.log, behavioural/de2_wrapper.sv, behavioural/raster.sv, behavioural/razzle.sv.bak, behavioural/triangle.sv, constraints/DE0.qsf, constraints/DE2.qsf, constraints/Nexys4_Master.xdc, constraints/nexys4_wrapper.xdc, behavioural/nexys4_wrapper.sv files
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behavioural/ahb_pixel_memory.sv.bak deleted 100755 → 0
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View file @ 22cb7ecb
// Example code for an M0 AHBLite System
// Iain McNally
// ECS, University of Soutampton
//
// This module is an AHB-Lite Slave containing a RAM
// Since this loads a program it is for FPGA use only
//
// Number of addressable locations : 307200
// Size of each addressable location : bits_per_pixel bits
// Supported transfer sizes : Word
// Alignment of base address : Word aligned
//
// Memory is synchronous which should suit block memory types
// Read takes 1 cycle
// Write takes 2 cycles (single wait state)
//
// Note this is not the most efficient design but works with
// Xilinx and Altera(Intel) FPGAs
//
module ahb_pixel_memory #(
)(
//AHBLITE INTERFACE
//Slave Select Signal
input HSEL,
//Global Signals
input HCLK,
input HRESETn,
//Address, Control & Write Data
input HREADY,
input [31:0] HADDR,
input [1:0] HTRANS,
input HWRITE,
input [2:0] HSIZE,
input [31:0] HWDATA,
// non ahb input
input [9:0] pixel_x ,
input [8:0] pixel_y ,
// Transfer Response & Read Data
output HREADYOUT,
output logic [31:0] HRDATA,
//Non-AHB Signals
output logic pixel
);
timeunit 1ns;
timeprecision 100ps;
localparam No_Transfer = 2'b0;
//memory
logic [7:0] memory [0:307199] ;
// other declarations
logic write_enable, read_enable;
logic [18:0] word_address;
logic [18:0] pixel_address ;
//Generate the control signals here:
always_ff @(posedge HCLK, negedge HRESETn)
if (! HRESETn )
begin
write_enable <= '0;
read_enable <= '0;
word_address <= '0;
end
else if ( HREADY && HSEL && (HTRANS != No_Transfer) )
begin
write_enable <= HWRITE;
read_enable <= ! HWRITE;
word_address <= HADDR[20:2];
end
else
begin
write_enable <= '0;
read_enable <= '0;
word_address <= '0;
end
//memory
always_ff @(posedge HCLK)
begin
if( write_enable )
memory[word_address] <= HWDATA ;
end
always_comb
pixel_address = (pixel_y * 640) + pixel_x ;
assign pixel = memory[pixel_address] ;
assign HRDATA = read_enable ? memory[word_address] : '0 ;
/*
assign bv1 = memory[0] ;
assign bv2 = memory[1] ;
assign bv3 = memory[2] ;
assign tv1 = memory[3] ;
assign tv2 = memory[4] ;
assign tv3 = memory[5] ;
assign BCO = memory[6] ;
assign TCO = memory[7] ;
*/
//Transfer Response
assign HREADYOUT = '1; //Single Cycle Wait State for Write
endmodule
behavioural/de0_wrapper.sv deleted 100644 → 0
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// Example code for an M0 AHBLite System
// Iain McNally
// ECS, University of Soutampton
//
// This module is a wrapper allowing the system to be used on the DE0 FPGA board
//
module de0_wrapper(
input CLOCK_50,
input [9:0] SW,
input [2:0] KEY, // de0 keys are active low
output [9:0] LEDG,
output [7:0] HEX0,
output [7:0] HEX1,
output [7:0] HEX2,
output [7:0] HEX3
);
timeunit 1ns;
timeprecision 100ps;
localparam heartbeat_count_msb = 25;
wire HCLK, HRESETn, LOCKUP, DataValid;
wire [1:0] Buttons;
wire [15:0] Switches;
assign Switches = { 6'd0, SW }; // DE0 has just 10 switches
assign Buttons = ~KEY[1:0];
arm_soc soc_inst(.HCLK, .HRESETn, .DataOut(LEDG), .DataValid, .Switches, .Buttons, .LOCKUP);
assign DataInvalid = ! DataValid;
// Drive HRESETn directly from active low CPU KEY[2] button
assign HRESETn = KEY[2];
// Drive HCLK from 50MHz de0 board clock
assign HCLK = CLOCK_50;
// This code gives us a heartbeat signal on the least significant
// decimal point of the seven segment display
//
logic running, heartbeat;
logic [heartbeat_count_msb:0] tick_count;
always_ff @(posedge CLOCK_50, negedge HRESETn )
if ( ! HRESETn )
begin
running <= 0;
heartbeat <= 0;
tick_count <= 0;
end
else
begin
running <= 1;
heartbeat = tick_count[heartbeat_count_msb] && tick_count[heartbeat_count_msb-2];
tick_count <= tick_count + 1;
end
// seven segment display to indicate system status
assign HEX0 = ~{heartbeat, 1'b0,
!DataValid&&!LOCKUP,
!DataValid&&!LOCKUP,
!DataValid&&!LOCKUP,
!LOCKUP,
!LOCKUP,
!DataValid&&!LOCKUP };
// HEX1 is off
assign HEX1 = ~{8'b0000_0000 };
// running shows as r on HEX2
assign HEX2 = ~{2'b00,running,1'b0,running, 4'b000 };
// LOCKUP shows as L on HEX3
assign HEX3 = ~{2'b00,LOCKUP,LOCKUP,LOCKUP, 3'b000 };
endmodule
behavioural/de1_soc_wrapper.sv.bak deleted 100644 → 0
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// Example code for an M0 AHBLite System
// Iain McNally
// ECS, University of Soutampton
//
// This module is a wrapper allowing the system to be used on the DE1-SoC FPGA board
//
module de1_soc_wrapper(
input CLOCK_50,
input [9:0] SW,
input [3:0] KEY, // de1 keys are active low
output [9:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output logic [7:0] VGA_R,VGA_G,VGA_B,
output logic VGA_HS,VGA_VS, VGA_CLK, VGA_BLANK_N
);
timeunit 1ns;
timeprecision 100ps;
localparam heartbeat_count_msb = 25;
wire HCLK, HRESETn, LOCKUP;
wire [1:0] Buttons;
wire [15:0] Switches;
logic pixel ;
logic [9:0] pixel_x ;
logic [8:0] pixel_y ;
assign Switches = { 6'd0, SW }; // DE1-SoC has just 10 switches
assign Buttons = ~KEY[1:0];
arm_soc soc_inst(.HCLK, .HRESETn, .Switches,.pixel, .pixel_x, .pixel_y .Buttons, .LOCKUP);
razzle raz_inst (
.CLOCK_50(CLOCK_50), .KEY(KEY), .pixel_x(pixel_x), .pixel_y(pixel_y), .pixel(pixel),
.VGA_R(VGA_R),.VGA_G(VGA_G),.VGA_B(VGA_B),
.VGA_HS(VGA_HS),.VGA_VS(VGA_VS), .VGA_CLK(VGA_CLK),
.VGA_BLANK_N(VGA_BLANK_N)
);
// Drive HRESETn directly from active low CPU KEY[2] button
assign HRESETn = KEY[2];
// Drive HCLK from 50MHz de0 board clock
assign HCLK = CLOCK_50;
// This code gives us a heartbeat signal
//
logic running, heartbeat;
logic [heartbeat_count_msb:0] tick_count;
always_ff @(posedge CLOCK_50, negedge HRESETn )
if ( ! HRESETn )
begin
running <= 0;
heartbeat <= 0;
tick_count <= 0;
end
else
begin
running <= 1;
heartbeat = tick_count[heartbeat_count_msb] && tick_count[heartbeat_count_msb-2];
tick_count <= tick_count + 1;
end
// seven segment display to indicate system status
// HEX0 is heartbeat
assign HEX0 = (heartbeat) ? 7'b0100011 : '1;
// HEX1 is DataValid
assign HEX1 = ~{!LOCKUP};
// running shows as r on HEX2
assign HEX2 = ~{1'b0,running,1'b0,running, 4'b000 };
// LOCKUP shows as L on HEX3
assign HEX3 = ~{1'b0,LOCKUP,LOCKUP,LOCKUP, 3'b000 };
endmodule
behavioural/de2_wrapper.sv deleted 100644 → 0
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− 85
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// Example code for an M0 AHBLite System
// Iain McNally
// ECS, University of Soutampton
//
// This module is a wrapper allowing the system to be used on the DE1-SoC FPGA board
//
module de2_wrapper(
input CLOCK_50,
input [15:0] SW,
input [2:0] KEY, // DE2 keys are active low
output [15:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3
);
timeunit 1ns;
timeprecision 100ps;
localparam heartbeat_count_msb = 25;
wire HCLK, HRESETn, LOCKUP, DataValid;
wire [1:0] Buttons;
wire [15:0] Switches;
assign Switches = SW; // DE2 has nore than 16 switches
assign Buttons = ~KEY[1:0];
arm_soc soc_inst(.HCLK, .HRESETn, .DataOut(LEDR), .DataValid, .Switches, .Buttons, .LOCKUP);
// Drive HRESETn directly from active low CPU KEY[2] button
assign HRESETn = KEY[2];
// Drive HCLK from 50MHz de0 board clock
assign HCLK = CLOCK_50;
// This code gives us a heartbeat signal
//
logic running, heartbeat;
logic [heartbeat_count_msb:0] tick_count;
always_ff @(posedge CLOCK_50, negedge HRESETn )
if ( ! HRESETn )
begin
running <= 0;
heartbeat <= 0;
tick_count <= 0;
end
else
begin
running <= 1;
heartbeat = tick_count[heartbeat_count_msb] && tick_count[heartbeat_count_msb-2];
tick_count <= tick_count + 1;
end
// seven segment display to indicate system status
// HEX0 is heartbeat
assign HEX0 = (heartbeat) ? 7'b0100011 : '1;
// HEX1 is DataValid
assign HEX1 = ~{!DataValid&&!LOCKUP,
!DataValid&&!LOCKUP,
!DataValid&&!LOCKUP,
!LOCKUP,
!LOCKUP,
!DataValid&&!LOCKUP };
// running shows as r on HEX2
assign HEX2 = ~{1'b0,running,1'b0,running, 4'b000 };
// LOCKUP shows as L on HEX3
assign HEX3 = ~{1'b0,LOCKUP,LOCKUP,LOCKUP, 3'b000 };
endmodule
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s1(03Sep2020:15:32:34): ncverilog ahb_pixel_memory.sv
s2(03Sep2020:16:20:52): ncverilog ahb_pixel_memory.sv
s3(03Sep2020:16:22:50): ncverilog ahb_pixel_memory.sv
s4(03Sep2020:16:24:06): ncverilog ahb_pixel_memory.sv
s5(03Sep2020:16:24:54): ncverilog ahb_pixel_memory.sv
s6(03Sep2020:16:27:48): ncverilog ahb_pixel_memory.sv
s7(03Sep2020:16:28:18): ncverilog ahb_pixel_memory.sv
s8(03Sep2020:16:30:37): ncverilog ahb_pixel_memory.sv
s9(03Sep2020:16:33:18): ncverilog ahb_pixel_memory.sv
s10(03Sep2020:16:33:55): ncverilog ahb_pixel_memory.sv
s11(03Sep2020:16:34:17): ncverilog ahb_pixel_memory.sv
s12(03Sep2020:16:39:58): ncverilog ahb_pixel_memory.sv
s13(03Sep2020:16:40:56): ncverilog ahb_pixel_memory.sv
s14(03Sep2020:16:44:26): ncverilog ahb_pixel_memory.sv
s15(03Sep2020:21:16:10): ncverilog ahb_pixel_memory.sv
s16(03Sep2020:21:16:58): ncverilog ahb_pixel_memory.sv
s17(03Sep2020:21:17:06): ncverilog ahb_pixel_memory.sv
s18(03Sep2020:21:19:03): ncverilog ahb_pixel_memory.sv
s19(03Sep2020:21:22:12): ncverilog ahb_pixel_memory.sv
s20(03Sep2020:21:24:32): ncverilog ahb_pixel_memory.sv
s21(03Sep2020:21:26:50): ncverilog ahb_pixel_memory.sv
s22(03Sep2020:21:28:09): ncverilog ahb_pixel_memory.sv
s23(03Sep2020:21:32:21): ncverilog ahb_pixel_memory.sv
s24(03Sep2020:22:38:44): ncverilog ahb_pixel_memory.sv
s25(03Sep2020:22:39:25): ncverilog ahb_pixel_memory.sv
s26(03Sep2020:22:40:54): ncverilog ahb_pixel_memory.sv
s27(04Sep2020:01:17:43): ncverilog ahb_pixel_memory.sv
s28(04Sep2020:01:19:10): ncverilog ahb_pixel_memory.sv
s29(04Sep2020:01:19:36): ncverilog ahb_pixel_memory.sv
s30(04Sep2020:01:21:33): ncverilog ahb_pixel_memory.sv
s31(04Sep2020:01:22:00): ncverilog ahb_pixel_memory.sv
s32(04Sep2020:01:23:20): ncverilog ahb_pixel_memory.sv
s33(04Sep2020:01:37:51): ncverilog ahb_pixel_memory.sv
s34(04Sep2020:01:40:22): ncverilog ahb_pixel_memory.sv
s35(04Sep2020:01:40:40): ncverilog ahb_pixel_memory.sv
s36(04Sep2020:15:55:13): ncverilog ahb_pixel_memory.sv
s37(04Sep2020:18:15:53): ncverilog ahb_pixel_memory.sv
s38(04Sep2020:18:21:41): ncverilog ahb_pixel_memory.sv
s39(04Sep2020:18:24:18): ncverilog ahb_pixel_memory.sv
s40(04Sep2020:18:29:56): ncverilog ahb_pixel_memory.sv
s41(05Sep2020:13:36:13): ncverilog ahb_pixel_memory.sv
s42(05Sep2020:13:55:51): ncverilog ahb_pixel_memory.sv
s43(05Sep2020:14:01:37): ncverilog ahb_out.sv
s44(05Sep2020:14:05:23): ncverilog arm_sco.sv
s45(05Sep2020:14:05:30): ncverilog arm_soc.sv
s46(05Sep2020:14:14:09): ncverilog arm_soc.sv
s47(05Sep2020:14:17:15): ncverilog arm_soc.sv
s48(05Sep2020:17:28:08): ncverilog ahb_out.sv
s49(05Sep2020:18:07:43): ncverilog ahb_pixel_memory.sv
s50(05Sep2020:18:08:45): ncverilog ahb_pixel_memory.sv
s51(05Sep2020:18:09:33): ncverilog ahb_pixel_memory.sv
s52(05Sep2020:21:00:06): ncverilog ahb_pixel_memory.sv
s53(05Sep2020:21:00:30): ncverilog ahb_pixel_memory.sv
s54(05Sep2020:21:05:51): ncverilog ahb_pixel_memory.sv
s55(05Sep2020:21:07:01): ncverilog arm_soc.sv
s56(05Sep2020:21:07:28): ncverilog arm_soc.sv
s57(05Sep2020:21:07:59): ncverilog arm_soc.sv
s58(05Sep2020:21:08:33): ncverilog CORTEXM0DS.sv
s59(05Sep2020:21:13:36): ncverilog ahb_pixel_memory.sv
s60(05Sep2020:21:13:58): ncverilog ahb_pixel_memory.sv
s61(08Sep2020:11:25:04): ncverilog ahb_pixel_memory.sv
s62(10Sep2020:18:42:30): ncverilog triangle.sv
s63(10Sep2020:18:43:02): ncverilog triangle.sv
s64(12Sep2020:14:37:11): ncverilog ahb_pixel_memory.sv
s65(12Sep2020:14:38:12): ncverilog ahb_pixel_memory.sv
s66(12Sep2020:14:38:50): ncverilog ahb_pixel_memory.sv
s67(12Sep2020:14:39:26): ncverilog ahb_pixel_memory.sv
s68(12Sep2020:14:39:40): ncverilog arm_soc.sv
s69(13Sep2020:14:50:20): ncverilog ahb_pixel_memory.sv
s70(14Sep2020:12:36:10): ncverilog ahb_pixel_memory.sv
s71(14Sep2020:12:37:08): ncverilog ahb_pixel_memory.sv
s72(14Sep2020:13:30:23): ncverilog ahb_pixel_memory.sv
s73(14Sep2020:13:34:14): ncverilog ahb_pixel_memory.sv
s74(14Sep2020:13:37:40): ncverilog ahb_pixel_memory.sv
s75(14Sep2020:16:17:26): ncverilog ahb_pixel_memory.sv
s76(14Sep2020:22:05:49): ncverilog ahb_pixel_memory.sv
s77(15Sep2020:11:21:25): ncverilog ahb_pixel_memory.sv
s78(17Sep2020:16:56:12): ncverilog razzle.sv
s79(17Sep2020:16:57:03): ncverilog razzle.sv
s80(29Sep2020:11:27:22): ncverilog ahb_pixel_memory.sv
behavioural/ncverilog.log deleted 100644 → 0
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ncverilog(64): 15.20-s058: (c) Copyright 1995-2018 Cadence Design Systems, Inc.
TOOL: ncverilog 15.20-s058: Started on Sep 29, 2020 at 11:27:22 BST
ncverilog
ahb_pixel_memory.sv
file: ahb_pixel_memory.sv
module worklib.ahb_pixel_memory:sv
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.ahb_pixel_memory:sv <0x196eaf8a>
streams: 0, words: 0
Building instance specific data structures.
Loading native compiled code: .................... Done
Design hierarchy summary:
Instances Unique
Modules: 1 1
Registers: 6 6
Scalar wires: 1 -
Vectored wires: 1 -
Always blocks: 4 4
Initial blocks: 1 1
Cont. assignments: 0 2
Simulation timescale: 100ps
Writing initial simulation snapshot: worklib.ahb_pixel_memory:sv
Loading snapshot worklib.ahb_pixel_memory:sv .................... Done
ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
ncsim> source /eda/cadence/incisiv/tools/inca/files/ncsimrc
ncsim> run
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
TOOL: ncverilog 15.20-s058: Exiting on Sep 29, 2020 at 11:27:23 BST (total: 00:00:01)
behavioural/new file deleted 100644 → 0
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module raster ( input logic CLOCK_50,
input logic [3:0] KEY,
input logic pixel,
output logic [7:0] VGA_R,VGA_G,VGA_B,
output logic [9:0] pixel_x,
output logic [8:0] pixel_y ,
output logic VGA_HS,VGA_VS, VGA_CLK, VGA_BLANK_N);
behavioural/nexys4_wrapper.sv deleted 100644 → 0
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// Example code for an M0 AHBLite System
// Iain McNally
// ECS, University of Soutampton
//
// This module is a wrapper allowing the system to be used on the Nexsys 4 FPGA board
//
module nexys4_wrapper(
input Clock, nReset,
input [15:0] Switches,
input [1:0] Buttons, // nexys4 buttons are active high
output [15:0] DataOut,
output DataValid, DataInvalid,
output Status_Green, Status_Red
);
timeunit 1ns;
timeprecision 100ps;
localparam heartbeat_count_msb = 26;
localparam heartbeat_dimmer_msb = 5;
wire HCLK, HRESETn, LOCKUP;
arm_soc soc_inst(.HCLK, .HRESETn, .DataOut, .DataValid, .Switches, .Buttons, .LOCKUP);
assign DataInvalid = ! DataValid;
// Drive HRESETn directly from active low CPU RESET button
assign HRESETn = nReset;
// Drive HCLK from 50MHz signal derived from 100MHz Nexys4 board clock
logic Clock50;
always_ff @(posedge Clock, negedge nReset )
if ( ! nReset )
Clock50 <= 0;
else
Clock50 <= ! Clock50;
assign HCLK = Clock50;
// This code gives us a heartbeat signal on the RGB LED
//
// The LED is:
// steady orange - at reset,
// steady red - in the event of ARM M0 "lockup" and
// pulsing green - under normal operation
//
logic running, heartbeat;
logic [heartbeat_count_msb:0] tick_count;
always_ff @(posedge Clock, negedge nReset )
if ( ! nReset )
begin
running <= 0;
heartbeat <= 0;
tick_count <= 0;
end
else
begin
running <= 1;
heartbeat = tick_count[heartbeat_count_msb] && tick_count[heartbeat_count_msb-2] && (&tick_count[heartbeat_dimmer_msb:0]);
tick_count <= tick_count + 1;
end
// Single LED with two colours to indicate system status
assign Status_Green = !running || ( heartbeat && !LOCKUP );
assign Status_Red = !running || LOCKUP;
endmodule
behavioural/raster.sv deleted 100644 → 0
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module raster ( input logic CLOCK_50,
input logic pixel,
output logic [7:0] VGA_R,VGA_G,VGA_B,
output logic [9:0] pixel_x,
output logic [8:0] pixel_y ,
output logic VGA_HS,VGA_VS, VGA_CLK, VGA_BLANK_N);
behavioural/razzle.sv.bak deleted 100644 → 0
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// Description:
// This code generates a VGA output for ARM SoC based
// on razzle code modified by Iain Mcnally <ECS, University of Soutampton>
// Maintainer: Karthik Sathyanarayanan <ks6n19@soton.ac.uk>
// Revision : $Revision$
module razzle (
input logic CLOCK_50,
input logic [3:0] KEY,
input logic [9:0] pixel,
output logic [7:0] VGA_R,VGA_G,VGA_B,
output logic [9:0] pixel_x,
output logic [8:0] pixel_y ,
output logic VGA_HS,VGA_VS, VGA_CLK, VGA_BLANK_N);
// Video Display Signals
logic [10:0] H_count,V_count;
logic Red_Data;
logic video_on, video_on_H, video_on_V, clock_enable;
timeunit 1ns;
timeprecision 100ps;
// Map internal signals to external busses
logic nReset;
logic Red,Green,Blue;
assign nReset=KEY[2]; // Keys are active low?
assign VGA_R = Red ? 255 : 0;
assign VGA_G = Green ? 255 : 0;
assign VGA_B = Blue ? 255 : 0;
assign VGA_CLK = clock_enable;
assign VGA_BLANK_N = video_on;
// Colors for pixel data on video signal
assign Red_Data = pixel ;
assign Green_Data = 0;
assign Blue_Data = 0;
// turn off color (black) at screen edges and during retrace with video_on
assign Red = Red_Data && video_on;
assign Green = Green_Data && video_on;
assign Blue = Blue_Data && video_on;
// video_on turns off pixel color data when not in the pixel view area
assign video_on = video_on_H && video_on_V;
assign pixel_x = H_count ;
assign pixel_y = V_count ;
// code for pixel as colour output
always @(posedge CLOCK_50 , negedge nReset )
if (! nReset)
begin
pixel = '0;
end
else
begin : pixel
if (video_on)
pixel = '1;
end : pixel
// Generate Horizontal and Vertical Timing Signals for Video Signal
//VIDEO_DISPLAY
always @(posedge CLOCK_50, negedge nReset)
if ( ! nReset)
begin
clock_enable = 0;
H_count = 0;
V_count = 0;
video_on_H = 0;
video_on_V = 0;
end
else
begin : VIDEO_DISPLAY
// Clock enable used for a 24Mhz video clock rate
// 640 by 480 display mode needs close to a 25Mhz pixel clock
// 24Mhz should work on most new monitors
clock_enable = ! clock_enable;
// H_count counts pixels (640 + extra time for sync signals)
//
// <-Clock out RGB Pixel Row Data -> <-H Sync->
// ------------------------------------__________--------
// 0 640 659 755 799
//
if ( clock_enable )
begin
if (H_count >= 799)
H_count = 0;
else
H_count = H_count + 1;
// Generate Horizontal Sync Signal
if ((H_count <= 755) && (H_count >= 659))
VGA_HS = 0;
else
VGA_HS = 1;
// V_count counts rows of pixels (480 + extra time for sync signals)
//
// <---- 480 Horizontal Syncs (pixel rows) --> ->V Sync<-
// -----------------------------------------------_______------------
// 0 480 493-494 524
//
if ((V_count >= 524) && (H_count >= 699))
V_count = 0;
else if (H_count == 699)
V_count = V_count + 1;
// Generate Vertical Sync Signal
if ((V_count <= 494) && (V_count >= 493))
VGA_VS = 0;
else
VGA_VS = 1;
// Generate Video on Screen Signals for Pixel Data
if (H_count <= 639)
video_on_H = 1;
else
video_on_H = 0;
if (V_count <= 479)
video_on_V = 1;
else
video_on_V = 0;
end
end : VIDEO_DISPLAY
endmodule
behavioural/triangle.sv deleted 100644 → 0
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View file @ 22cb7ecb
module Triangle (
input logic clk,
input logic nReset,
input logic [27:0]bv1, bv2, bv3,
input logic [27:0]tv1, tv2, tv3,
input logic [3:0] BCO, TCO,
output logic [10:0] x, y,
output logic [3:0] TRIcolour,
output logic request);
logic [10:0] ycurrent, xcurrent, bi, ti, j;
logic [10:0] bx1, by1, bx2, by2, bx3, by3, btx2, bmax, top;
logic [10:0] tx1, ty1, tx2, ty2, tx3, ty3, ttx2, tmax, bot;
logic bm, bn, tm, tn;
logic [31:0] bslope12, bslope13, tslope13, tslope23, b12, b13, t13, t23,d;
logic [3:0] bco, tco;
assign bx1 = bv1%640;
assign by1 = bv1/640;
assign bx2 = bv2%640;
assign by2 = bv2/640;
assign bx3 = bv3%640;
assign by3 = bv3/640;
assign tx1 = tv1%640;
assign ty1 = tv1/640;
assign tx2 = tv2%640;
assign ty2 = tv2/640;
assign tx3 = tv3%640;
assign ty3 = tv3/640;
//get value of slopes
always_comb
begin
if(bx2>bx1)
begin
bslope12 = ((bx2-bx1)*10000)/(by2-by1);
bm = 1;
end
else
begin
bslope12 = ((bx1-bx2)*10000)/(by2-by1);
bm = 0;
end
if(bx3>bx1)
begin
bslope13 = ((bx3-bx1)*10000)/(by3-by1);
bn = 1;
end
else
begin
bslope13 = ((bx1-bx3)*10000)/(by3-by1);
bn = 0;
end
if(tx3>tx1)
begin
tslope13 = ((tx3-tx1)*10000)/(ty3-ty1);
tm = 1;
end
else
begin
tslope13 = ((tx1-tx3)*10000)/(ty3-ty1);
tm = 0;
end
if(tx3>tx2)
begin
tslope23 = ((tx3-tx2)*10000)/(ty3-ty2);
tn = 1;
end
else
begin
tslope23 = ((tx2-tx3)*10000)/(ty3-ty2);
tn = 0;
end
end
enum{idle, bprep, bdrawy, bdrawx, tprep, tdrawy, tdrawx}state;
always_ff @(posedge clk, negedge nReset)
if ( ! nReset)
begin
ycurrent <= 0;
xcurrent <= 0;
bi <= 0;
ti <= 0;
j <= 0;
d <= 0;
btx2 <= 0;
ttx2 <= 0;
request <= 0;
bco <= 0;
bmax <= 0;
state <= 0;
b12 <= 0;
b13 <= 0;
top <= 0;
ti <= 0;
tco <= 0;
tmax <= 0;
state <= 0;
t13 <= 0;
t23 <= 0;
bot <= 0;
TRIcolour <= 0;
end
else
begin : DRAW_BOTTOM_FLAT_TRIANGLE
case(state)
idle:begin
request <= 0;
if(by3 != 0)
state <= bprep;
else if (ty3 != 0)
state <= tprep;
end
bprep:begin
d <= 0;
bi <= by1;
bco <= BCO;
bmax <= by2;
state <= bdrawy;
b12 <= bslope12;
b13 <= bslope13;
top <= bx1;
end
bdrawy:begin
request <= 0;
ycurrent <= bi;
if(bm)
j <= top + (d*b12)/10000;
else
j <= top - (d*b12)/10000;
if(bn)
btx2 <= top + (d*b13)/10000;
else
btx2 <= top - (d*b13)/10000;
state <= bdrawx;
end
bdrawx:begin
xcurrent <= j;
TRIcolour <= bco;
request <= 1;
j = j+1;
if( j > btx2)
begin
bi <= bi+1;
if(bi< bmax)
begin
d = d+1;
state <= bdrawy;
end
else if (ty3 != 0)
state <= tprep;
else
state <= idle;
end
end
tprep:begin
request <= 0;
d <= 0;
ti <= ty3;
tco <= TCO;
tmax <= ty1;
state <= tdrawy;
t13 <= tslope13;
t23 <= tslope23;
bot <= tx3;
end
tdrawy:begin
request <= 0;
ycurrent <= ti;
if(tm)
j <= bot - (d*t13)/10000;
else
j <= bot + (d*t13)/10000;
if(tn)
ttx2 <= bot - (d*t23)/10000;
else
ttx2 <= bot + (d*t23)/10000;
state <= tdrawx;
end
tdrawx:begin
xcurrent <= j;
TRIcolour <= tco;
request <= 1;
j = j+1;
if( j > ttx2)
begin
ti <= ti-1;
if(ti> tmax)
begin
d = d+1;
state <= tdrawy;
end
else
begin
state <= idle;
end
end
end
endcase
end : DRAW_BOTTOM_FLAT_TRIANGLE
assign x = xcurrent;
assign y = ycurrent;
endmodule
constraints/DE0.qsf deleted 100644 → 0
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− 547
View file @ 22cb7ecb
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constraints/DE2.qsf deleted 100644 → 0
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View file @ 22cb7ecb
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constraints/Nexys4_Master.xdc deleted 100644 → 0
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− 492
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constraints/nexys4_wrapper.xdc deleted 100644 → 0
+ 0
− 132
View file @ 22cb7ecb
## This file is a general .xdc for the Nexys4 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ
set_property PACKAGE_PIN E3 [get_ports Clock]
set_property IOSTANDARD LVCMOS33 [get_ports Clock]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports Clock]
create_clock -period 20.000 -name ahb_clock -waveform {1.000 11.000} [get_nets Clock50]
## Buttons
set_property PACKAGE_PIN C12 [get_ports nReset]
set_property IOSTANDARD LVCMOS33 [get_ports nReset]
# This is the top button in the cluster of 5
set_property PACKAGE_PIN F15 [get_ports {Buttons[0]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Buttons[0]' has been applied to the port object 'Buttons[0]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Buttons[0]}]
# This is the bottom button in the cluster of 5
set_property PACKAGE_PIN V10 [get_ports {Buttons[1]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Buttons[1]' has been applied to the port object 'Buttons[1]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Buttons[1]}]
## Switches
set_property PACKAGE_PIN U9 [get_ports {Switches[0]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[0]' has been applied to the port object 'Switches[0]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[0]}]
set_property PACKAGE_PIN U8 [get_ports {Switches[1]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[1]' has been applied to the port object 'Switches[1]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[1]}]
set_property PACKAGE_PIN R7 [get_ports {Switches[2]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[2]' has been applied to the port object 'Switches[2]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[2]}]
set_property PACKAGE_PIN R6 [get_ports {Switches[3]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[3]' has been applied to the port object 'Switches[3]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[3]}]
set_property PACKAGE_PIN R5 [get_ports {Switches[4]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[4]' has been applied to the port object 'Switches[4]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[4]}]
set_property PACKAGE_PIN V7 [get_ports {Switches[5]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[5]' has been applied to the port object 'Switches[5]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[5]}]
set_property PACKAGE_PIN V6 [get_ports {Switches[6]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[6]' has been applied to the port object 'Switches[6]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[6]}]
set_property PACKAGE_PIN V5 [get_ports {Switches[7]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[7]' has been applied to the port object 'Switches[7]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[7]}]
set_property PACKAGE_PIN U4 [get_ports {Switches[8]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[8]' has been applied to the port object 'Switches[8]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[8]}]
set_property PACKAGE_PIN V2 [get_ports {Switches[9]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[9]' has been applied to the port object 'Switches[9]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[9]}]
set_property PACKAGE_PIN U2 [get_ports {Switches[10]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[10]' has been applied to the port object 'Switches[10]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[10]}]
set_property PACKAGE_PIN T3 [get_ports {Switches[11]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[11]' has been applied to the port object 'Switches[11]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[11]}]
set_property PACKAGE_PIN T1 [get_ports {Switches[12]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[12]' has been applied to the port object 'Switches[12]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[12]}]
set_property PACKAGE_PIN R3 [get_ports {Switches[13]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[13]' has been applied to the port object 'Switches[13]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[13]}]
set_property PACKAGE_PIN P3 [get_ports {Switches[14]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[14]' has been applied to the port object 'Switches[14]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[14]}]
set_property PACKAGE_PIN P4 [get_ports {Switches[15]}]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[15]' has been applied to the port object 'Switches[15]'.
set_property IOSTANDARD LVCMOS33 [get_ports {Switches[15]}]
## LEDs
##Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0
set_property PACKAGE_PIN T8 [get_ports {DataOut[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[0]}]
##Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1
set_property PACKAGE_PIN V9 [get_ports {DataOut[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[1]}]
##Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2
set_property PACKAGE_PIN R8 [get_ports {DataOut[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[2]}]
##Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3
set_property PACKAGE_PIN T6 [get_ports {DataOut[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[3]}]
##Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4
set_property PACKAGE_PIN T5 [get_ports {DataOut[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[4]}]
##Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5
set_property PACKAGE_PIN T4 [get_ports {DataOut[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[5]}]
##Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6
set_property PACKAGE_PIN U7 [get_ports {DataOut[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[6]}]
##Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7
set_property PACKAGE_PIN U6 [get_ports {DataOut[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[7]}]
set_property PACKAGE_PIN V4 [get_ports {DataOut[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[8]}]
set_property PACKAGE_PIN U3 [get_ports {DataOut[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[9]}]
set_property PACKAGE_PIN V1 [get_ports {DataOut[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[10]}]
set_property PACKAGE_PIN R1 [get_ports {DataOut[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[11]}]
set_property PACKAGE_PIN P5 [get_ports {DataOut[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[12]}]
set_property PACKAGE_PIN U1 [get_ports {DataOut[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[13]}]
set_property PACKAGE_PIN R2 [get_ports {DataOut[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[14]}]
set_property PACKAGE_PIN P2 [get_ports {DataOut[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[15]}]
# LD16 RGB LED Signals
set_property PACKAGE_PIN K5 [get_ports Status_Red]
set_property IOSTANDARD LVCMOS33 [get_ports Status_Red]
set_property PACKAGE_PIN F13 [get_ports Status_Green]
set_property IOSTANDARD LVCMOS33 [get_ports Status_Green]
# LD17 RGB LED Signals
set_property PACKAGE_PIN K6 [get_ports DataInvalid]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'DataInvalid' has been applied to the port object 'DataInvalid'.
set_property IOSTANDARD LVCMOS33 [get_ports DataInvalid]
set_property PACKAGE_PIN H6 [get_ports DataValid]
# The conversion of 'IOSTANDARD' constraint on 'net' object 'DataValid' has been applied to the port object 'DataValid'.
set_property IOSTANDARD LVCMOS33 [get_ports DataValid]
software/code/main.c
+ 2
− 2
View file @ c184cbce
......@@ -76,9 +76,9 @@ int main(void) {
int y1 = 0 ;
int x2 = 50;
int y2 = 30;
int y2 = 300;
int x3 = 50;
int x3 = 500;
int y3 = 70;
while(1) {
......
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