diff --git a/behavioural/ahb_pixel_memory.sv.bak b/behavioural/ahb_pixel_memory.sv.bak
deleted file mode 100755
index 80ac71446c5b615fdb7f715fe4e53eae7e9dc37d..0000000000000000000000000000000000000000
--- a/behavioural/ahb_pixel_memory.sv.bak
+++ /dev/null
@@ -1,123 +0,0 @@
-// Example code for an M0 AHBLite System
-// Iain McNally
-// ECS, University of Soutampton
-//
-// This module is an AHB-Lite Slave containing a RAM
-// Since this loads a program it is for FPGA use only
-//
-// Number of addressable locations : 307200
-// Size of each addressable location : bits_per_pixel bits
-// Supported transfer sizes : Word
-// Alignment of base address : Word aligned
-//
-
-// Memory is synchronous which should suit block memory types
-// Read takes 1 cycle
-// Write takes 2 cycles (single wait state)
-//
-// Note this is not the most efficient design but works with
-// Xilinx and Altera(Intel) FPGAs
-//
-
-
-module ahb_pixel_memory #(
-)(
- //AHBLITE INTERFACE
-
- //Slave Select Signal
- input HSEL,
- //Global Signals
- input HCLK,
- input HRESETn,
- //Address, Control & Write Data
- input HREADY,
- input [31:0] HADDR,
- input [1:0] HTRANS,
- input HWRITE,
- input [2:0] HSIZE,
- input [31:0] HWDATA,
-
- // non ahb input
- input [9:0] pixel_x ,
- input [8:0] pixel_y ,
- // Transfer Response & Read Data
- output HREADYOUT,
- output logic [31:0] HRDATA,
-
- //Non-AHB Signals
- output logic pixel
-
-
-);
-
-timeunit 1ns;
-timeprecision 100ps;
-
-localparam No_Transfer = 2'b0;
-
-//memory
- logic [7:0] memory [0:307199] ;
-
-// other declarations
- logic write_enable, read_enable;
- logic [18:0] word_address;
- logic [18:0] pixel_address ;
-
-
-//Generate the control signals here:
-always_ff @(posedge HCLK, negedge HRESETn)
- if (! HRESETn )
- begin
- write_enable <= '0;
- read_enable <= '0;
- word_address <= '0;
- end
- else if ( HREADY && HSEL && (HTRANS != No_Transfer) )
- begin
- write_enable <= HWRITE;
- read_enable <= ! HWRITE;
- word_address <= HADDR[20:2];
- end
- else
- begin
- write_enable <= '0;
- read_enable <= '0;
- word_address <= '0;
- end
-
-
-
- //memory
- always_ff @(posedge HCLK)
- begin
- if( write_enable )
- memory[word_address] <= HWDATA ;
- end
-
- always_comb
- pixel_address = (pixel_y * 640) + pixel_x ;
-
-
-
- assign pixel = memory[pixel_address] ;
-
- assign HRDATA = read_enable ? memory[word_address] : '0 ;
-
- /*
- assign bv1 = memory[0] ;
- assign bv2 = memory[1] ;
- assign bv3 = memory[2] ;
- assign tv1 = memory[3] ;
- assign tv2 = memory[4] ;
- assign tv3 = memory[5] ;
- assign BCO = memory[6] ;
- assign TCO = memory[7] ;
- */
-
-
-//Transfer Response
- assign HREADYOUT = '1; //Single Cycle Wait State for Write
-
-
-endmodule
-
diff --git a/behavioural/de0_wrapper.sv b/behavioural/de0_wrapper.sv
deleted file mode 100644
index 2130b9cb10aa8d488fd411f363c9e8ab3726ba72..0000000000000000000000000000000000000000
--- a/behavioural/de0_wrapper.sv
+++ /dev/null
@@ -1,87 +0,0 @@
-// Example code for an M0 AHBLite System
-// Iain McNally
-// ECS, University of Soutampton
-//
-// This module is a wrapper allowing the system to be used on the DE0 FPGA board
-//
-
-module de0_wrapper(
-
- input CLOCK_50,
-
- input [9:0] SW,
- input [2:0] KEY, // de0 keys are active low
-
- output [9:0] LEDG,
- output [7:0] HEX0,
- output [7:0] HEX1,
- output [7:0] HEX2,
- output [7:0] HEX3
-
-);
-
-timeunit 1ns;
-timeprecision 100ps;
-
- localparam heartbeat_count_msb = 25;
-
-
- wire HCLK, HRESETn, LOCKUP, DataValid;
- wire [1:0] Buttons;
- wire [15:0] Switches;
-
- assign Switches = { 6'd0, SW }; // DE0 has just 10 switches
-
- assign Buttons = ~KEY[1:0];
-
- arm_soc soc_inst(.HCLK, .HRESETn, .DataOut(LEDG), .DataValid, .Switches, .Buttons, .LOCKUP);
-
- assign DataInvalid = ! DataValid;
-
- // Drive HRESETn directly from active low CPU KEY[2] button
- assign HRESETn = KEY[2];
-
- // Drive HCLK from 50MHz de0 board clock
- assign HCLK = CLOCK_50;
-
-
-
- // This code gives us a heartbeat signal on the least significant
- // decimal point of the seven segment display
- //
- logic running, heartbeat;
- logic [heartbeat_count_msb:0] tick_count;
- always_ff @(posedge CLOCK_50, negedge HRESETn )
- if ( ! HRESETn )
- begin
- running <= 0;
- heartbeat <= 0;
- tick_count <= 0;
- end
- else
- begin
- running <= 1;
- heartbeat = tick_count[heartbeat_count_msb] && tick_count[heartbeat_count_msb-2];
- tick_count <= tick_count + 1;
- end
-
- // seven segment display to indicate system status
- assign HEX0 = ~{heartbeat, 1'b0,
- !DataValid&&!LOCKUP,
- !DataValid&&!LOCKUP,
- !DataValid&&!LOCKUP,
- !LOCKUP,
- !LOCKUP,
- !DataValid&&!LOCKUP };
-
- // HEX1 is off
- assign HEX1 = ~{8'b0000_0000 };
-
- // running shows as r on HEX2
- assign HEX2 = ~{2'b00,running,1'b0,running, 4'b000 };
-
- // LOCKUP shows as L on HEX3
- assign HEX3 = ~{2'b00,LOCKUP,LOCKUP,LOCKUP, 3'b000 };
-
-
-endmodule
diff --git a/behavioural/de1_soc_wrapper.sv.bak b/behavioural/de1_soc_wrapper.sv.bak
deleted file mode 100644
index 030646a45acc58ca4ac31e8df41ce0bfc7e63da8..0000000000000000000000000000000000000000
--- a/behavioural/de1_soc_wrapper.sv.bak
+++ /dev/null
@@ -1,93 +0,0 @@
-// Example code for an M0 AHBLite System
-// Iain McNally
-// ECS, University of Soutampton
-//
-// This module is a wrapper allowing the system to be used on the DE1-SoC FPGA board
-//
-
-module de1_soc_wrapper(
-
- input CLOCK_50,
-
- input [9:0] SW,
- input [3:0] KEY, // de1 keys are active low
-
- output [9:0] LEDR,
- output [6:0] HEX0,
- output [6:0] HEX1,
- output [6:0] HEX2,
- output [6:0] HEX3,
- output logic [7:0] VGA_R,VGA_G,VGA_B,
- output logic VGA_HS,VGA_VS, VGA_CLK, VGA_BLANK_N
-
-
-);
-
-timeunit 1ns;
-timeprecision 100ps;
-
- localparam heartbeat_count_msb = 25;
-
-
- wire HCLK, HRESETn, LOCKUP;
- wire [1:0] Buttons;
- wire [15:0] Switches;
- logic pixel ;
- logic [9:0] pixel_x ;
- logic [8:0] pixel_y ;
- assign Switches = { 6'd0, SW }; // DE1-SoC has just 10 switches
-
- assign Buttons = ~KEY[1:0];
-
- arm_soc soc_inst(.HCLK, .HRESETn, .Switches,.pixel, .pixel_x, .pixel_y .Buttons, .LOCKUP);
-
- razzle raz_inst (
- .CLOCK_50(CLOCK_50), .KEY(KEY), .pixel_x(pixel_x), .pixel_y(pixel_y), .pixel(pixel),
- .VGA_R(VGA_R),.VGA_G(VGA_G),.VGA_B(VGA_B),
- .VGA_HS(VGA_HS),.VGA_VS(VGA_VS), .VGA_CLK(VGA_CLK),
- .VGA_BLANK_N(VGA_BLANK_N)
- );
-
-
- // Drive HRESETn directly from active low CPU KEY[2] button
- assign HRESETn = KEY[2];
-
- // Drive HCLK from 50MHz de0 board clock
- assign HCLK = CLOCK_50;
-
-
-
- // This code gives us a heartbeat signal
- //
- logic running, heartbeat;
- logic [heartbeat_count_msb:0] tick_count;
- always_ff @(posedge CLOCK_50, negedge HRESETn )
- if ( ! HRESETn )
- begin
- running <= 0;
- heartbeat <= 0;
- tick_count <= 0;
- end
- else
- begin
- running <= 1;
- heartbeat = tick_count[heartbeat_count_msb] && tick_count[heartbeat_count_msb-2];
- tick_count <= tick_count + 1;
- end
-
- // seven segment display to indicate system status
-
- // HEX0 is heartbeat
- assign HEX0 = (heartbeat) ? 7'b0100011 : '1;
-
- // HEX1 is DataValid
- assign HEX1 = ~{!LOCKUP};
-
- // running shows as r on HEX2
- assign HEX2 = ~{1'b0,running,1'b0,running, 4'b000 };
-
- // LOCKUP shows as L on HEX3
- assign HEX3 = ~{1'b0,LOCKUP,LOCKUP,LOCKUP, 3'b000 };
-
-
-endmodule
diff --git a/behavioural/de2_wrapper.sv b/behavioural/de2_wrapper.sv
deleted file mode 100644
index d6dd7f6f3646d0d56571b27ff7b053fd4542fe7e..0000000000000000000000000000000000000000
--- a/behavioural/de2_wrapper.sv
+++ /dev/null
@@ -1,85 +0,0 @@
-// Example code for an M0 AHBLite System
-// Iain McNally
-// ECS, University of Soutampton
-//
-// This module is a wrapper allowing the system to be used on the DE1-SoC FPGA board
-//
-
-module de2_wrapper(
-
- input CLOCK_50,
-
- input [15:0] SW,
- input [2:0] KEY, // DE2 keys are active low
-
- output [15:0] LEDR,
- output [6:0] HEX0,
- output [6:0] HEX1,
- output [6:0] HEX2,
- output [6:0] HEX3
-
-);
-
-timeunit 1ns;
-timeprecision 100ps;
-
- localparam heartbeat_count_msb = 25;
-
-
- wire HCLK, HRESETn, LOCKUP, DataValid;
- wire [1:0] Buttons;
- wire [15:0] Switches;
-
- assign Switches = SW; // DE2 has nore than 16 switches
-
- assign Buttons = ~KEY[1:0];
-
- arm_soc soc_inst(.HCLK, .HRESETn, .DataOut(LEDR), .DataValid, .Switches, .Buttons, .LOCKUP);
-
- // Drive HRESETn directly from active low CPU KEY[2] button
- assign HRESETn = KEY[2];
-
- // Drive HCLK from 50MHz de0 board clock
- assign HCLK = CLOCK_50;
-
-
-
- // This code gives us a heartbeat signal
- //
- logic running, heartbeat;
- logic [heartbeat_count_msb:0] tick_count;
- always_ff @(posedge CLOCK_50, negedge HRESETn )
- if ( ! HRESETn )
- begin
- running <= 0;
- heartbeat <= 0;
- tick_count <= 0;
- end
- else
- begin
- running <= 1;
- heartbeat = tick_count[heartbeat_count_msb] && tick_count[heartbeat_count_msb-2];
- tick_count <= tick_count + 1;
- end
-
- // seven segment display to indicate system status
-
- // HEX0 is heartbeat
- assign HEX0 = (heartbeat) ? 7'b0100011 : '1;
-
- // HEX1 is DataValid
- assign HEX1 = ~{!DataValid&&!LOCKUP,
- !DataValid&&!LOCKUP,
- !DataValid&&!LOCKUP,
- !LOCKUP,
- !LOCKUP,
- !DataValid&&!LOCKUP };
-
- // running shows as r on HEX2
- assign HEX2 = ~{1'b0,running,1'b0,running, 4'b000 };
-
- // LOCKUP shows as L on HEX3
- assign HEX3 = ~{1'b0,LOCKUP,LOCKUP,LOCKUP, 3'b000 };
-
-
-endmodule
diff --git a/behavioural/ncverilog.history b/behavioural/ncverilog.history
deleted file mode 100644
index e8f1baf2d379e268da2dbaaa3b12221c781d9a29..0000000000000000000000000000000000000000
--- a/behavioural/ncverilog.history
+++ /dev/null
@@ -1,80 +0,0 @@
-s1(03Sep2020:15:32:34): ncverilog ahb_pixel_memory.sv
-s2(03Sep2020:16:20:52): ncverilog ahb_pixel_memory.sv
-s3(03Sep2020:16:22:50): ncverilog ahb_pixel_memory.sv
-s4(03Sep2020:16:24:06): ncverilog ahb_pixel_memory.sv
-s5(03Sep2020:16:24:54): ncverilog ahb_pixel_memory.sv
-s6(03Sep2020:16:27:48): ncverilog ahb_pixel_memory.sv
-s7(03Sep2020:16:28:18): ncverilog ahb_pixel_memory.sv
-s8(03Sep2020:16:30:37): ncverilog ahb_pixel_memory.sv
-s9(03Sep2020:16:33:18): ncverilog ahb_pixel_memory.sv
-s10(03Sep2020:16:33:55): ncverilog ahb_pixel_memory.sv
-s11(03Sep2020:16:34:17): ncverilog ahb_pixel_memory.sv
-s12(03Sep2020:16:39:58): ncverilog ahb_pixel_memory.sv
-s13(03Sep2020:16:40:56): ncverilog ahb_pixel_memory.sv
-s14(03Sep2020:16:44:26): ncverilog ahb_pixel_memory.sv
-s15(03Sep2020:21:16:10): ncverilog ahb_pixel_memory.sv
-s16(03Sep2020:21:16:58): ncverilog ahb_pixel_memory.sv
-s17(03Sep2020:21:17:06): ncverilog ahb_pixel_memory.sv
-s18(03Sep2020:21:19:03): ncverilog ahb_pixel_memory.sv
-s19(03Sep2020:21:22:12): ncverilog ahb_pixel_memory.sv
-s20(03Sep2020:21:24:32): ncverilog ahb_pixel_memory.sv
-s21(03Sep2020:21:26:50): ncverilog ahb_pixel_memory.sv
-s22(03Sep2020:21:28:09): ncverilog ahb_pixel_memory.sv
-s23(03Sep2020:21:32:21): ncverilog ahb_pixel_memory.sv
-s24(03Sep2020:22:38:44): ncverilog ahb_pixel_memory.sv
-s25(03Sep2020:22:39:25): ncverilog ahb_pixel_memory.sv
-s26(03Sep2020:22:40:54): ncverilog ahb_pixel_memory.sv
-s27(04Sep2020:01:17:43): ncverilog ahb_pixel_memory.sv
-s28(04Sep2020:01:19:10): ncverilog ahb_pixel_memory.sv
-s29(04Sep2020:01:19:36): ncverilog ahb_pixel_memory.sv
-s30(04Sep2020:01:21:33): ncverilog ahb_pixel_memory.sv
-s31(04Sep2020:01:22:00): ncverilog ahb_pixel_memory.sv
-s32(04Sep2020:01:23:20): ncverilog ahb_pixel_memory.sv
-s33(04Sep2020:01:37:51): ncverilog ahb_pixel_memory.sv
-s34(04Sep2020:01:40:22): ncverilog ahb_pixel_memory.sv
-s35(04Sep2020:01:40:40): ncverilog ahb_pixel_memory.sv
-s36(04Sep2020:15:55:13): ncverilog ahb_pixel_memory.sv
-s37(04Sep2020:18:15:53): ncverilog ahb_pixel_memory.sv
-s38(04Sep2020:18:21:41): ncverilog ahb_pixel_memory.sv
-s39(04Sep2020:18:24:18): ncverilog ahb_pixel_memory.sv
-s40(04Sep2020:18:29:56): ncverilog ahb_pixel_memory.sv
-s41(05Sep2020:13:36:13): ncverilog ahb_pixel_memory.sv
-s42(05Sep2020:13:55:51): ncverilog ahb_pixel_memory.sv
-s43(05Sep2020:14:01:37): ncverilog ahb_out.sv
-s44(05Sep2020:14:05:23): ncverilog arm_sco.sv
-s45(05Sep2020:14:05:30): ncverilog arm_soc.sv
-s46(05Sep2020:14:14:09): ncverilog arm_soc.sv
-s47(05Sep2020:14:17:15): ncverilog arm_soc.sv
-s48(05Sep2020:17:28:08): ncverilog ahb_out.sv
-s49(05Sep2020:18:07:43): ncverilog ahb_pixel_memory.sv
-s50(05Sep2020:18:08:45): ncverilog ahb_pixel_memory.sv
-s51(05Sep2020:18:09:33): ncverilog ahb_pixel_memory.sv
-s52(05Sep2020:21:00:06): ncverilog ahb_pixel_memory.sv
-s53(05Sep2020:21:00:30): ncverilog ahb_pixel_memory.sv
-s54(05Sep2020:21:05:51): ncverilog ahb_pixel_memory.sv
-s55(05Sep2020:21:07:01): ncverilog arm_soc.sv
-s56(05Sep2020:21:07:28): ncverilog arm_soc.sv
-s57(05Sep2020:21:07:59): ncverilog arm_soc.sv
-s58(05Sep2020:21:08:33): ncverilog CORTEXM0DS.sv
-s59(05Sep2020:21:13:36): ncverilog ahb_pixel_memory.sv
-s60(05Sep2020:21:13:58): ncverilog ahb_pixel_memory.sv
-s61(08Sep2020:11:25:04): ncverilog ahb_pixel_memory.sv
-s62(10Sep2020:18:42:30): ncverilog triangle.sv
-s63(10Sep2020:18:43:02): ncverilog triangle.sv
-s64(12Sep2020:14:37:11): ncverilog ahb_pixel_memory.sv
-s65(12Sep2020:14:38:12): ncverilog ahb_pixel_memory.sv
-s66(12Sep2020:14:38:50): ncverilog ahb_pixel_memory.sv
-s67(12Sep2020:14:39:26): ncverilog ahb_pixel_memory.sv
-s68(12Sep2020:14:39:40): ncverilog arm_soc.sv
-s69(13Sep2020:14:50:20): ncverilog ahb_pixel_memory.sv
-s70(14Sep2020:12:36:10): ncverilog ahb_pixel_memory.sv
-s71(14Sep2020:12:37:08): ncverilog ahb_pixel_memory.sv
-s72(14Sep2020:13:30:23): ncverilog ahb_pixel_memory.sv
-s73(14Sep2020:13:34:14): ncverilog ahb_pixel_memory.sv
-s74(14Sep2020:13:37:40): ncverilog ahb_pixel_memory.sv
-s75(14Sep2020:16:17:26): ncverilog ahb_pixel_memory.sv
-s76(14Sep2020:22:05:49): ncverilog ahb_pixel_memory.sv
-s77(15Sep2020:11:21:25): ncverilog ahb_pixel_memory.sv
-s78(17Sep2020:16:56:12): ncverilog razzle.sv
-s79(17Sep2020:16:57:03): ncverilog razzle.sv
-s80(29Sep2020:11:27:22): ncverilog ahb_pixel_memory.sv
diff --git a/behavioural/ncverilog.log b/behavioural/ncverilog.log
deleted file mode 100644
index ef1315fff30bf81dafd3f6b05c8e033b13dc6b3a..0000000000000000000000000000000000000000
--- a/behavioural/ncverilog.log
+++ /dev/null
@@ -1,34 +0,0 @@
-ncverilog(64): 15.20-s058: (c) Copyright 1995-2018 Cadence Design Systems, Inc.
-TOOL: ncverilog 15.20-s058: Started on Sep 29, 2020 at 11:27:22 BST
-ncverilog
- ahb_pixel_memory.sv
-file: ahb_pixel_memory.sv
- module worklib.ahb_pixel_memory:sv
- errors: 0, warnings: 0
- Caching library 'worklib' ....... Done
- Elaborating the design hierarchy:
-ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
- Building instance overlay tables: .................... Done
- Generating native compiled code:
- worklib.ahb_pixel_memory:sv <0x196eaf8a>
- streams: 0, words: 0
- Building instance specific data structures.
- Loading native compiled code: .................... Done
- Design hierarchy summary:
- Instances Unique
- Modules: 1 1
- Registers: 6 6
- Scalar wires: 1 -
- Vectored wires: 1 -
- Always blocks: 4 4
- Initial blocks: 1 1
- Cont. assignments: 0 2
- Simulation timescale: 100ps
- Writing initial simulation snapshot: worklib.ahb_pixel_memory:sv
-Loading snapshot worklib.ahb_pixel_memory:sv .................... Done
-ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
-ncsim> source /eda/cadence/incisiv/tools/inca/files/ncsimrc
-ncsim> run
-ncsim: *W,RNQUIE: Simulation is complete.
-ncsim> exit
-TOOL: ncverilog 15.20-s058: Exiting on Sep 29, 2020 at 11:27:23 BST (total: 00:00:01)
diff --git a/behavioural/new file b/behavioural/new file
deleted file mode 100644
index c15da53690895a994cbe3def855139c7af74a6b9..0000000000000000000000000000000000000000
--- a/behavioural/new file
+++ /dev/null
@@ -1,7 +0,0 @@
-module raster ( input logic CLOCK_50,
- input logic [3:0] KEY,
- input logic pixel,
- output logic [7:0] VGA_R,VGA_G,VGA_B,
- output logic [9:0] pixel_x,
- output logic [8:0] pixel_y ,
- output logic VGA_HS,VGA_VS, VGA_CLK, VGA_BLANK_N);
diff --git a/behavioural/nexys4_wrapper.sv b/behavioural/nexys4_wrapper.sv
deleted file mode 100644
index e9f4f76003b19d3aae946d35cbf928a748ee36a4..0000000000000000000000000000000000000000
--- a/behavioural/nexys4_wrapper.sv
+++ /dev/null
@@ -1,79 +0,0 @@
-// Example code for an M0 AHBLite System
-// Iain McNally
-// ECS, University of Soutampton
-//
-// This module is a wrapper allowing the system to be used on the Nexsys 4 FPGA board
-//
-
-module nexys4_wrapper(
-
- input Clock, nReset,
-
- input [15:0] Switches,
- input [1:0] Buttons, // nexys4 buttons are active high
-
- output [15:0] DataOut,
- output DataValid, DataInvalid,
- output Status_Green, Status_Red
-
-);
-
-timeunit 1ns;
-timeprecision 100ps;
-
- localparam heartbeat_count_msb = 26;
- localparam heartbeat_dimmer_msb = 5;
-
-
- wire HCLK, HRESETn, LOCKUP;
-
- arm_soc soc_inst(.HCLK, .HRESETn, .DataOut, .DataValid, .Switches, .Buttons, .LOCKUP);
-
- assign DataInvalid = ! DataValid;
-
- // Drive HRESETn directly from active low CPU RESET button
- assign HRESETn = nReset;
-
- // Drive HCLK from 50MHz signal derived from 100MHz Nexys4 board clock
- logic Clock50;
- always_ff @(posedge Clock, negedge nReset )
- if ( ! nReset )
- Clock50 <= 0;
- else
- Clock50 <= ! Clock50;
-
- assign HCLK = Clock50;
-
-
-
- // This code gives us a heartbeat signal on the RGB LED
- //
- // The LED is:
- // steady orange - at reset,
- // steady red - in the event of ARM M0 "lockup" and
- // pulsing green - under normal operation
- //
- logic running, heartbeat;
- logic [heartbeat_count_msb:0] tick_count;
- always_ff @(posedge Clock, negedge nReset )
- if ( ! nReset )
- begin
- running <= 0;
- heartbeat <= 0;
- tick_count <= 0;
- end
- else
- begin
- running <= 1;
- heartbeat = tick_count[heartbeat_count_msb] && tick_count[heartbeat_count_msb-2] && (&tick_count[heartbeat_dimmer_msb:0]);
- tick_count <= tick_count + 1;
- end
-
- // Single LED with two colours to indicate system status
- assign Status_Green = !running || ( heartbeat && !LOCKUP );
- assign Status_Red = !running || LOCKUP;
-
-
-
-
-endmodule
diff --git a/behavioural/raster.sv b/behavioural/raster.sv
deleted file mode 100644
index dd99d0b7a71cceea428b2a077fb363e696164ab0..0000000000000000000000000000000000000000
--- a/behavioural/raster.sv
+++ /dev/null
@@ -1,6 +0,0 @@
-module raster ( input logic CLOCK_50,
- input logic pixel,
- output logic [7:0] VGA_R,VGA_G,VGA_B,
- output logic [9:0] pixel_x,
- output logic [8:0] pixel_y ,
- output logic VGA_HS,VGA_VS, VGA_CLK, VGA_BLANK_N);
diff --git a/behavioural/razzle.sv.bak b/behavioural/razzle.sv.bak
deleted file mode 100644
index 850c55cd95579f937c384030bcbea231282fddd2..0000000000000000000000000000000000000000
--- a/behavioural/razzle.sv.bak
+++ /dev/null
@@ -1,156 +0,0 @@
-// Description:
-// This code generates a VGA output for ARM SoC based
-// on razzle code modified by Iain Mcnally <ECS, University of Soutampton>
-// Maintainer: Karthik Sathyanarayanan <ks6n19@soton.ac.uk>
-// Revision : $Revision$
-
-
-module razzle (
-
- input logic CLOCK_50,
- input logic [3:0] KEY,
- input logic [9:0] pixel,
- output logic [7:0] VGA_R,VGA_G,VGA_B,
- output logic [9:0] pixel_x,
- output logic [8:0] pixel_y ,
- output logic VGA_HS,VGA_VS, VGA_CLK, VGA_BLANK_N);
-
-// Video Display Signals
-logic [10:0] H_count,V_count;
-
-logic Red_Data;
-logic video_on, video_on_H, video_on_V, clock_enable;
-
-timeunit 1ns;
-timeprecision 100ps;
-
-// Map internal signals to external busses
-
-logic nReset;
-logic Red,Green,Blue;
-
-assign nReset=KEY[2]; // Keys are active low?
-
-assign VGA_R = Red ? 255 : 0;
-assign VGA_G = Green ? 255 : 0;
-assign VGA_B = Blue ? 255 : 0;
-
-assign VGA_CLK = clock_enable;
-assign VGA_BLANK_N = video_on;
-
-
-// Colors for pixel data on video signal
-assign Red_Data = pixel ;
-assign Green_Data = 0;
-assign Blue_Data = 0;
-
-// turn off color (black) at screen edges and during retrace with video_on
-assign Red = Red_Data && video_on;
-assign Green = Green_Data && video_on;
-assign Blue = Blue_Data && video_on;
-
-// video_on turns off pixel color data when not in the pixel view area
-assign video_on = video_on_H && video_on_V;
-
-assign pixel_x = H_count ;
-assign pixel_y = V_count ;
-
-// code for pixel as colour output
-
-always @(posedge CLOCK_50 , negedge nReset )
- if (! nReset)
- begin
- pixel = '0;
- end
-
- else
- begin : pixel
-
- if (video_on)
- pixel = '1;
-
- end : pixel
-
-// Generate Horizontal and Vertical Timing Signals for Video Signal
-//VIDEO_DISPLAY
-
-always @(posedge CLOCK_50, negedge nReset)
- if ( ! nReset)
- begin
- clock_enable = 0;
- H_count = 0;
- V_count = 0;
- video_on_H = 0;
- video_on_V = 0;
- end
-
- else
- begin : VIDEO_DISPLAY
- // Clock enable used for a 24Mhz video clock rate
- // 640 by 480 display mode needs close to a 25Mhz pixel clock
- // 24Mhz should work on most new monitors
-
- clock_enable = ! clock_enable;
-
- // H_count counts pixels (640 + extra time for sync signals)
- //
- // <-Clock out RGB Pixel Row Data -> <-H Sync->
- // ------------------------------------__________--------
- // 0 640 659 755 799
- //
-
- if ( clock_enable )
- begin
-
-
- if (H_count >= 799)
- H_count = 0;
- else
- H_count = H_count + 1;
-
- // Generate Horizontal Sync Signal
- if ((H_count <= 755) && (H_count >= 659))
- VGA_HS = 0;
- else
- VGA_HS = 1;
-
- // V_count counts rows of pixels (480 + extra time for sync signals)
- //
- // <---- 480 Horizontal Syncs (pixel rows) --> ->V Sync<-
- // -----------------------------------------------_______------------
- // 0 480 493-494 524
- //
- if ((V_count >= 524) && (H_count >= 699))
- V_count = 0;
- else if (H_count == 699)
- V_count = V_count + 1;
-
-
- // Generate Vertical Sync Signal
- if ((V_count <= 494) && (V_count >= 493))
- VGA_VS = 0;
- else
- VGA_VS = 1;
-
-
- // Generate Video on Screen Signals for Pixel Data
- if (H_count <= 639)
- video_on_H = 1;
- else
- video_on_H = 0;
-
-
- if (V_count <= 479)
- video_on_V = 1;
- else
- video_on_V = 0;
-
- end
-
- end : VIDEO_DISPLAY
-
-endmodule
-
-
-
-
diff --git a/behavioural/triangle.sv b/behavioural/triangle.sv
deleted file mode 100644
index 05d74dbb7149a0318c7a861523d7ea44fd1892c2..0000000000000000000000000000000000000000
--- a/behavioural/triangle.sv
+++ /dev/null
@@ -1,218 +0,0 @@
-module Triangle (
- input logic clk,
- input logic nReset,
- input logic [27:0]bv1, bv2, bv3,
- input logic [27:0]tv1, tv2, tv3,
- input logic [3:0] BCO, TCO,
- output logic [10:0] x, y,
- output logic [3:0] TRIcolour,
- output logic request);
-
-logic [10:0] ycurrent, xcurrent, bi, ti, j;
-logic [10:0] bx1, by1, bx2, by2, bx3, by3, btx2, bmax, top;
-logic [10:0] tx1, ty1, tx2, ty2, tx3, ty3, ttx2, tmax, bot;
-logic bm, bn, tm, tn;
-logic [31:0] bslope12, bslope13, tslope13, tslope23, b12, b13, t13, t23,d;
-logic [3:0] bco, tco;
-assign bx1 = bv1%640;
-assign by1 = bv1/640;
-assign bx2 = bv2%640;
-assign by2 = bv2/640;
-assign bx3 = bv3%640;
-assign by3 = bv3/640;
-assign tx1 = tv1%640;
-assign ty1 = tv1/640;
-assign tx2 = tv2%640;
-assign ty2 = tv2/640;
-assign tx3 = tv3%640;
-assign ty3 = tv3/640;
-//get value of slopes
-always_comb
-begin
- if(bx2>bx1)
- begin
- bslope12 = ((bx2-bx1)*10000)/(by2-by1);
- bm = 1;
- end
- else
- begin
- bslope12 = ((bx1-bx2)*10000)/(by2-by1);
- bm = 0;
- end
- if(bx3>bx1)
- begin
- bslope13 = ((bx3-bx1)*10000)/(by3-by1);
- bn = 1;
- end
- else
- begin
- bslope13 = ((bx1-bx3)*10000)/(by3-by1);
- bn = 0;
- end
- if(tx3>tx1)
- begin
- tslope13 = ((tx3-tx1)*10000)/(ty3-ty1);
- tm = 1;
- end
- else
- begin
- tslope13 = ((tx1-tx3)*10000)/(ty3-ty1);
- tm = 0;
- end
- if(tx3>tx2)
- begin
- tslope23 = ((tx3-tx2)*10000)/(ty3-ty2);
- tn = 1;
- end
- else
- begin
- tslope23 = ((tx2-tx3)*10000)/(ty3-ty2);
- tn = 0;
- end
-end
-
-enum{idle, bprep, bdrawy, bdrawx, tprep, tdrawy, tdrawx}state;
-
-always_ff @(posedge clk, negedge nReset)
- if ( ! nReset)
- begin
- ycurrent <= 0;
- xcurrent <= 0;
- bi <= 0;
- ti <= 0;
- j <= 0;
- d <= 0;
- btx2 <= 0;
- ttx2 <= 0;
- request <= 0;
- bco <= 0;
- bmax <= 0;
- state <= 0;
- b12 <= 0;
- b13 <= 0;
- top <= 0;
- ti <= 0;
- tco <= 0;
- tmax <= 0;
- state <= 0;
- t13 <= 0;
- t23 <= 0;
- bot <= 0;
- TRIcolour <= 0;
- end
- else
- begin : DRAW_BOTTOM_FLAT_TRIANGLE
- case(state)
- idle:begin
- request <= 0;
- if(by3 != 0)
- state <= bprep;
- else if (ty3 != 0)
- state <= tprep;
- end
- bprep:begin
- d <= 0;
- bi <= by1;
- bco <= BCO;
- bmax <= by2;
- state <= bdrawy;
- b12 <= bslope12;
- b13 <= bslope13;
- top <= bx1;
- end
- bdrawy:begin
- request <= 0;
- ycurrent <= bi;
-
- if(bm)
- j <= top + (d*b12)/10000;
- else
- j <= top - (d*b12)/10000;
-
- if(bn)
- btx2 <= top + (d*b13)/10000;
- else
- btx2 <= top - (d*b13)/10000;
-
- state <= bdrawx;
- end
-
- bdrawx:begin
- xcurrent <= j;
- TRIcolour <= bco;
- request <= 1;
- j = j+1;
- if( j > btx2)
- begin
- bi <= bi+1;
- if(bi< bmax)
-
- begin
- d = d+1;
- state <= bdrawy;
- end
-
- else if (ty3 != 0)
- state <= tprep;
-
- else
- state <= idle;
- end
-
- end
-
- tprep:begin
- request <= 0;
- d <= 0;
- ti <= ty3;
- tco <= TCO;
- tmax <= ty1;
- state <= tdrawy;
- t13 <= tslope13;
- t23 <= tslope23;
- bot <= tx3;
- end
-
- tdrawy:begin
- request <= 0;
- ycurrent <= ti;
- if(tm)
- j <= bot - (d*t13)/10000;
- else
- j <= bot + (d*t13)/10000;
-
-
- if(tn)
- ttx2 <= bot - (d*t23)/10000;
- else
- ttx2 <= bot + (d*t23)/10000;
-
- state <= tdrawx;
- end
- tdrawx:begin
- xcurrent <= j;
- TRIcolour <= tco;
- request <= 1;
- j = j+1;
- if( j > ttx2)
- begin
- ti <= ti-1;
- if(ti> tmax)
- begin
- d = d+1;
- state <= tdrawy;
- end
-
- else
- begin
- state <= idle;
- end
- end
- end
- endcase
- end : DRAW_BOTTOM_FLAT_TRIANGLE
-
-assign x = xcurrent;
-assign y = ycurrent;
-
-endmodule
diff --git a/constraints/DE0.qsf b/constraints/DE0.qsf
deleted file mode 100644
index 4c2d00b7c7cf9d53fae664d0279a184e5489bcb1..0000000000000000000000000000000000000000
--- a/constraints/DE0.qsf
+++ /dev/null
@@ -1,547 +0,0 @@
-# Copyright (C) 1991-2010 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE EP3C16F484C6
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_B1 -to LEDG[9]
-set_location_assignment PIN_B2 -to LEDG[8]
-set_location_assignment PIN_C2 -to LEDG[7]
-set_location_assignment PIN_C1 -to LEDG[6]
-set_location_assignment PIN_E1 -to LEDG[5]
-set_location_assignment PIN_F2 -to LEDG[4]
-set_location_assignment PIN_H1 -to LEDG[3]
-set_location_assignment PIN_J3 -to LEDG[2]
-set_location_assignment PIN_J2 -to LEDG[1]
-set_location_assignment PIN_J1 -to LEDG[0]
-set_location_assignment PIN_D2 -to SW[9]
-set_location_assignment PIN_E4 -to SW[8]
-set_location_assignment PIN_E3 -to SW[7]
-set_location_assignment PIN_H7 -to SW[6]
-set_location_assignment PIN_J7 -to SW[5]
-set_location_assignment PIN_G5 -to SW[4]
-set_location_assignment PIN_G4 -to SW[3]
-set_location_assignment PIN_H6 -to SW[2]
-set_location_assignment PIN_H5 -to SW[1]
-set_location_assignment PIN_J6 -to SW[0]
-set_location_assignment PIN_F1 -to KEY[2]
-set_location_assignment PIN_G3 -to KEY[1]
-set_location_assignment PIN_H2 -to KEY[0]
-set_location_assignment PIN_R2 -to FL_ADDR[21]
-set_location_assignment PIN_P3 -to FL_ADDR[20]
-set_location_assignment PIN_P1 -to FL_ADDR[19]
-set_location_assignment PIN_M6 -to FL_ADDR[18]
-set_location_assignment PIN_M5 -to FL_ADDR[17]
-set_location_assignment PIN_AA2 -to FL_ADDR[16]
-set_location_assignment PIN_L6 -to FL_ADDR[15]
-set_location_assignment PIN_L7 -to FL_ADDR[14]
-set_location_assignment PIN_M1 -to FL_ADDR[13]
-set_location_assignment PIN_M2 -to FL_ADDR[12]
-set_location_assignment PIN_M3 -to FL_ADDR[11]
-set_location_assignment PIN_N1 -to FL_ADDR[10]
-set_location_assignment PIN_N2 -to FL_ADDR[9]
-set_location_assignment PIN_P2 -to FL_ADDR[8]
-set_location_assignment PIN_M4 -to FL_ADDR[7]
-set_location_assignment PIN_M8 -to FL_ADDR[6]
-set_location_assignment PIN_N6 -to FL_ADDR[5]
-set_location_assignment PIN_N5 -to FL_ADDR[4]
-set_location_assignment PIN_N7 -to FL_ADDR[3]
-set_location_assignment PIN_P6 -to FL_ADDR[2]
-set_location_assignment PIN_P5 -to FL_ADDR[1]
-set_location_assignment PIN_P7 -to FL_ADDR[0]
-set_location_assignment PIN_AA1 -to FL_BYTE_N
-set_location_assignment PIN_N8 -to FL_CE_N
-set_location_assignment PIN_R7 -to FL_DQ[0]
-set_location_assignment PIN_P8 -to FL_DQ[1]
-set_location_assignment PIN_R8 -to FL_DQ[2]
-set_location_assignment PIN_U1 -to FL_DQ[3]
-set_location_assignment PIN_V2 -to FL_DQ[4]
-set_location_assignment PIN_V3 -to FL_DQ[5]
-set_location_assignment PIN_W1 -to FL_DQ[6]
-set_location_assignment PIN_Y1 -to FL_DQ[7]
-set_location_assignment PIN_T5 -to FL_DQ[8]
-set_location_assignment PIN_T7 -to FL_DQ[9]
-set_location_assignment PIN_T4 -to FL_DQ[10]
-set_location_assignment PIN_U2 -to FL_DQ[11]
-set_location_assignment PIN_V1 -to FL_DQ[12]
-set_location_assignment PIN_V4 -to FL_DQ[13]
-set_location_assignment PIN_W2 -to FL_DQ[14]
-set_location_assignment PIN_R6 -to FL_OE_N
-set_location_assignment PIN_R1 -to FL_RST_N
-set_location_assignment PIN_M7 -to FL_RY
-set_location_assignment PIN_P4 -to FL_WE_N
-set_location_assignment PIN_T3 -to FL_WP_N
-set_location_assignment PIN_Y2 -to FL_DQ15_AM1
-set_location_assignment PIN_U7 -to GPIO_0[31]
-set_location_assignment PIN_V5 -to GPIO_0[30]
-set_location_assignment PIN_W6 -to GPIO_0[29]
-set_location_assignment PIN_W7 -to GPIO_0[28]
-set_location_assignment PIN_V8 -to GPIO_0[27]
-set_location_assignment PIN_T8 -to GPIO_0[26]
-set_location_assignment PIN_W10 -to GPIO_0[25]
-set_location_assignment PIN_Y10 -to GPIO_0[24]
-set_location_assignment PIN_V11 -to GPIO_0[23]
-set_location_assignment PIN_R10 -to GPIO_0[22]
-set_location_assignment PIN_V12 -to GPIO_0[21]
-set_location_assignment PIN_U13 -to GPIO_0[20]
-set_location_assignment PIN_W13 -to GPIO_0[19]
-set_location_assignment PIN_Y13 -to GPIO_0[18]
-set_location_assignment PIN_U14 -to GPIO_0[17]
-set_location_assignment PIN_V14 -to GPIO_0[16]
-set_location_assignment PIN_AA4 -to GPIO_0[15]
-set_location_assignment PIN_AB4 -to GPIO_0[14]
-set_location_assignment PIN_AA5 -to GPIO_0[13]
-set_location_assignment PIN_AB5 -to GPIO_0[12]
-set_location_assignment PIN_AA8 -to GPIO_0[11]
-set_location_assignment PIN_AB8 -to GPIO_0[10]
-set_location_assignment PIN_AA10 -to GPIO_0[9]
-set_location_assignment PIN_AB10 -to GPIO_0[8]
-set_location_assignment PIN_AA13 -to GPIO_0[7]
-set_location_assignment PIN_AB13 -to GPIO_0[6]
-set_location_assignment PIN_AB14 -to GPIO_0[5]
-set_location_assignment PIN_AA14 -to GPIO_0[4]
-set_location_assignment PIN_AB15 -to GPIO_0[3]
-set_location_assignment PIN_AA15 -to GPIO_0[2]
-set_location_assignment PIN_AA16 -to GPIO_0[1]
-set_location_assignment PIN_AB16 -to GPIO_0[0]
-set_location_assignment PIN_AB12 -to GPIO_CLKIN_N0
-set_location_assignment PIN_AA12 -to GPIO_CLKIN_P0
-set_location_assignment PIN_AB3 -to GPIO_CLKOUT_N0
-set_location_assignment PIN_AA3 -to GPIO_CLKOUT_P0
-set_location_assignment PIN_AA11 -to GPIO_CLKIN_P1
-set_location_assignment PIN_AB11 -to GPIO_CLKIN_N1
-set_location_assignment PIN_T16 -to GPIO_CLKOUT_P1
-set_location_assignment PIN_R16 -to GPIO_CLKOUT_N1
-set_location_assignment PIN_V7 -to GPIO_1[31]
-set_location_assignment PIN_V6 -to GPIO_1[30]
-set_location_assignment PIN_U8 -to GPIO_1[29]
-set_location_assignment PIN_Y7 -to GPIO_1[28]
-set_location_assignment PIN_T9 -to GPIO_1[27]
-set_location_assignment PIN_U9 -to GPIO_1[26]
-set_location_assignment PIN_T10 -to GPIO_1[25]
-set_location_assignment PIN_U10 -to GPIO_1[24]
-set_location_assignment PIN_R12 -to GPIO_1[23]
-set_location_assignment PIN_R11 -to GPIO_1[22]
-set_location_assignment PIN_T12 -to GPIO_1[21]
-set_location_assignment PIN_U12 -to GPIO_1[20]
-set_location_assignment PIN_R14 -to GPIO_1[19]
-set_location_assignment PIN_T14 -to GPIO_1[18]
-set_location_assignment PIN_AB7 -to GPIO_1[17]
-set_location_assignment PIN_AA7 -to GPIO_1[16]
-set_location_assignment PIN_AA9 -to GPIO_1[15]
-set_location_assignment PIN_AB9 -to GPIO_1[14]
-set_location_assignment PIN_V15 -to GPIO_1[13]
-set_location_assignment PIN_W15 -to GPIO_1[12]
-set_location_assignment PIN_T15 -to GPIO_1[11]
-set_location_assignment PIN_U15 -to GPIO_1[10]
-set_location_assignment PIN_W17 -to GPIO_1[9]
-set_location_assignment PIN_Y17 -to GPIO_1[8]
-set_location_assignment PIN_AB17 -to GPIO_1[7]
-set_location_assignment PIN_AA17 -to GPIO_1[6]
-set_location_assignment PIN_AA18 -to GPIO_1[5]
-set_location_assignment PIN_AB18 -to GPIO_1[4]
-set_location_assignment PIN_AB19 -to GPIO_1[3]
-set_location_assignment PIN_AA19 -to GPIO_1[2]
-set_location_assignment PIN_AB20 -to GPIO_1[1]
-set_location_assignment PIN_AA20 -to GPIO_1[0]
-set_location_assignment PIN_P22 -to PS2_KBCLK
-set_location_assignment PIN_P21 -to PS2_KBDAT
-set_location_assignment PIN_R21 -to PS2_MSCLK
-set_location_assignment PIN_R22 -to PS2_MSDAT
-set_location_assignment PIN_U22 -to UART_RXD
-set_location_assignment PIN_U21 -to UART_TXD
-set_location_assignment PIN_V22 -to UART_RTS
-set_location_assignment PIN_V21 -to UART_CTS
-set_location_assignment PIN_Y21 -to SD_CLK
-set_location_assignment PIN_Y22 -to SD_CMD
-set_location_assignment PIN_AA22 -to SD_DAT0
-set_location_assignment PIN_W21 -to SD_DAT3
-set_location_assignment PIN_W20 -to SD_WP_N
-set_location_assignment PIN_C20 -to LCD_DATA[7]
-set_location_assignment PIN_D20 -to LCD_DATA[6]
-set_location_assignment PIN_B21 -to LCD_DATA[5]
-set_location_assignment PIN_B22 -to LCD_DATA[4]
-set_location_assignment PIN_C21 -to LCD_DATA[3]
-set_location_assignment PIN_C22 -to LCD_DATA[2]
-set_location_assignment PIN_D21 -to LCD_DATA[1]
-set_location_assignment PIN_D22 -to LCD_DATA[0]
-set_location_assignment PIN_E22 -to LCD_RW
-set_location_assignment PIN_F22 -to LCD_RS
-set_location_assignment PIN_E21 -to LCD_EN
-set_location_assignment PIN_F21 -to LCD_BLON
-set_location_assignment PIN_J21 -to VGA_G[3]
-set_location_assignment PIN_K17 -to VGA_G[2]
-set_location_assignment PIN_J17 -to VGA_G[1]
-set_location_assignment PIN_H22 -to VGA_G[0]
-set_location_assignment PIN_L21 -to VGA_HS
-set_location_assignment PIN_L22 -to VGA_VS
-set_location_assignment PIN_H21 -to VGA_R[3]
-set_location_assignment PIN_H20 -to VGA_R[2]
-set_location_assignment PIN_H17 -to VGA_R[1]
-set_location_assignment PIN_H19 -to VGA_R[0]
-set_location_assignment PIN_K18 -to VGA_B[3]
-set_location_assignment PIN_J22 -to VGA_B[2]
-set_location_assignment PIN_K21 -to VGA_B[1]
-set_location_assignment PIN_K22 -to VGA_B[0]
-set_location_assignment PIN_G21 -to CLOCK_50
-set_location_assignment PIN_E11 -to HEX0[0]
-set_location_assignment PIN_F11 -to HEX0[1]
-set_location_assignment PIN_H12 -to HEX0[2]
-set_location_assignment PIN_H13 -to HEX0[3]
-set_location_assignment PIN_G12 -to HEX0[4]
-set_location_assignment PIN_F12 -to HEX0[5]
-set_location_assignment PIN_F13 -to HEX0[6]
-set_location_assignment PIN_D13 -to HEX0[7]
-set_location_assignment PIN_A15 -to HEX1[6]
-set_location_assignment PIN_E14 -to HEX1[5]
-set_location_assignment PIN_B14 -to HEX1[4]
-set_location_assignment PIN_A14 -to HEX1[3]
-set_location_assignment PIN_C13 -to HEX1[2]
-set_location_assignment PIN_B13 -to HEX1[1]
-set_location_assignment PIN_A13 -to HEX1[0]
-set_location_assignment PIN_B15 -to HEX1[7]
-set_location_assignment PIN_F14 -to HEX2[6]
-set_location_assignment PIN_B17 -to HEX2[5]
-set_location_assignment PIN_A17 -to HEX2[4]
-set_location_assignment PIN_E15 -to HEX2[3]
-set_location_assignment PIN_B16 -to HEX2[2]
-set_location_assignment PIN_A16 -to HEX2[1]
-set_location_assignment PIN_D15 -to HEX2[0]
-set_location_assignment PIN_A18 -to HEX2[7]
-set_location_assignment PIN_G15 -to HEX3[6]
-set_location_assignment PIN_D19 -to HEX3[5]
-set_location_assignment PIN_C19 -to HEX3[4]
-set_location_assignment PIN_B19 -to HEX3[3]
-set_location_assignment PIN_A19 -to HEX3[2]
-set_location_assignment PIN_F15 -to HEX3[1]
-set_location_assignment PIN_B18 -to HEX3[0]
-set_location_assignment PIN_G16 -to HEX3[7]
-set_location_assignment PIN_G8 -to DRAM_CAS_N
-set_location_assignment PIN_G7 -to DRAM_CS_N
-set_location_assignment PIN_E5 -to DRAM_CLK
-set_location_assignment PIN_E6 -to DRAM_CKE
-set_location_assignment PIN_B5 -to DRAM_BA[0]
-set_location_assignment PIN_A4 -to DRAM_BA[1]
-set_location_assignment PIN_F10 -to DRAM_DQ[15]
-set_location_assignment PIN_E10 -to DRAM_DQ[14]
-set_location_assignment PIN_A10 -to DRAM_DQ[13]
-set_location_assignment PIN_B10 -to DRAM_DQ[12]
-set_location_assignment PIN_C10 -to DRAM_DQ[11]
-set_location_assignment PIN_A9 -to DRAM_DQ[10]
-set_location_assignment PIN_B9 -to DRAM_DQ[9]
-set_location_assignment PIN_A8 -to DRAM_DQ[8]
-set_location_assignment PIN_F8 -to DRAM_DQ[7]
-set_location_assignment PIN_H9 -to DRAM_DQ[6]
-set_location_assignment PIN_G9 -to DRAM_DQ[5]
-set_location_assignment PIN_F9 -to DRAM_DQ[4]
-set_location_assignment PIN_E9 -to DRAM_DQ[3]
-set_location_assignment PIN_H10 -to DRAM_DQ[2]
-set_location_assignment PIN_G10 -to DRAM_DQ[1]
-set_location_assignment PIN_D10 -to DRAM_DQ[0]
-set_location_assignment PIN_E7 -to DRAM_LDQM
-set_location_assignment PIN_B8 -to DRAM_UDQM
-set_location_assignment PIN_F7 -to DRAM_RAS_N
-set_location_assignment PIN_D6 -to DRAM_WE_N
-set_location_assignment PIN_B12 -to CLOCK_50_2
-set_location_assignment PIN_C8 -to DRAM_ADDR[12]
-set_location_assignment PIN_A7 -to DRAM_ADDR[11]
-set_location_assignment PIN_B4 -to DRAM_ADDR[10]
-set_location_assignment PIN_B7 -to DRAM_ADDR[9]
-set_location_assignment PIN_C7 -to DRAM_ADDR[8]
-set_location_assignment PIN_A6 -to DRAM_ADDR[7]
-set_location_assignment PIN_B6 -to DRAM_ADDR[6]
-set_location_assignment PIN_C6 -to DRAM_ADDR[5]
-set_location_assignment PIN_A5 -to DRAM_ADDR[4]
-set_location_assignment PIN_C3 -to DRAM_ADDR[3]
-set_location_assignment PIN_B3 -to DRAM_ADDR[2]
-set_location_assignment PIN_A3 -to DRAM_ADDR[1]
-set_location_assignment PIN_C4 -to DRAM_ADDR[0]
-
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_CLKOUT_N1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_CLKOUT_P1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_CLKIN_N1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_CLKIN_P1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_CLKOUT_N0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_CLKOUT_P0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_CLKIN_N0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_CLKIN_P0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
-
-set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
-
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to *
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to *
-set_instance_assignment -name TSU_REQUIREMENT "10 ns" -from * -to *
-
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/constraints/DE2.qsf b/constraints/DE2.qsf
deleted file mode 100644
index 78eb924f921f4c31d34bc9b0f4211add37c6658f..0000000000000000000000000000000000000000
--- a/constraints/DE2.qsf
+++ /dev/null
@@ -1,464 +0,0 @@
-# Copyright (C) 1991-2010 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-set_global_assignment -name DEVICE EP2C35F672C6
-set_global_assignment -name FAMILY "Cyclone II"
-
-set_location_assignment PIN_N25 -to SW[0]
-set_location_assignment PIN_N26 -to SW[1]
-set_location_assignment PIN_P25 -to SW[2]
-set_location_assignment PIN_AE14 -to SW[3]
-set_location_assignment PIN_AF14 -to SW[4]
-set_location_assignment PIN_AD13 -to SW[5]
-set_location_assignment PIN_AC13 -to SW[6]
-set_location_assignment PIN_C13 -to SW[7]
-set_location_assignment PIN_B13 -to SW[8]
-set_location_assignment PIN_A13 -to SW[9]
-set_location_assignment PIN_N1 -to SW[10]
-set_location_assignment PIN_P1 -to SW[11]
-set_location_assignment PIN_P2 -to SW[12]
-set_location_assignment PIN_T7 -to SW[13]
-set_location_assignment PIN_U3 -to SW[14]
-set_location_assignment PIN_U4 -to SW[15]
-set_location_assignment PIN_V1 -to SW[16]
-set_location_assignment PIN_V2 -to SW[17]
-set_location_assignment PIN_T6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V4 -to DRAM_ADDR[1]
-set_location_assignment PIN_V3 -to DRAM_ADDR[2]
-set_location_assignment PIN_W2 -to DRAM_ADDR[3]
-set_location_assignment PIN_W1 -to DRAM_ADDR[4]
-set_location_assignment PIN_U6 -to DRAM_ADDR[5]
-set_location_assignment PIN_U7 -to DRAM_ADDR[6]
-set_location_assignment PIN_U5 -to DRAM_ADDR[7]
-set_location_assignment PIN_W4 -to DRAM_ADDR[8]
-set_location_assignment PIN_W3 -to DRAM_ADDR[9]
-set_location_assignment PIN_Y1 -to DRAM_ADDR[10]
-set_location_assignment PIN_V5 -to DRAM_ADDR[11]
-set_location_assignment PIN_AE2 -to DRAM_BA_0
-set_location_assignment PIN_AE3 -to DRAM_BA_1
-set_location_assignment PIN_AB3 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AA7 -to DRAM_CLK
-set_location_assignment PIN_AC3 -to DRAM_CS_N
-set_location_assignment PIN_V6 -to DRAM_DQ[0]
-set_location_assignment PIN_AA2 -to DRAM_DQ[1]
-set_location_assignment PIN_AA1 -to DRAM_DQ[2]
-set_location_assignment PIN_Y3 -to DRAM_DQ[3]
-set_location_assignment PIN_Y4 -to DRAM_DQ[4]
-set_location_assignment PIN_R8 -to DRAM_DQ[5]
-set_location_assignment PIN_T8 -to DRAM_DQ[6]
-set_location_assignment PIN_V7 -to DRAM_DQ[7]
-set_location_assignment PIN_W6 -to DRAM_DQ[8]
-set_location_assignment PIN_AB2 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA4 -to DRAM_DQ[11]
-set_location_assignment PIN_AA3 -to DRAM_DQ[12]
-set_location_assignment PIN_AC2 -to DRAM_DQ[13]
-set_location_assignment PIN_AC1 -to DRAM_DQ[14]
-set_location_assignment PIN_AA5 -to DRAM_DQ[15]
-set_location_assignment PIN_AD2 -to DRAM_LDQM
-set_location_assignment PIN_Y5 -to DRAM_UDQM
-set_location_assignment PIN_AB4 -to DRAM_RAS_N
-set_location_assignment PIN_AD3 -to DRAM_WE_N
-set_location_assignment PIN_AC18 -to FL_ADDR[0]
-set_location_assignment PIN_AB18 -to FL_ADDR[1]
-set_location_assignment PIN_AE19 -to FL_ADDR[2]
-set_location_assignment PIN_AF19 -to FL_ADDR[3]
-set_location_assignment PIN_AE18 -to FL_ADDR[4]
-set_location_assignment PIN_AF18 -to FL_ADDR[5]
-set_location_assignment PIN_Y16 -to FL_ADDR[6]
-set_location_assignment PIN_AA16 -to FL_ADDR[7]
-set_location_assignment PIN_AD17 -to FL_ADDR[8]
-set_location_assignment PIN_AC17 -to FL_ADDR[9]
-set_location_assignment PIN_AE17 -to FL_ADDR[10]
-set_location_assignment PIN_AF17 -to FL_ADDR[11]
-set_location_assignment PIN_W16 -to FL_ADDR[12]
-set_location_assignment PIN_W15 -to FL_ADDR[13]
-set_location_assignment PIN_AC16 -to FL_ADDR[14]
-set_location_assignment PIN_AD16 -to FL_ADDR[15]
-set_location_assignment PIN_AE16 -to FL_ADDR[16]
-set_location_assignment PIN_AC15 -to FL_ADDR[17]
-set_location_assignment PIN_AB15 -to FL_ADDR[18]
-set_location_assignment PIN_AA15 -to FL_ADDR[19]
-set_location_assignment PIN_Y15 -to FL_ADDR[20]
-set_location_assignment PIN_Y14 -to FL_ADDR[21]
-set_location_assignment PIN_V17 -to FL_CE_N
-set_location_assignment PIN_W17 -to FL_OE_N
-set_location_assignment PIN_AD19 -to FL_DQ[0]
-set_location_assignment PIN_AC19 -to FL_DQ[1]
-set_location_assignment PIN_AF20 -to FL_DQ[2]
-set_location_assignment PIN_AE20 -to FL_DQ[3]
-set_location_assignment PIN_AB20 -to FL_DQ[4]
-set_location_assignment PIN_AC20 -to FL_DQ[5]
-set_location_assignment PIN_AF21 -to FL_DQ[6]
-set_location_assignment PIN_AE21 -to FL_DQ[7]
-set_location_assignment PIN_AA18 -to FL_RST_N
-set_location_assignment PIN_AA17 -to FL_WE_N
-set_location_assignment PIN_AF10 -to HEX0[0]
-set_location_assignment PIN_AB12 -to HEX0[1]
-set_location_assignment PIN_AC12 -to HEX0[2]
-set_location_assignment PIN_AD11 -to HEX0[3]
-set_location_assignment PIN_AE11 -to HEX0[4]
-set_location_assignment PIN_V14 -to HEX0[5]
-set_location_assignment PIN_V13 -to HEX0[6]
-set_location_assignment PIN_V20 -to HEX1[0]
-set_location_assignment PIN_V21 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_Y22 -to HEX1[3]
-set_location_assignment PIN_AA24 -to HEX1[4]
-set_location_assignment PIN_AA23 -to HEX1[5]
-set_location_assignment PIN_AB24 -to HEX1[6]
-set_location_assignment PIN_AB23 -to HEX2[0]
-set_location_assignment PIN_V22 -to HEX2[1]
-set_location_assignment PIN_AC25 -to HEX2[2]
-set_location_assignment PIN_AC26 -to HEX2[3]
-set_location_assignment PIN_AB26 -to HEX2[4]
-set_location_assignment PIN_AB25 -to HEX2[5]
-set_location_assignment PIN_Y24 -to HEX2[6]
-set_location_assignment PIN_Y23 -to HEX3[0]
-set_location_assignment PIN_AA25 -to HEX3[1]
-set_location_assignment PIN_AA26 -to HEX3[2]
-set_location_assignment PIN_Y26 -to HEX3[3]
-set_location_assignment PIN_Y25 -to HEX3[4]
-set_location_assignment PIN_U22 -to HEX3[5]
-set_location_assignment PIN_W24 -to HEX3[6]
-set_location_assignment PIN_U9 -to HEX4[0]
-set_location_assignment PIN_U1 -to HEX4[1]
-set_location_assignment PIN_U2 -to HEX4[2]
-set_location_assignment PIN_T4 -to HEX4[3]
-set_location_assignment PIN_R7 -to HEX4[4]
-set_location_assignment PIN_R6 -to HEX4[5]
-set_location_assignment PIN_T3 -to HEX4[6]
-set_location_assignment PIN_T2 -to HEX5[0]
-set_location_assignment PIN_P6 -to HEX5[1]
-set_location_assignment PIN_P7 -to HEX5[2]
-set_location_assignment PIN_T9 -to HEX5[3]
-set_location_assignment PIN_R5 -to HEX5[4]
-set_location_assignment PIN_R4 -to HEX5[5]
-set_location_assignment PIN_R3 -to HEX5[6]
-set_location_assignment PIN_R2 -to HEX6[0]
-set_location_assignment PIN_P4 -to HEX6[1]
-set_location_assignment PIN_P3 -to HEX6[2]
-set_location_assignment PIN_M2 -to HEX6[3]
-set_location_assignment PIN_M3 -to HEX6[4]
-set_location_assignment PIN_M5 -to HEX6[5]
-set_location_assignment PIN_M4 -to HEX6[6]
-set_location_assignment PIN_L3 -to HEX7[0]
-set_location_assignment PIN_L2 -to HEX7[1]
-set_location_assignment PIN_L9 -to HEX7[2]
-set_location_assignment PIN_L6 -to HEX7[3]
-set_location_assignment PIN_L7 -to HEX7[4]
-set_location_assignment PIN_P9 -to HEX7[5]
-set_location_assignment PIN_N9 -to HEX7[6]
-set_location_assignment PIN_G26 -to KEY[0]
-set_location_assignment PIN_N23 -to KEY[1]
-set_location_assignment PIN_P23 -to KEY[2]
-set_location_assignment PIN_W26 -to KEY[3]
-set_location_assignment PIN_AE23 -to LEDR[0]
-set_location_assignment PIN_AF23 -to LEDR[1]
-set_location_assignment PIN_AB21 -to LEDR[2]
-set_location_assignment PIN_AC22 -to LEDR[3]
-set_location_assignment PIN_AD22 -to LEDR[4]
-set_location_assignment PIN_AD23 -to LEDR[5]
-set_location_assignment PIN_AD21 -to LEDR[6]
-set_location_assignment PIN_AC21 -to LEDR[7]
-set_location_assignment PIN_AA14 -to LEDR[8]
-set_location_assignment PIN_Y13 -to LEDR[9]
-set_location_assignment PIN_AA13 -to LEDR[10]
-set_location_assignment PIN_AC14 -to LEDR[11]
-set_location_assignment PIN_AD15 -to LEDR[12]
-set_location_assignment PIN_AE15 -to LEDR[13]
-set_location_assignment PIN_AF13 -to LEDR[14]
-set_location_assignment PIN_AE13 -to LEDR[15]
-set_location_assignment PIN_AE12 -to LEDR[16]
-set_location_assignment PIN_AD12 -to LEDR[17]
-set_location_assignment PIN_AE22 -to LEDG[0]
-set_location_assignment PIN_AF22 -to LEDG[1]
-set_location_assignment PIN_W19 -to LEDG[2]
-set_location_assignment PIN_V18 -to LEDG[3]
-set_location_assignment PIN_U18 -to LEDG[4]
-set_location_assignment PIN_U17 -to LEDG[5]
-set_location_assignment PIN_AA20 -to LEDG[6]
-set_location_assignment PIN_Y18 -to LEDG[7]
-set_location_assignment PIN_Y12 -to LEDG[8]
-set_location_assignment PIN_D13 -to CLOCK_27
-set_location_assignment PIN_N2 -to CLOCK_50
-set_location_assignment PIN_P26 -to EXT_CLOCK
-set_location_assignment PIN_D26 -to PS2_CLK
-set_location_assignment PIN_C24 -to PS2_DAT
-set_location_assignment PIN_C25 -to UART_RXD
-set_location_assignment PIN_B25 -to UART_TXD
-set_location_assignment PIN_K4 -to LCD_RW
-set_location_assignment PIN_K3 -to LCD_EN
-set_location_assignment PIN_K1 -to LCD_RS
-set_location_assignment PIN_J1 -to LCD_DATA[0]
-set_location_assignment PIN_J2 -to LCD_DATA[1]
-set_location_assignment PIN_H1 -to LCD_DATA[2]
-set_location_assignment PIN_H2 -to LCD_DATA[3]
-set_location_assignment PIN_J4 -to LCD_DATA[4]
-set_location_assignment PIN_J3 -to LCD_DATA[5]
-set_location_assignment PIN_H4 -to LCD_DATA[6]
-set_location_assignment PIN_H3 -to LCD_DATA[7]
-set_location_assignment PIN_L4 -to LCD_ON
-set_location_assignment PIN_K2 -to LCD_BLON
-set_location_assignment PIN_AE4 -to SRAM_ADDR[0]
-set_location_assignment PIN_AF4 -to SRAM_ADDR[1]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC6 -to SRAM_ADDR[3]
-set_location_assignment PIN_AD4 -to SRAM_ADDR[4]
-set_location_assignment PIN_AD5 -to SRAM_ADDR[5]
-set_location_assignment PIN_AE5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AD6 -to SRAM_ADDR[8]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[9]
-set_location_assignment PIN_V10 -to SRAM_ADDR[10]
-set_location_assignment PIN_V9 -to SRAM_ADDR[11]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[12]
-set_location_assignment PIN_W8 -to SRAM_ADDR[13]
-set_location_assignment PIN_W10 -to SRAM_ADDR[14]
-set_location_assignment PIN_Y10 -to SRAM_ADDR[15]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[16]
-set_location_assignment PIN_AC8 -to SRAM_ADDR[17]
-set_location_assignment PIN_AD8 -to SRAM_DQ[0]
-set_location_assignment PIN_AE6 -to SRAM_DQ[1]
-set_location_assignment PIN_AF6 -to SRAM_DQ[2]
-set_location_assignment PIN_AA9 -to SRAM_DQ[3]
-set_location_assignment PIN_AA10 -to SRAM_DQ[4]
-set_location_assignment PIN_AB10 -to SRAM_DQ[5]
-set_location_assignment PIN_AA11 -to SRAM_DQ[6]
-set_location_assignment PIN_Y11 -to SRAM_DQ[7]
-set_location_assignment PIN_AE7 -to SRAM_DQ[8]
-set_location_assignment PIN_AF7 -to SRAM_DQ[9]
-set_location_assignment PIN_AE8 -to SRAM_DQ[10]
-set_location_assignment PIN_AF8 -to SRAM_DQ[11]
-set_location_assignment PIN_W11 -to SRAM_DQ[12]
-set_location_assignment PIN_W12 -to SRAM_DQ[13]
-set_location_assignment PIN_AC9 -to SRAM_DQ[14]
-set_location_assignment PIN_AC10 -to SRAM_DQ[15]
-set_location_assignment PIN_AE10 -to SRAM_WE_N
-set_location_assignment PIN_AD10 -to SRAM_OE_N
-set_location_assignment PIN_AF9 -to SRAM_UB_N
-set_location_assignment PIN_AE9 -to SRAM_LB_N
-set_location_assignment PIN_AC11 -to SRAM_CE_N
-set_location_assignment PIN_K7 -to OTG_ADDR[0]
-set_location_assignment PIN_F2 -to OTG_ADDR[1]
-set_location_assignment PIN_F1 -to OTG_CS_N
-set_location_assignment PIN_G2 -to OTG_RD_N
-set_location_assignment PIN_G1 -to OTG_WR_N
-set_location_assignment PIN_G5 -to OTG_RST_N
-set_location_assignment PIN_F4 -to OTG_DATA[0]
-set_location_assignment PIN_D2 -to OTG_DATA[1]
-set_location_assignment PIN_D1 -to OTG_DATA[2]
-set_location_assignment PIN_F7 -to OTG_DATA[3]
-set_location_assignment PIN_J5 -to OTG_DATA[4]
-set_location_assignment PIN_J8 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_E2 -to OTG_DATA[8]
-set_location_assignment PIN_E1 -to OTG_DATA[9]
-set_location_assignment PIN_K6 -to OTG_DATA[10]
-set_location_assignment PIN_K5 -to OTG_DATA[11]
-set_location_assignment PIN_G4 -to OTG_DATA[12]
-set_location_assignment PIN_G3 -to OTG_DATA[13]
-set_location_assignment PIN_J6 -to OTG_DATA[14]
-set_location_assignment PIN_K8 -to OTG_DATA[15]
-set_location_assignment PIN_B3 -to OTG_INT0
-set_location_assignment PIN_C3 -to OTG_INT1
-set_location_assignment PIN_C2 -to OTG_DACK0_N
-set_location_assignment PIN_B2 -to OTG_DACK1_N
-set_location_assignment PIN_F6 -to OTG_DREQ0
-set_location_assignment PIN_E5 -to OTG_DREQ1
-set_location_assignment PIN_F3 -to OTG_FSPEED
-set_location_assignment PIN_G6 -to OTG_LSPEED
-set_location_assignment PIN_B14 -to TDI
-set_location_assignment PIN_A14 -to TCS
-set_location_assignment PIN_D14 -to TCK
-set_location_assignment PIN_F14 -to TDO
-set_location_assignment PIN_C4 -to TD_RESET
-set_location_assignment PIN_C8 -to VGA_R[0]
-set_location_assignment PIN_F10 -to VGA_R[1]
-set_location_assignment PIN_G10 -to VGA_R[2]
-set_location_assignment PIN_D9 -to VGA_R[3]
-set_location_assignment PIN_C9 -to VGA_R[4]
-set_location_assignment PIN_A8 -to VGA_R[5]
-set_location_assignment PIN_H11 -to VGA_R[6]
-set_location_assignment PIN_H12 -to VGA_R[7]
-set_location_assignment PIN_F11 -to VGA_R[8]
-set_location_assignment PIN_E10 -to VGA_R[9]
-set_location_assignment PIN_B9 -to VGA_G[0]
-set_location_assignment PIN_A9 -to VGA_G[1]
-set_location_assignment PIN_C10 -to VGA_G[2]
-set_location_assignment PIN_D10 -to VGA_G[3]
-set_location_assignment PIN_B10 -to VGA_G[4]
-set_location_assignment PIN_A10 -to VGA_G[5]
-set_location_assignment PIN_G11 -to VGA_G[6]
-set_location_assignment PIN_D11 -to VGA_G[7]
-set_location_assignment PIN_E12 -to VGA_G[8]
-set_location_assignment PIN_D12 -to VGA_G[9]
-set_location_assignment PIN_J13 -to VGA_B[0]
-set_location_assignment PIN_J14 -to VGA_B[1]
-set_location_assignment PIN_F12 -to VGA_B[2]
-set_location_assignment PIN_G12 -to VGA_B[3]
-set_location_assignment PIN_J10 -to VGA_B[4]
-set_location_assignment PIN_J11 -to VGA_B[5]
-set_location_assignment PIN_C11 -to VGA_B[6]
-set_location_assignment PIN_B11 -to VGA_B[7]
-set_location_assignment PIN_C12 -to VGA_B[8]
-set_location_assignment PIN_B12 -to VGA_B[9]
-set_location_assignment PIN_B8 -to VGA_CLK
-set_location_assignment PIN_D6 -to VGA_BLANK
-set_location_assignment PIN_A7 -to VGA_HS
-set_location_assignment PIN_D8 -to VGA_VS
-set_location_assignment PIN_B7 -to VGA_SYNC
-set_location_assignment PIN_A6 -to I2C_SCLK
-set_location_assignment PIN_B6 -to I2C_SDAT
-set_location_assignment PIN_J9 -to TD_DATA[0]
-set_location_assignment PIN_E8 -to TD_DATA[1]
-set_location_assignment PIN_H8 -to TD_DATA[2]
-set_location_assignment PIN_H10 -to TD_DATA[3]
-set_location_assignment PIN_G9 -to TD_DATA[4]
-set_location_assignment PIN_F9 -to TD_DATA[5]
-set_location_assignment PIN_D7 -to TD_DATA[6]
-set_location_assignment PIN_C7 -to TD_DATA[7]
-set_location_assignment PIN_D5 -to TD_HS
-set_location_assignment PIN_K9 -to TD_VS
-set_location_assignment PIN_C5 -to AUD_ADCLRCK
-set_location_assignment PIN_B5 -to AUD_ADCDAT
-set_location_assignment PIN_C6 -to AUD_DACLRCK
-set_location_assignment PIN_A4 -to AUD_DACDAT
-set_location_assignment PIN_A5 -to AUD_XCK
-set_location_assignment PIN_B4 -to AUD_BCLK
-set_location_assignment PIN_D17 -to ENET_DATA[0]
-set_location_assignment PIN_C17 -to ENET_DATA[1]
-set_location_assignment PIN_B18 -to ENET_DATA[2]
-set_location_assignment PIN_A18 -to ENET_DATA[3]
-set_location_assignment PIN_B17 -to ENET_DATA[4]
-set_location_assignment PIN_A17 -to ENET_DATA[5]
-set_location_assignment PIN_B16 -to ENET_DATA[6]
-set_location_assignment PIN_B15 -to ENET_DATA[7]
-set_location_assignment PIN_B20 -to ENET_DATA[8]
-set_location_assignment PIN_A20 -to ENET_DATA[9]
-set_location_assignment PIN_C19 -to ENET_DATA[10]
-set_location_assignment PIN_D19 -to ENET_DATA[11]
-set_location_assignment PIN_B19 -to ENET_DATA[12]
-set_location_assignment PIN_A19 -to ENET_DATA[13]
-set_location_assignment PIN_E18 -to ENET_DATA[14]
-set_location_assignment PIN_D18 -to ENET_DATA[15]
-set_location_assignment PIN_B24 -to ENET_CLK
-set_location_assignment PIN_A21 -to ENET_CMD
-set_location_assignment PIN_A23 -to ENET_CS_N
-set_location_assignment PIN_B21 -to ENET_INT
-set_location_assignment PIN_A22 -to ENET_RD_N
-set_location_assignment PIN_B22 -to ENET_WR_N
-set_location_assignment PIN_B23 -to ENET_RST_N
-set_location_assignment PIN_AE24 -to IRDA_TXD
-set_location_assignment PIN_AE25 -to IRDA_RXD
-set_location_assignment PIN_AD24 -to SD_DAT
-set_location_assignment PIN_AC23 -to SD_DAT3
-set_location_assignment PIN_Y21 -to SD_CMD
-set_location_assignment PIN_AD25 -to SD_CLK
-set_location_assignment PIN_D25 -to GPIO_0[0]
-set_location_assignment PIN_J22 -to GPIO_0[1]
-set_location_assignment PIN_E26 -to GPIO_0[2]
-set_location_assignment PIN_E25 -to GPIO_0[3]
-set_location_assignment PIN_F24 -to GPIO_0[4]
-set_location_assignment PIN_F23 -to GPIO_0[5]
-set_location_assignment PIN_J21 -to GPIO_0[6]
-set_location_assignment PIN_J20 -to GPIO_0[7]
-set_location_assignment PIN_F25 -to GPIO_0[8]
-set_location_assignment PIN_F26 -to GPIO_0[9]
-set_location_assignment PIN_N18 -to GPIO_0[10]
-set_location_assignment PIN_P18 -to GPIO_0[11]
-set_location_assignment PIN_G23 -to GPIO_0[12]
-set_location_assignment PIN_G24 -to GPIO_0[13]
-set_location_assignment PIN_K22 -to GPIO_0[14]
-set_location_assignment PIN_G25 -to GPIO_0[15]
-set_location_assignment PIN_H23 -to GPIO_0[16]
-set_location_assignment PIN_H24 -to GPIO_0[17]
-set_location_assignment PIN_J23 -to GPIO_0[18]
-set_location_assignment PIN_J24 -to GPIO_0[19]
-set_location_assignment PIN_H25 -to GPIO_0[20]
-set_location_assignment PIN_H26 -to GPIO_0[21]
-set_location_assignment PIN_H19 -to GPIO_0[22]
-set_location_assignment PIN_K18 -to GPIO_0[23]
-set_location_assignment PIN_K19 -to GPIO_0[24]
-set_location_assignment PIN_K21 -to GPIO_0[25]
-set_location_assignment PIN_K23 -to GPIO_0[26]
-set_location_assignment PIN_K24 -to GPIO_0[27]
-set_location_assignment PIN_L21 -to GPIO_0[28]
-set_location_assignment PIN_L20 -to GPIO_0[29]
-set_location_assignment PIN_J25 -to GPIO_0[30]
-set_location_assignment PIN_J26 -to GPIO_0[31]
-set_location_assignment PIN_L23 -to GPIO_0[32]
-set_location_assignment PIN_L24 -to GPIO_0[33]
-set_location_assignment PIN_L25 -to GPIO_0[34]
-set_location_assignment PIN_L19 -to GPIO_0[35]
-set_location_assignment PIN_K25 -to GPIO_1[0]
-set_location_assignment PIN_K26 -to GPIO_1[1]
-set_location_assignment PIN_M22 -to GPIO_1[2]
-set_location_assignment PIN_M23 -to GPIO_1[3]
-set_location_assignment PIN_M19 -to GPIO_1[4]
-set_location_assignment PIN_M20 -to GPIO_1[5]
-set_location_assignment PIN_N20 -to GPIO_1[6]
-set_location_assignment PIN_M21 -to GPIO_1[7]
-set_location_assignment PIN_M24 -to GPIO_1[8]
-set_location_assignment PIN_M25 -to GPIO_1[9]
-set_location_assignment PIN_N24 -to GPIO_1[10]
-set_location_assignment PIN_P24 -to GPIO_1[11]
-set_location_assignment PIN_R25 -to GPIO_1[12]
-set_location_assignment PIN_R24 -to GPIO_1[13]
-set_location_assignment PIN_R20 -to GPIO_1[14]
-set_location_assignment PIN_T22 -to GPIO_1[15]
-set_location_assignment PIN_T23 -to GPIO_1[16]
-set_location_assignment PIN_T24 -to GPIO_1[17]
-set_location_assignment PIN_T25 -to GPIO_1[18]
-set_location_assignment PIN_T18 -to GPIO_1[19]
-set_location_assignment PIN_T21 -to GPIO_1[20]
-set_location_assignment PIN_T20 -to GPIO_1[21]
-set_location_assignment PIN_U26 -to GPIO_1[22]
-set_location_assignment PIN_U25 -to GPIO_1[23]
-set_location_assignment PIN_U23 -to GPIO_1[24]
-set_location_assignment PIN_U24 -to GPIO_1[25]
-set_location_assignment PIN_R19 -to GPIO_1[26]
-set_location_assignment PIN_T19 -to GPIO_1[27]
-set_location_assignment PIN_U20 -to GPIO_1[28]
-set_location_assignment PIN_U21 -to GPIO_1[29]
-set_location_assignment PIN_V26 -to GPIO_1[30]
-set_location_assignment PIN_V25 -to GPIO_1[31]
-set_location_assignment PIN_V24 -to GPIO_1[32]
-set_location_assignment PIN_V23 -to GPIO_1[33]
-set_location_assignment PIN_W25 -to GPIO_1[34]
-set_location_assignment PIN_W23 -to GPIO_1[35]
-
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-
-set_global_assignment -name IGNORE_CLOCK_SETTINGS ON
-set_global_assignment -name FMAX_REQUIREMENT "50 MHz"
-set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to *
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to *
-set_instance_assignment -name TSU_REQUIREMENT "10 ns" -from * -to *
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to *
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to I2C_SCLK
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to I2C_SDAT
-
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/constraints/Nexys4_Master.xdc b/constraints/Nexys4_Master.xdc
deleted file mode 100644
index 0d6ebb4c09c0801c593f0460952d8b25c2525708..0000000000000000000000000000000000000000
--- a/constraints/Nexys4_Master.xdc
+++ /dev/null
@@ -1,492 +0,0 @@
-
-####################################################################################
-# Generated by PlanAhead 14.7 built on 'Fri Sep 27 19:29:51 MDT 2013' by 'xbuild'
-####################################################################################
-
-
-####################################################################################
-# Constraints from file : 'Nexys4UserDemo.ucf'
-####################################################################################
-
-#Nexys4 User Demo User Constraint File
-# System Clock, 100MHz
-set_property PACKAGE_PIN E3 [get_ports clk_i]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'clk_i' has been applied to the port object 'clk_i'.
-set_property IOSTANDARD LVCMOS33 [get_ports clk_i]
-# Active-Low Reset, CPU_RESET button
-set_property PACKAGE_PIN C12 [get_ports rstn_i]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'rstn_i' has been applied to the port object 'rstn_i'.
-set_property IOSTANDARD LVCMOS33 [get_ports rstn_i]
-
-# Pushbuttons
-set_property PACKAGE_PIN T16 [get_ports btnl_i]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'btnl_i' has been applied to the port object 'btnl_i'.
-set_property IOSTANDARD LVCMOS33 [get_ports btnl_i]
-set_property PACKAGE_PIN E16 [get_ports btnc_i]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'btnc_i' has been applied to the port object 'btnc_i'.
-set_property IOSTANDARD LVCMOS33 [get_ports btnc_i]
-set_property PACKAGE_PIN R10 [get_ports btnr_i]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'btnr_i' has been applied to the port object 'btnr_i'.
-set_property IOSTANDARD LVCMOS33 [get_ports btnr_i]
-set_property PACKAGE_PIN V10 [get_ports btnd_i]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'btnd_i' has been applied to the port object 'btnd_i'.
-set_property IOSTANDARD LVCMOS33 [get_ports btnd_i]
-set_property PACKAGE_PIN F15 [get_ports btnu_i]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'btnu_i' has been applied to the port object 'btnu_i'.
-set_property IOSTANDARD LVCMOS33 [get_ports btnu_i]
-
-set_property PACKAGE_PIN U9 [get_ports {sw_i[0]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[0]' has been applied to the port object 'sw_i[0]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[0]}]
-set_property PACKAGE_PIN U8 [get_ports {sw_i[1]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[1]' has been applied to the port object 'sw_i[1]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[1]}]
-set_property PACKAGE_PIN R7 [get_ports {sw_i[2]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[2]' has been applied to the port object 'sw_i[2]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[2]}]
-set_property PACKAGE_PIN R6 [get_ports {sw_i[3]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[3]' has been applied to the port object 'sw_i[3]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[3]}]
-set_property PACKAGE_PIN R5 [get_ports {sw_i[4]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[4]' has been applied to the port object 'sw_i[4]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[4]}]
-set_property PACKAGE_PIN V7 [get_ports {sw_i[5]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[5]' has been applied to the port object 'sw_i[5]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[5]}]
-set_property PACKAGE_PIN V6 [get_ports {sw_i[6]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[6]' has been applied to the port object 'sw_i[6]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[6]}]
-set_property PACKAGE_PIN V5 [get_ports {sw_i[7]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[7]' has been applied to the port object 'sw_i[7]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[7]}]
-set_property PACKAGE_PIN U4 [get_ports {sw_i[8]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[8]' has been applied to the port object 'sw_i[8]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[8]}]
-set_property PACKAGE_PIN V2 [get_ports {sw_i[9]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[9]' has been applied to the port object 'sw_i[9]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[9]}]
-set_property PACKAGE_PIN U2 [get_ports {sw_i[10]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[10]' has been applied to the port object 'sw_i[10]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[10]}]
-set_property PACKAGE_PIN T3 [get_ports {sw_i[11]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[11]' has been applied to the port object 'sw_i[11]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[11]}]
-set_property PACKAGE_PIN T1 [get_ports {sw_i[12]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[12]' has been applied to the port object 'sw_i[12]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[12]}]
-set_property PACKAGE_PIN R3 [get_ports {sw_i[13]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[13]' has been applied to the port object 'sw_i[13]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[13]}]
-set_property PACKAGE_PIN P3 [get_ports {sw_i[14]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[14]' has been applied to the port object 'sw_i[14]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[14]}]
-set_property PACKAGE_PIN P4 [get_ports {sw_i[15]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sw_i[15]' has been applied to the port object 'sw_i[15]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {sw_i[15]}]
-
-# ADT7420 Temperature Sensor TWI Signals
-#NET "tmp_ct" LOC = "C14" |IOSTANDARD=LVCMOS33 | PULLUP;
-#NET "tmp_int" LOC = "D14" |IOSTANDARD=LVCMOS33 | PULLUP;
-set_property PACKAGE_PIN F16 [get_ports tmp_scl]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'tmp_scl' has been applied to the port object 'tmp_scl'.
-set_property IOSTANDARD LVCMOS33 [get_ports tmp_scl]
-set_property PACKAGE_PIN G16 [get_ports tmp_sda]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'tmp_sda' has been applied to the port object 'tmp_sda'.
-set_property IOSTANDARD LVCMOS33 [get_ports tmp_sda]
-
-# ADXL362 Accelerometer SPI Signals
-set_property PACKAGE_PIN C15 [get_ports ss]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'ss' has been applied to the port object 'ss'.
-set_property IOSTANDARD LVCMOS33 [get_ports ss]
-set_property PACKAGE_PIN D13 [get_ports miso]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'miso' has been applied to the port object 'miso'.
-set_property IOSTANDARD LVCMOS33 [get_ports miso]
-set_property PACKAGE_PIN B14 [get_ports mosi]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'mosi' has been applied to the port object 'mosi'.
-set_property IOSTANDARD LVCMOS33 [get_ports mosi]
-set_property PACKAGE_PIN D15 [get_ports sclk]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'sclk' has been applied to the port object 'sclk'.
-set_property IOSTANDARD LVCMOS33 [get_ports sclk]
-
-# 8-Digit Seven-Segment Display Segments
-set_property PACKAGE_PIN L3 [get_ports {disp_seg_o[0]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_seg_o[0]' has been applied to the port object 'disp_seg_o[0]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_seg_o[0]}]
-set_property PACKAGE_PIN N1 [get_ports {disp_seg_o[1]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_seg_o[1]' has been applied to the port object 'disp_seg_o[1]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_seg_o[1]}]
-set_property PACKAGE_PIN L5 [get_ports {disp_seg_o[2]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_seg_o[2]' has been applied to the port object 'disp_seg_o[2]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_seg_o[2]}]
-set_property PACKAGE_PIN L4 [get_ports {disp_seg_o[3]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_seg_o[3]' has been applied to the port object 'disp_seg_o[3]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_seg_o[3]}]
-set_property PACKAGE_PIN K3 [get_ports {disp_seg_o[4]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_seg_o[4]' has been applied to the port object 'disp_seg_o[4]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_seg_o[4]}]
-set_property PACKAGE_PIN M2 [get_ports {disp_seg_o[5]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_seg_o[5]' has been applied to the port object 'disp_seg_o[5]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_seg_o[5]}]
-set_property PACKAGE_PIN L6 [get_ports {disp_seg_o[6]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_seg_o[6]' has been applied to the port object 'disp_seg_o[6]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_seg_o[6]}]
-#DP
-set_property PACKAGE_PIN M4 [get_ports {disp_seg_o[7]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_seg_o[7]' has been applied to the port object 'disp_seg_o[7]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_seg_o[7]}]
-# 8-Digit Seven-Segment Display Anodes, Active-Low
-set_property PACKAGE_PIN N6 [get_ports {disp_an_o[0]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_an_o[0]' has been applied to the port object 'disp_an_o[0]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_an_o[0]}]
-set_property PACKAGE_PIN M6 [get_ports {disp_an_o[1]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_an_o[1]' has been applied to the port object 'disp_an_o[1]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_an_o[1]}]
-set_property PACKAGE_PIN M3 [get_ports {disp_an_o[2]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_an_o[2]' has been applied to the port object 'disp_an_o[2]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_an_o[2]}]
-set_property PACKAGE_PIN N5 [get_ports {disp_an_o[3]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_an_o[3]' has been applied to the port object 'disp_an_o[3]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_an_o[3]}]
-set_property PACKAGE_PIN N2 [get_ports {disp_an_o[4]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_an_o[4]' has been applied to the port object 'disp_an_o[4]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_an_o[4]}]
-set_property PACKAGE_PIN N4 [get_ports {disp_an_o[5]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_an_o[5]' has been applied to the port object 'disp_an_o[5]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_an_o[5]}]
-set_property PACKAGE_PIN L1 [get_ports {disp_an_o[6]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_an_o[6]' has been applied to the port object 'disp_an_o[6]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_an_o[6]}]
-set_property PACKAGE_PIN M1 [get_ports {disp_an_o[7]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'disp_an_o[7]' has been applied to the port object 'disp_an_o[7]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {disp_an_o[7]}]
-
-# LD16 RGB LED Signals
-set_property PACKAGE_PIN K5 [get_ports rgb1_red_o]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'rgb1_red_o' has been applied to the port object 'rgb1_red_o'.
-set_property IOSTANDARD LVCMOS33 [get_ports rgb1_red_o]
-set_property PACKAGE_PIN F13 [get_ports rgb1_green_o]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'rgb1_green_o' has been applied to the port object 'rgb1_green_o'.
-set_property IOSTANDARD LVCMOS33 [get_ports rgb1_green_o]
-set_property PACKAGE_PIN F6 [get_ports rgb1_blue_o]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'rgb1_blue_o' has been applied to the port object 'rgb1_blue_o'.
-set_property IOSTANDARD LVCMOS33 [get_ports rgb1_blue_o]
-# LD17 RGB LED Signals
-set_property PACKAGE_PIN K6 [get_ports rgb2_red_o]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'rgb2_red_o' has been applied to the port object 'rgb2_red_o'.
-set_property IOSTANDARD LVCMOS33 [get_ports rgb2_red_o]
-set_property PACKAGE_PIN H6 [get_ports rgb2_green_o]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'rgb2_green_o' has been applied to the port object 'rgb2_green_o'.
-set_property IOSTANDARD LVCMOS33 [get_ports rgb2_green_o]
-set_property PACKAGE_PIN L16 [get_ports rgb2_blue_o]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'rgb2_blue_o' has been applied to the port object 'rgb2_blue_o'.
-set_property IOSTANDARD LVCMOS33 [get_ports rgb2_blue_o]
-# LEDs
-set_property PACKAGE_PIN T8 [get_ports {led_o[0]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[0]' has been applied to the port object 'led_o[0]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[0]}]
-set_property PACKAGE_PIN V9 [get_ports {led_o[1]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[1]' has been applied to the port object 'led_o[1]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[1]}]
-set_property PACKAGE_PIN R8 [get_ports {led_o[2]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[2]' has been applied to the port object 'led_o[2]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[2]}]
-set_property PACKAGE_PIN T6 [get_ports {led_o[3]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[3]' has been applied to the port object 'led_o[3]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[3]}]
-set_property PACKAGE_PIN T5 [get_ports {led_o[4]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[4]' has been applied to the port object 'led_o[4]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[4]}]
-set_property PACKAGE_PIN T4 [get_ports {led_o[5]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[5]' has been applied to the port object 'led_o[5]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[5]}]
-set_property PACKAGE_PIN U7 [get_ports {led_o[6]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[6]' has been applied to the port object 'led_o[6]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[6]}]
-set_property PACKAGE_PIN U6 [get_ports {led_o[7]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[7]' has been applied to the port object 'led_o[7]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[7]}]
-set_property PACKAGE_PIN V4 [get_ports {led_o[8]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[8]' has been applied to the port object 'led_o[8]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[8]}]
-set_property PACKAGE_PIN U3 [get_ports {led_o[9]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[9]' has been applied to the port object 'led_o[9]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[9]}]
-set_property PACKAGE_PIN V1 [get_ports {led_o[10]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[10]' has been applied to the port object 'led_o[10]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[10]}]
-set_property PACKAGE_PIN R1 [get_ports {led_o[11]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[11]' has been applied to the port object 'led_o[11]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[11]}]
-set_property PACKAGE_PIN P5 [get_ports {led_o[12]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[12]' has been applied to the port object 'led_o[12]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[12]}]
-set_property PACKAGE_PIN U1 [get_ports {led_o[13]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[13]' has been applied to the port object 'led_o[13]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[13]}]
-set_property PACKAGE_PIN R2 [get_ports {led_o[14]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[14]' has been applied to the port object 'led_o[14]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[14]}]
-set_property PACKAGE_PIN P2 [get_ports {led_o[15]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'led_o[15]' has been applied to the port object 'led_o[15]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {led_o[15]}]
-
-# VGA Signals
-set_property PACKAGE_PIN A3 [get_ports {vga_red_o[0]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_red_o[0]' has been applied to the port object 'vga_red_o[0]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_red_o[0]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_red_o[0]' has been applied to the port object 'vga_red_o[0]'.
-set_property SLEW FAST [get_ports {vga_red_o[0]}]
-set_property PACKAGE_PIN B4 [get_ports {vga_red_o[1]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_red_o[1]' has been applied to the port object 'vga_red_o[1]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_red_o[1]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_red_o[1]' has been applied to the port object 'vga_red_o[1]'.
-set_property SLEW FAST [get_ports {vga_red_o[1]}]
-set_property PACKAGE_PIN C5 [get_ports {vga_red_o[2]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_red_o[2]' has been applied to the port object 'vga_red_o[2]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_red_o[2]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_red_o[2]' has been applied to the port object 'vga_red_o[2]'.
-set_property SLEW FAST [get_ports {vga_red_o[2]}]
-set_property PACKAGE_PIN A4 [get_ports {vga_red_o[3]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_red_o[3]' has been applied to the port object 'vga_red_o[3]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_red_o[3]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_red_o[3]' has been applied to the port object 'vga_red_o[3]'.
-set_property SLEW FAST [get_ports {vga_red_o[3]}]
-set_property PACKAGE_PIN B7 [get_ports {vga_blue_o[0]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_blue_o[0]' has been applied to the port object 'vga_blue_o[0]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue_o[0]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_blue_o[0]' has been applied to the port object 'vga_blue_o[0]'.
-set_property SLEW FAST [get_ports {vga_blue_o[0]}]
-set_property PACKAGE_PIN C7 [get_ports {vga_blue_o[1]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_blue_o[1]' has been applied to the port object 'vga_blue_o[1]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue_o[1]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_blue_o[1]' has been applied to the port object 'vga_blue_o[1]'.
-set_property SLEW FAST [get_ports {vga_blue_o[1]}]
-set_property PACKAGE_PIN D7 [get_ports {vga_blue_o[2]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_blue_o[2]' has been applied to the port object 'vga_blue_o[2]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue_o[2]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_blue_o[2]' has been applied to the port object 'vga_blue_o[2]'.
-set_property SLEW FAST [get_ports {vga_blue_o[2]}]
-set_property PACKAGE_PIN D8 [get_ports {vga_blue_o[3]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_blue_o[3]' has been applied to the port object 'vga_blue_o[3]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue_o[3]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_blue_o[3]' has been applied to the port object 'vga_blue_o[3]'.
-set_property SLEW FAST [get_ports {vga_blue_o[3]}]
-set_property PACKAGE_PIN C6 [get_ports {vga_green_o[0]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_green_o[0]' has been applied to the port object 'vga_green_o[0]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_green_o[0]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_green_o[0]' has been applied to the port object 'vga_green_o[0]'.
-set_property SLEW FAST [get_ports {vga_green_o[0]}]
-set_property PACKAGE_PIN A5 [get_ports {vga_green_o[1]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_green_o[1]' has been applied to the port object 'vga_green_o[1]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_green_o[1]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_green_o[1]' has been applied to the port object 'vga_green_o[1]'.
-set_property SLEW FAST [get_ports {vga_green_o[1]}]
-set_property PACKAGE_PIN B6 [get_ports {vga_green_o[2]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_green_o[2]' has been applied to the port object 'vga_green_o[2]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_green_o[2]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_green_o[2]' has been applied to the port object 'vga_green_o[2]'.
-set_property SLEW FAST [get_ports {vga_green_o[2]}]
-set_property PACKAGE_PIN A6 [get_ports {vga_green_o[3]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_green_o[3]' has been applied to the port object 'vga_green_o[3]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_green_o[3]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_green_o[3]' has been applied to the port object 'vga_green_o[3]'.
-set_property SLEW FAST [get_ports {vga_green_o[3]}]
-set_property PACKAGE_PIN B11 [get_ports vga_hs_o]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_hs_o' has been applied to the port object 'vga_hs_o'.
-set_property IOSTANDARD LVCMOS33 [get_ports vga_hs_o]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_hs_o' has been applied to the port object 'vga_hs_o'.
-set_property SLEW FAST [get_ports vga_hs_o]
-set_property PACKAGE_PIN B12 [get_ports vga_vs_o]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_vs_o' has been applied to the port object 'vga_vs_o'.
-set_property IOSTANDARD LVCMOS33 [get_ports vga_vs_o]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_vs_o' has been applied to the port object 'vga_vs_o'.
-set_property SLEW FAST [get_ports vga_vs_o]
-
-# ADMP421 Omnidirectional Microphone Signals
-set_property PACKAGE_PIN J5 [get_ports pdm_clk_o]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'pdm_clk_o' has been applied to the port object 'pdm_clk_o'.
-set_property IOSTANDARD LVCMOS33 [get_ports pdm_clk_o]
-set_property PACKAGE_PIN H5 [get_ports pdm_data_i]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'pdm_data_i' has been applied to the port object 'pdm_data_i'.
-set_property IOSTANDARD LVCMOS33 [get_ports pdm_data_i]
-set_property PACKAGE_PIN F5 [get_ports pdm_lrsel_o]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'pdm_lrsel_o' has been applied to the port object 'pdm_lrsel_o'.
-set_property IOSTANDARD LVCMOS33 [get_ports pdm_lrsel_o]
-
-# Audio Out Signals
-set_property PACKAGE_PIN A11 [get_ports pwm_audio_o]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'pwm_audio_o' has been applied to the port object 'pwm_audio_o'.
-set_property IOSTANDARD LVCMOS33 [get_ports pwm_audio_o]
-set_property PACKAGE_PIN D12 [get_ports pwm_sdaudio_o]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'pwm_sdaudio_o' has been applied to the port object 'pwm_sdaudio_o'.
-set_property IOSTANDARD LVCMOS33 [get_ports pwm_sdaudio_o]
-
-# PSRAM Memory Signals
-set_property PACKAGE_PIN J18 [get_ports {Mem_A[0]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[0]' has been applied to the port object 'Mem_A[0]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[0]}]
-set_property PACKAGE_PIN H17 [get_ports {Mem_A[1]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[1]' has been applied to the port object 'Mem_A[1]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[1]}]
-set_property PACKAGE_PIN H15 [get_ports {Mem_A[2]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[2]' has been applied to the port object 'Mem_A[2]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[2]}]
-set_property PACKAGE_PIN J17 [get_ports {Mem_A[3]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[3]' has been applied to the port object 'Mem_A[3]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[3]}]
-set_property PACKAGE_PIN H16 [get_ports {Mem_A[4]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[4]' has been applied to the port object 'Mem_A[4]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[4]}]
-set_property PACKAGE_PIN K15 [get_ports {Mem_A[5]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[5]' has been applied to the port object 'Mem_A[5]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[5]}]
-set_property PACKAGE_PIN K13 [get_ports {Mem_A[6]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[6]' has been applied to the port object 'Mem_A[6]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[6]}]
-set_property PACKAGE_PIN N15 [get_ports {Mem_A[7]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[7]' has been applied to the port object 'Mem_A[7]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[7]}]
-set_property PACKAGE_PIN V16 [get_ports {Mem_A[8]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[8]' has been applied to the port object 'Mem_A[8]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[8]}]
-set_property PACKAGE_PIN U14 [get_ports {Mem_A[9]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[9]' has been applied to the port object 'Mem_A[9]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[9]}]
-set_property PACKAGE_PIN V14 [get_ports {Mem_A[10]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[10]' has been applied to the port object 'Mem_A[10]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[10]}]
-set_property PACKAGE_PIN V12 [get_ports {Mem_A[11]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[11]' has been applied to the port object 'Mem_A[11]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[11]}]
-set_property PACKAGE_PIN P14 [get_ports {Mem_A[12]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[12]' has been applied to the port object 'Mem_A[12]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[12]}]
-set_property PACKAGE_PIN U16 [get_ports {Mem_A[13]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[13]' has been applied to the port object 'Mem_A[13]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[13]}]
-set_property PACKAGE_PIN R15 [get_ports {Mem_A[14]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[14]' has been applied to the port object 'Mem_A[14]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[14]}]
-set_property PACKAGE_PIN N14 [get_ports {Mem_A[15]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[15]' has been applied to the port object 'Mem_A[15]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[15]}]
-set_property PACKAGE_PIN N16 [get_ports {Mem_A[16]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[16]' has been applied to the port object 'Mem_A[16]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[16]}]
-set_property PACKAGE_PIN M13 [get_ports {Mem_A[17]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[17]' has been applied to the port object 'Mem_A[17]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[17]}]
-set_property PACKAGE_PIN V17 [get_ports {Mem_A[18]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[18]' has been applied to the port object 'Mem_A[18]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[18]}]
-set_property PACKAGE_PIN U17 [get_ports {Mem_A[19]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[19]' has been applied to the port object 'Mem_A[19]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[19]}]
-set_property PACKAGE_PIN T10 [get_ports {Mem_A[20]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[20]' has been applied to the port object 'Mem_A[20]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[20]}]
-set_property PACKAGE_PIN M16 [get_ports {Mem_A[21]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[21]' has been applied to the port object 'Mem_A[21]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[21]}]
-set_property PACKAGE_PIN U13 [get_ports {Mem_A[22]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_A[22]' has been applied to the port object 'Mem_A[22]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_A[22]}]
-set_property PACKAGE_PIN R11 [get_ports Mem_WEN]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_WEN' has been applied to the port object 'Mem_WEN'.
-set_property IOSTANDARD LVCMOS33 [get_ports Mem_WEN]
-set_property PACKAGE_PIN H14 [get_ports Mem_OEN]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_OEN' has been applied to the port object 'Mem_OEN'.
-set_property IOSTANDARD LVCMOS33 [get_ports Mem_OEN]
-set_property PACKAGE_PIN L18 [get_ports Mem_CEN]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_CEN' has been applied to the port object 'Mem_CEN'.
-set_property IOSTANDARD LVCMOS33 [get_ports Mem_CEN]
-set_property PACKAGE_PIN J13 [get_ports Mem_UB]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_UB' has been applied to the port object 'Mem_UB'.
-set_property IOSTANDARD LVCMOS33 [get_ports Mem_UB]
-set_property PACKAGE_PIN J15 [get_ports Mem_LB]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_LB' has been applied to the port object 'Mem_LB'.
-set_property IOSTANDARD LVCMOS33 [get_ports Mem_LB]
-set_property PACKAGE_PIN T15 [get_ports Mem_CLK]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_CLK' has been applied to the port object 'Mem_CLK'.
-set_property IOSTANDARD LVCMOS33 [get_ports Mem_CLK]
-set_property PACKAGE_PIN T13 [get_ports Mem_ADV]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_ADV' has been applied to the port object 'Mem_ADV'.
-set_property IOSTANDARD LVCMOS33 [get_ports Mem_ADV]
-set_property PACKAGE_PIN J14 [get_ports Mem_CRE]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_CRE' has been applied to the port object 'Mem_CRE'.
-set_property IOSTANDARD LVCMOS33 [get_ports Mem_CRE]
-set_property PACKAGE_PIN R12 [get_ports {Mem_DQ[0]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[0]' has been applied to the port object 'Mem_DQ[0]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[0]}]
-set_property PACKAGE_PIN T11 [get_ports {Mem_DQ[1]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[1]' has been applied to the port object 'Mem_DQ[1]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[1]}]
-set_property PACKAGE_PIN U12 [get_ports {Mem_DQ[2]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[2]' has been applied to the port object 'Mem_DQ[2]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[2]}]
-set_property PACKAGE_PIN R13 [get_ports {Mem_DQ[3]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[3]' has been applied to the port object 'Mem_DQ[3]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[3]}]
-set_property PACKAGE_PIN U18 [get_ports {Mem_DQ[4]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[4]' has been applied to the port object 'Mem_DQ[4]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[4]}]
-set_property PACKAGE_PIN R17 [get_ports {Mem_DQ[5]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[5]' has been applied to the port object 'Mem_DQ[5]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[5]}]
-set_property PACKAGE_PIN T18 [get_ports {Mem_DQ[6]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[6]' has been applied to the port object 'Mem_DQ[6]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[6]}]
-set_property PACKAGE_PIN R18 [get_ports {Mem_DQ[7]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[7]' has been applied to the port object 'Mem_DQ[7]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[7]}]
-set_property PACKAGE_PIN F18 [get_ports {Mem_DQ[8]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[8]' has been applied to the port object 'Mem_DQ[8]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[8]}]
-set_property PACKAGE_PIN G18 [get_ports {Mem_DQ[9]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[9]' has been applied to the port object 'Mem_DQ[9]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[9]}]
-set_property PACKAGE_PIN G17 [get_ports {Mem_DQ[10]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[10]' has been applied to the port object 'Mem_DQ[10]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[10]}]
-set_property PACKAGE_PIN M18 [get_ports {Mem_DQ[11]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[11]' has been applied to the port object 'Mem_DQ[11]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[11]}]
-set_property PACKAGE_PIN M17 [get_ports {Mem_DQ[12]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[12]' has been applied to the port object 'Mem_DQ[12]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[12]}]
-set_property PACKAGE_PIN P18 [get_ports {Mem_DQ[13]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[13]' has been applied to the port object 'Mem_DQ[13]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[13]}]
-set_property PACKAGE_PIN N17 [get_ports {Mem_DQ[14]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[14]' has been applied to the port object 'Mem_DQ[14]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[14]}]
-set_property PACKAGE_PIN P17 [get_ports {Mem_DQ[15]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Mem_DQ[15]' has been applied to the port object 'Mem_DQ[15]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Mem_DQ[15]}]
-
-# PS2 Signals
-set_property PACKAGE_PIN F4 [get_ports ps2_clk]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'ps2_clk' has been applied to the port object 'ps2_clk'.
-set_property IOSTANDARD LVCMOS33 [get_ports ps2_clk]
-# The conversion of 'PULL' constraint on 'net' object 'ps2_clk' has been applied to the port object 'ps2_clk'.
-set_property PULLUP true [get_ports ps2_clk]
-set_property PACKAGE_PIN B2 [get_ports ps2_data]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'ps2_data' has been applied to the port object 'ps2_data'.
-set_property IOSTANDARD LVCMOS33 [get_ports ps2_data]
-# The conversion of 'PULL' constraint on 'net' object 'ps2_data' has been applied to the port object 'ps2_data'.
-set_property PULLUP true [get_ports ps2_data]
-
-# Incoming System Clock PERIOD Constraint
-
-# All timing constraint translations are rough conversions, intended to act as a template for further manual refinement. The translations should not be expected to produce semantically identical results to the original ucf. Each xdc timing constraint must be manually inspected and verified to ensure it captures the desired intent
-
-create_clock -name clk_i -period 10.000 [get_ports clk_i]
-
-# Ignore Clock Domain Crossing signals
-# These signals are coming from the 100MHz clock domain
-# ant are not time-critical: RGB LED, Temperature, Accelerometer
-# and Mouse Controller data, going to the 108Mhz clock domain, the VGA display controller
-
-# Define a new TNM for a FROM - TO constraint
-
-get_false_path -from [all_fanout -endpoints_only -only_cells -flat -from [get_nets clk_i]] -to [all_fanout -endpoints_only -flat -from [get_nets Inst_VGA/pxl_clk]]
diff --git a/constraints/nexys4_wrapper.xdc b/constraints/nexys4_wrapper.xdc
deleted file mode 100644
index 6a8360f6dfb381fd49ca2de4e39d30b03fd95060..0000000000000000000000000000000000000000
--- a/constraints/nexys4_wrapper.xdc
+++ /dev/null
@@ -1,132 +0,0 @@
-## This file is a general .xdc for the Nexys4 rev B board
-## To use it in a project:
-## - uncomment the lines corresponding to used pins
-## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
-
-## Clock signal
-##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ
-set_property PACKAGE_PIN E3 [get_ports Clock]
-set_property IOSTANDARD LVCMOS33 [get_ports Clock]
-create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports Clock]
-create_clock -period 20.000 -name ahb_clock -waveform {1.000 11.000} [get_nets Clock50]
-
-## Buttons
-set_property PACKAGE_PIN C12 [get_ports nReset]
-set_property IOSTANDARD LVCMOS33 [get_ports nReset]
-
-# This is the top button in the cluster of 5
-set_property PACKAGE_PIN F15 [get_ports {Buttons[0]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Buttons[0]' has been applied to the port object 'Buttons[0]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Buttons[0]}]
-
-# This is the bottom button in the cluster of 5
-set_property PACKAGE_PIN V10 [get_ports {Buttons[1]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Buttons[1]' has been applied to the port object 'Buttons[1]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Buttons[1]}]
-
-## Switches
-set_property PACKAGE_PIN U9 [get_ports {Switches[0]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[0]' has been applied to the port object 'Switches[0]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[0]}]
-set_property PACKAGE_PIN U8 [get_ports {Switches[1]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[1]' has been applied to the port object 'Switches[1]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[1]}]
-set_property PACKAGE_PIN R7 [get_ports {Switches[2]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[2]' has been applied to the port object 'Switches[2]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[2]}]
-set_property PACKAGE_PIN R6 [get_ports {Switches[3]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[3]' has been applied to the port object 'Switches[3]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[3]}]
-set_property PACKAGE_PIN R5 [get_ports {Switches[4]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[4]' has been applied to the port object 'Switches[4]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[4]}]
-set_property PACKAGE_PIN V7 [get_ports {Switches[5]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[5]' has been applied to the port object 'Switches[5]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[5]}]
-set_property PACKAGE_PIN V6 [get_ports {Switches[6]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[6]' has been applied to the port object 'Switches[6]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[6]}]
-set_property PACKAGE_PIN V5 [get_ports {Switches[7]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[7]' has been applied to the port object 'Switches[7]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[7]}]
-set_property PACKAGE_PIN U4 [get_ports {Switches[8]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[8]' has been applied to the port object 'Switches[8]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[8]}]
-set_property PACKAGE_PIN V2 [get_ports {Switches[9]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[9]' has been applied to the port object 'Switches[9]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[9]}]
-set_property PACKAGE_PIN U2 [get_ports {Switches[10]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[10]' has been applied to the port object 'Switches[10]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[10]}]
-set_property PACKAGE_PIN T3 [get_ports {Switches[11]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[11]' has been applied to the port object 'Switches[11]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[11]}]
-set_property PACKAGE_PIN T1 [get_ports {Switches[12]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[12]' has been applied to the port object 'Switches[12]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[12]}]
-set_property PACKAGE_PIN R3 [get_ports {Switches[13]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[13]' has been applied to the port object 'Switches[13]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[13]}]
-set_property PACKAGE_PIN P3 [get_ports {Switches[14]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[14]' has been applied to the port object 'Switches[14]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[14]}]
-set_property PACKAGE_PIN P4 [get_ports {Switches[15]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'Switches[15]' has been applied to the port object 'Switches[15]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {Switches[15]}]
-
-
-## LEDs
-##Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0
-set_property PACKAGE_PIN T8 [get_ports {DataOut[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[0]}]
-##Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1
-set_property PACKAGE_PIN V9 [get_ports {DataOut[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[1]}]
-##Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2
-set_property PACKAGE_PIN R8 [get_ports {DataOut[2]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[2]}]
-##Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3
-set_property PACKAGE_PIN T6 [get_ports {DataOut[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[3]}]
-##Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4
-set_property PACKAGE_PIN T5 [get_ports {DataOut[4]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[4]}]
-##Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5
-set_property PACKAGE_PIN T4 [get_ports {DataOut[5]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[5]}]
-##Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6
-set_property PACKAGE_PIN U7 [get_ports {DataOut[6]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[6]}]
-##Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7
-set_property PACKAGE_PIN U6 [get_ports {DataOut[7]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[7]}]
-
-set_property PACKAGE_PIN V4 [get_ports {DataOut[8]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[8]}]
-set_property PACKAGE_PIN U3 [get_ports {DataOut[9]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[9]}]
-set_property PACKAGE_PIN V1 [get_ports {DataOut[10]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[10]}]
-set_property PACKAGE_PIN R1 [get_ports {DataOut[11]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[11]}]
-set_property PACKAGE_PIN P5 [get_ports {DataOut[12]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[12]}]
-set_property PACKAGE_PIN U1 [get_ports {DataOut[13]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[13]}]
-set_property PACKAGE_PIN R2 [get_ports {DataOut[14]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[14]}]
-set_property PACKAGE_PIN P2 [get_ports {DataOut[15]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {DataOut[15]}]
-
-# LD16 RGB LED Signals
-set_property PACKAGE_PIN K5 [get_ports Status_Red]
-set_property IOSTANDARD LVCMOS33 [get_ports Status_Red]
-set_property PACKAGE_PIN F13 [get_ports Status_Green]
-set_property IOSTANDARD LVCMOS33 [get_ports Status_Green]
-# LD17 RGB LED Signals
-set_property PACKAGE_PIN K6 [get_ports DataInvalid]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'DataInvalid' has been applied to the port object 'DataInvalid'.
-set_property IOSTANDARD LVCMOS33 [get_ports DataInvalid]
-set_property PACKAGE_PIN H6 [get_ports DataValid]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'DataValid' has been applied to the port object 'DataValid'.
-set_property IOSTANDARD LVCMOS33 [get_ports DataValid]
diff --git a/software/code/main.c b/software/code/main.c
index adfc7381aee98f56bbddd62550b1eeedd92a44c4..076eb4e473191ca03bbe0e5b5022f6b1457453e5 100644
--- a/software/code/main.c
+++ b/software/code/main.c
@@ -76,9 +76,9 @@ int main(void) {
int y1 = 0 ;
int x2 = 50;
- int y2 = 30;
+ int y2 = 300;
- int x3 = 50;
+ int x3 = 500;
int y3 = 70;
while(1) {