Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
V
VHDL
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Deploy
Releases
Package registry
Model registry
Operate
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
Jack Driscoll
VHDL
Commits
e4133d4f
Commit
e4133d4f
authored
7 months ago
by
Jack Driscoll
Browse files
Options
Downloads
Patches
Plain Diff
added invert signal and can insert errors for parity check
parent
775ccb99
No related branches found
No related tags found
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
MSF/MSF_decoder/tb/basic_msf_signal_tb.vhd
+32
-7
32 additions, 7 deletions
MSF/MSF_decoder/tb/basic_msf_signal_tb.vhd
with
32 additions
and
7 deletions
MSF/MSF_decoder/tb/basic_msf_signal_tb.vhd
+
32
−
7
View file @
e4133d4f
...
@@ -20,7 +20,7 @@ architecture basic_msf_signal of basic_msf_signal_tb is
...
@@ -20,7 +20,7 @@ architecture basic_msf_signal of basic_msf_signal_tb is
signal
fast_clk
:
std_logic
:
=
'0'
;
signal
fast_clk
:
std_logic
:
=
'0'
;
signal
rst
:
std_logic
:
=
'0'
;
signal
rst
:
std_logic
:
=
'0'
;
signal
read_next
:
std_logic
:
=
'0'
;
signal
read_next
:
std_logic
:
=
'0'
;
signal
h_filter_in
:
std_logic
:
=
'
1
'
;
signal
h_filter_in
:
std_logic
:
=
'
0
'
;
signal
year_out
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
signal
year_out
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
signal
month_out
:
std_logic_vector
(
4
downto
0
)
:
=
(
others
=>
'0'
);
signal
month_out
:
std_logic_vector
(
4
downto
0
)
:
=
(
others
=>
'0'
);
...
@@ -34,9 +34,18 @@ architecture basic_msf_signal of basic_msf_signal_tb is
...
@@ -34,9 +34,18 @@ architecture basic_msf_signal of basic_msf_signal_tb is
signal
bit_count
:
integer
:
=
58
;
signal
bit_count
:
integer
:
=
58
;
signal
inv_wave
:
std_logic
:
=
'0'
;
--invert output msf signal
--Type of parity error--
type
error_type
is
(
year_parity
,
month_day_parity
,
dow_parity
,
hour_minute_parity
,
no_parity
);
signal
current_error
:
error_type
:
=
no_parity
;
--select error
--File variables--
--File variables--
file
f_TIME_DATA
:
text
;
file
f_TIME_DATA
:
text
;
--Parity Check Function--
function
parity_check
(
vector
:
std_logic_vector
)
return
std_logic
is
function
parity_check
(
vector
:
std_logic_vector
)
return
std_logic
is
variable
count
:
integer
:
=
0
;
variable
count
:
integer
:
=
0
;
begin
begin
...
@@ -55,6 +64,8 @@ architecture basic_msf_signal of basic_msf_signal_tb is
...
@@ -55,6 +64,8 @@ architecture basic_msf_signal of basic_msf_signal_tb is
begin
begin
--Clock Generation--
--Clock Generation--
...
@@ -162,12 +173,26 @@ architecture basic_msf_signal of basic_msf_signal_tb is
...
@@ -162,12 +173,26 @@ architecture basic_msf_signal of basic_msf_signal_tb is
msf_a_string
(
7
downto
0
)
<=
"01111110"
;
msf_a_string
(
7
downto
0
)
<=
"01111110"
;
--Error insertion--
wait
until
rising_edge
(
fast_clk
);
if
current_error
=
year_parity
then
msf_a_string
(
37
)
<=
msf_a_string
(
37
)
xor
'1'
;
elsif
current_error
=
month_day_parity
then
msf_a_string
(
28
)
<=
msf_a_string
(
28
)
xor
'1'
;
elsif
current_error
=
dow_parity
then
msf_a_string
(
22
)
<=
msf_a_string
(
22
)
xor
'1'
;
elsif
current_error
=
hour_minute_parity
then
msf_a_string
(
13
)
<=
msf_a_string
(
13
)
xor
'1'
;
else
end
if
;
end
process
DATA_READ
;
end
process
DATA_READ
;
--Send data as MSF signal--
--Send data as MSF signal--
SEND_DATA
:
process
SEND_DATA
:
process
begin
begin
h_filter_in
<=
inv_wave
;
file_open
(
f_TIME_DATA
,
"H:\MSF_Project\time_data.csv"
,
read_mode
);
file_open
(
f_TIME_DATA
,
"H:\MSF_Project\time_data.csv"
,
read_mode
);
while
not
endfile
(
f_TIME_DATA
)
loop
while
not
endfile
(
f_TIME_DATA
)
loop
--Start of minute indicator--
--Start of minute indicator--
...
@@ -175,21 +200,21 @@ architecture basic_msf_signal of basic_msf_signal_tb is
...
@@ -175,21 +200,21 @@ architecture basic_msf_signal of basic_msf_signal_tb is
read_next
<=
'1'
;
read_next
<=
'1'
;
wait
until
rising_edge
(
clk
);
wait
until
rising_edge
(
clk
);
read_next
<=
'0'
;
read_next
<=
'0'
;
h_filter_in
<=
'0
'
;
h_filter_in
<=
inv_wave
xor
'1
'
;
wait
for
450
ms
;
wait
for
450
ms
;
wait
until
rising_edge
(
clk
);
wait
until
rising_edge
(
clk
);
h_filter_in
<=
'1'
;
h_filter_in
<=
inv_wave
;
wait
for
450
ms
;
wait
for
450
ms
;
for
i
in
0
to
58
loop
for
i
in
0
to
58
loop
bit_count
<=
bit_count
-
1
;
bit_count
<=
bit_count
-
1
;
wait
until
rising_edge
(
clk
);
wait
until
rising_edge
(
clk
);
h_filter_in
<=
'0
'
;
h_filter_in
<=
inv_wave
xor
'1
'
;
wait
until
rising_edge
(
clk
);
wait
until
rising_edge
(
clk
);
h_filter_in
<=
msf_a_string
(
bit_count
)
xor
'1'
;
h_filter_in
<=
msf_a_string
(
bit_count
)
xor
inv_wave
;
wait
until
rising_edge
(
clk
);
wait
until
rising_edge
(
clk
);
h_filter_in
<=
msf_b_string
(
bit_count
)
xor
'1'
;
--rely on don't care
h_filter_in
<=
msf_b_string
(
bit_count
)
xor
inv_wave
;
--rely on don't care
wait
until
rising_edge
(
clk
);
wait
until
rising_edge
(
clk
);
h_filter_in
<=
'1'
;
h_filter_in
<=
inv_wave
;
wait
for
750
ms
;
wait
for
750
ms
;
end
loop
;
end
loop
;
end
loop
;
end
loop
;
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment