Skip to content
Snippets Groups Projects
Commit b48432e7 authored by Jack Driscoll's avatar Jack Driscoll
Browse files

Update basic_msf_signal_tb.vhd

parent 6141c439
No related branches found
No related tags found
No related merge requests found
...@@ -16,8 +16,8 @@ architecture basic_msf_signal of basic_msf_signal_tb is ...@@ -16,8 +16,8 @@ architecture basic_msf_signal of basic_msf_signal_tb is
--Signal Declaration-- --Signal Declaration--
signal clk : std_logic := '0'; signal clk : std_logic := '0'; --10Hz clock for MSF pulse
signal fast_clk : std_logic := '0'; signal fast_clk : std_logic := '0'; --32768Hz clock for crystal
signal rst : std_logic := '0'; signal rst : std_logic := '0';
signal h_filter_in : std_logic := '1'; signal h_filter_in : std_logic := '1';
...@@ -37,6 +37,23 @@ architecture basic_msf_signal of basic_msf_signal_tb is ...@@ -37,6 +37,23 @@ architecture basic_msf_signal of basic_msf_signal_tb is
file f_TIME_DATA : text; file f_TIME_DATA : text;
function parity_check(vector : std_logic_vector) return std_logic is
variable count : integer := 0;
begin
for i in vector'range loop
if vector(i) = '1' then
count := count + 1;
end if;
end loop;
if (count mod 2) = 1 then
return '0';
else
return '1';
end if;
end function;
begin begin
...@@ -53,9 +70,9 @@ architecture basic_msf_signal of basic_msf_signal_tb is ...@@ -53,9 +70,9 @@ architecture basic_msf_signal of basic_msf_signal_tb is
FAST_CLOCK_CYCLE: process FAST_CLOCK_CYCLE: process
begin begin
fast_clk <= '0'; fast_clk <= '0';
wait for 200 us; wait for 30.517578 us;
fast_clk <= '1'; fast_clk <= '1';
wait for 200 us; wait for 30.517578 us;
end process FAST_CLOCK_CYCLE; end process FAST_CLOCK_CYCLE;
--Read time data from file-- --Read time data from file--
...@@ -84,6 +101,8 @@ architecture basic_msf_signal of basic_msf_signal_tb is ...@@ -84,6 +101,8 @@ architecture basic_msf_signal of basic_msf_signal_tb is
year_out(7 downto 4) <= std_logic_vector(to_unsigned((f_year-2000 - ((f_year-2000) mod 10))/10, 4)); year_out(7 downto 4) <= std_logic_vector(to_unsigned((f_year-2000 - ((f_year-2000) mod 10))/10, 4));
wait until rising_edge(fast_clk); wait until rising_edge(fast_clk);
msf_a_string(42 downto 35) <= year_out; msf_a_string(42 downto 35) <= year_out;
wait until rising_edge(fast_clk);
msf_b_string(5 downto 5) <= parity_check(year_out);
readline(f_TIME_DATA, file_line); readline(f_TIME_DATA, file_line);
read(file_line, f_month); read(file_line, f_month);
...@@ -98,26 +117,30 @@ architecture basic_msf_signal of basic_msf_signal_tb is ...@@ -98,26 +117,30 @@ architecture basic_msf_signal of basic_msf_signal_tb is
d_month_out(5 downto 4) <= std_logic_vector(to_unsigned((f_dmonth - f_dmonth mod 10)/10, 2)); d_month_out(5 downto 4) <= std_logic_vector(to_unsigned((f_dmonth - f_dmonth mod 10)/10, 2));
wait until rising_edge(fast_clk); wait until rising_edge(fast_clk);
msf_a_string(29 downto 24) <= d_month_out; msf_a_string(29 downto 24) <= d_month_out;
wait until rising_edge(fast_clk);
msf_b_string(4 downto 4) <= parity_check(month_out & d_month_out);
readline(f_TIME_DATA, file_line); readline(f_TIME_DATA, file_line);
read(file_line, f_dweek); read(file_line, f_dweek);
if f_dweek(1 to 6) = "Monday" then if f_dweek(1 to 6) = "Monday" then
d_week_out <= "001"; d_week_out <= "001";
elsif f_dweek(1 to 7) = "Tuesday" then elsif f_dweek(1 to 6) = "Tuesda" then
d_week_out <= "010"; d_week_out <= "010";
elsif f_dweek(1 to 9) = "Wednesday" then elsif f_dweek(1 to 6) = "Wednes" then
d_week_out <= "011"; d_week_out <= "011";
elsif f_dweek(1 to 8) = "Thursday" then elsif f_dweek(1 to 6) = "Thursd" then
d_week_out <= "100"; d_week_out <= "100";
elsif f_dweek(1 to 6) = "Friday" then elsif f_dweek(1 to 6) = "Friday" then
d_week_out <= "101"; d_week_out <= "101";
elsif f_dweek(1 to 8) = "Saturday" then elsif f_dweek(1 to 6) = "Saturd" then
d_week_out <= "110"; d_week_out <= "110";
else else
d_week_out <= "111"; d_week_out <= "111";
end if; end if;
wait until rising_edge(fast_clk); wait until rising_edge(fast_clk);
msf_a_string(23 downto 21) <= d_week_out; msf_a_string(23 downto 21) <= d_week_out;
wait until rising_edge(fast_clk);
msf_b_string(3 downto 3) <= parity_check(d_week_out);
readline(f_TIME_DATA, file_line); readline(f_TIME_DATA, file_line);
read(file_line, f_hour); read(file_line, f_hour);
...@@ -133,9 +156,10 @@ architecture basic_msf_signal of basic_msf_signal_tb is ...@@ -133,9 +156,10 @@ architecture basic_msf_signal of basic_msf_signal_tb is
wait until rising_edge(fast_clk); wait until rising_edge(fast_clk);
msf_a_string(14 downto 8) <= minute_out; msf_a_string(14 downto 8) <= minute_out;
wait until rising_edge(fast_clk); wait until rising_edge(fast_clk);
msf_b_string(2 downto 2) <= parity_check(f_hour & f_minute);
msf_a_string(7 downto 0) <= "01111110"; msf_a_string(7 downto 0) <= "01111110";
msf_b_string(6 downto 1) <= "011111"; --insert parity algorithm msf_b_string(1 downto 1) <= '1'; --assume BST
wait; wait;
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment