Update basic_msf_signal_tb.vhd

MSF/MSF_decoder/tb/basic_msf_signal_tb.vhd

@@ -16,9 +16,10 @@ architecture basic_msf_signal of basic_msf_signal_tb is
 
 	
 	--Signal Declaration--
-	signal clk			: std_logic := '0'; --10Hz clock for MSF pulse
-	signal fast_clk		: std_logic := '0'; --32768Hz clock for crystal
+	signal clk			: std_logic := '0';
+	signal fast_clk		: std_logic := '0';
 	signal rst			: std_logic := '0';
+	signal read_next	: std_logic := '0';
 	signal h_filter_in	: std_logic := '1';
 
 	signal year_out		: std_logic_vector (7 downto 0) := (others => '0');
@@ -31,12 +32,11 @@ architecture basic_msf_signal of basic_msf_signal_tb is
 	signal msf_a_string	: std_logic_vector (58 downto 0) := (others => '0');
 	signal msf_b_string	: std_logic_vector (58 downto 0) := (others => '0');
 	
-	signal bit_count	: integer := 0;
+	signal bit_count	: integer := 58;
 	
 	--File variables--
 	file f_TIME_DATA	: text;
 	
-
 	function parity_check(vector : std_logic_vector) return std_logic is
 	    variable count : integer := 0;
 		begin
@@ -70,9 +70,9 @@ architecture basic_msf_signal of basic_msf_signal_tb is
 		FAST_CLOCK_CYCLE: process
 			begin
 				fast_clk <= '0';
-				wait for 30.517578 us;
+				wait for 200 us;
 				fast_clk <= '1';
-				wait for 30.517578 us;
+				wait for 200 us;
 		end process FAST_CLOCK_CYCLE;
 		
 		--Read time data from file--
@@ -84,14 +84,14 @@ architecture basic_msf_signal of basic_msf_signal_tb is
 			variable f_year		: integer;
 			variable f_month	: integer;
 			variable f_dmonth	: integer;
-			variable f_dweek	: string (1 to 9);
+			variable f_dweek	: string (1 to 6);
 			variable f_hour		: integer;
 			variable f_minute	: integer;
 			variable remm		: integer;
 			
 			begin
-				file_open(f_TIME_DATA, "H:\MSF_Project\time_data.csv", read_mode);
 				
+				wait until rising_edge(read_next);
 				msf_a_string(58 downto 43) <= (others => '0'); 
 				msf_b_string(58 downto 43) <= "0000000011111110"; --default DUT1
 				
@@ -102,7 +102,7 @@ architecture basic_msf_signal of basic_msf_signal_tb is
 				wait until rising_edge(fast_clk);
 				msf_a_string(42 downto 35) <= year_out;
 				wait until rising_edge(fast_clk);
-				msf_b_string(5 downto 5) <= parity_check(year_out);
+				msf_b_string(5) <= parity_check(year_out);
 				
 				readline(f_TIME_DATA, file_line);
 				read(file_line, f_month);
@@ -118,7 +118,7 @@ architecture basic_msf_signal of basic_msf_signal_tb is
 				wait until rising_edge(fast_clk);
 				msf_a_string(29 downto 24) <= d_month_out;
 				wait until rising_edge(fast_clk);
-				msf_b_string(4 downto 4) <= parity_check(month_out & d_month_out);
+				msf_b_string(4) <= parity_check(msf_a_string(34 downto 24));
 				
 				readline(f_TIME_DATA, file_line);
 				read(file_line, f_dweek);
@@ -140,7 +140,7 @@ architecture basic_msf_signal of basic_msf_signal_tb is
 				wait until rising_edge(fast_clk);
 				msf_a_string(23 downto 21) <= d_week_out;
 				wait until rising_edge(fast_clk);
-				msf_b_string(3 downto 3) <= parity_check(d_week_out);
+				msf_b_string(3) <= parity_check(d_week_out);
 				
 				readline(f_TIME_DATA, file_line);
 				read(file_line, f_hour);
@@ -155,29 +155,32 @@ architecture basic_msf_signal of basic_msf_signal_tb is
 				minute_out(6 downto 4) <= std_logic_vector(to_unsigned((f_minute - f_minute mod 10)/10, 3));
 				wait until rising_edge(fast_clk);
 				msf_a_string(14 downto 8) <= minute_out;
+				readline(f_TIME_DATA, file_line); --whitespace
 				wait until rising_edge(fast_clk);
-				msf_b_string(2 downto 2) <= parity_check(f_hour & f_minute);
+				msf_b_string(2) <= parity_check(msf_a_string(20 downto 8));
+				msf_b_string(1) <= '1'; --BST
 				
 				msf_a_string(7 downto 0) <= "01111110";
-				msf_b_string(1 downto 1) <= '1'; --assume BST
 				
-				wait;
 				
 		end process DATA_READ;
 		
 		--Send data as MSF signal--
 		SEND_DATA: process
 			begin
+				file_open(f_TIME_DATA, "H:\MSF_Project\time_data.csv", read_mode);
+				while not endfile(f_TIME_DATA) loop
 					--Start of minute indicator--
+					bit_count <= 59;
+					read_next <= '1';
 					wait until rising_edge(clk);
-				wait until rising_edge(clk);
+					read_next <= '0';
 					h_filter_in <= '0';
 					wait for 450 ms;
 					wait until rising_edge(clk);
 					h_filter_in <= '1';
 					wait for 450 ms;
-				bit_count <= 59;
-				for i in 58 downto 0 loop
+					for i in 0 to 58 loop
 						bit_count <= bit_count - 1;
 						wait until rising_edge(clk);
 						h_filter_in <= '0';
@@ -189,7 +192,7 @@ architecture basic_msf_signal of basic_msf_signal_tb is
 						h_filter_in <= '1';
 						wait for 750 ms;
 					end loop;
-				
+				end loop;
 		end process SEND_DATA;