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Jack Driscoll
VHDL
Commits
46d3ae7c
Commit
46d3ae7c
authored
7 months ago
by
Jack Driscoll
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prints a sampled output into csv file
parent
022a9da4
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MSF/MSF_decoder/tb/basic_msf_signal_tb.vhd
+22
-7
22 additions, 7 deletions
MSF/MSF_decoder/tb/basic_msf_signal_tb.vhd
with
22 additions
and
7 deletions
MSF/MSF_decoder/tb/basic_msf_signal_tb.vhd
+
22
−
7
View file @
46d3ae7c
library
ieee
;
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
ieee
.
numeric_std
.
all
;
--use ieee.numeric_std_unsigned;
use
std
.
textio
.
all
;
use
std
.
textio
.
all
;
--library STD;
--use STD.textio.all;
entity
basic_msf_signal_tb
is
entity
basic_msf_signal_tb
is
end
entity
basic_msf_signal_tb
;
end
entity
basic_msf_signal_tb
;
...
@@ -81,9 +77,9 @@ architecture basic_msf_signal of basic_msf_signal_tb is
...
@@ -81,9 +77,9 @@ architecture basic_msf_signal of basic_msf_signal_tb is
FAST_CLOCK_CYCLE
:
process
FAST_CLOCK_CYCLE
:
process
begin
begin
fast_clk
<=
'0'
;
fast_clk
<=
'0'
;
wait
for
2
00
us
;
wait
for
10
00
us
;
fast_clk
<=
'1'
;
fast_clk
<=
'1'
;
wait
for
2
00
us
;
wait
for
10
00
us
;
end
process
FAST_CLOCK_CYCLE
;
end
process
FAST_CLOCK_CYCLE
;
--Read time data from file--
--Read time data from file--
...
@@ -220,6 +216,25 @@ architecture basic_msf_signal of basic_msf_signal_tb is
...
@@ -220,6 +216,25 @@ architecture basic_msf_signal of basic_msf_signal_tb is
end
loop
;
end
loop
;
end
process
SEND_DATA
;
end
process
SEND_DATA
;
--Sample output to text file--
SAMPLE_OUTPUT
:
process
variable
filen_line
:
line
;
variable
int_conv
:
integer
;
file
f_SAMPLE_DATA
:
text
open
write_mode
is
"H:\MSF_Project\msf_sample.csv"
;
begin
for
i
in
0
to
2000
loop
if
h_filter_in
=
'1'
then
int_conv
:
=
1
;
else
int_conv
:
=
0
;
end
if
;
wait
until
rising_edge
(
fast_clk
);
write
(
filen_line
,
int_conv
);
writeline
(
f_SAMPLE_DATA
,
filen_line
);
end
loop
;
end
process
SAMPLE_OUTPUT
;
--end;
--end;
...
...
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