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Jack Driscoll
VHDL
Commits
42b98ecd
Commit
42b98ecd
authored
8 months ago
by
Jack Driscoll
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MSF/MSF_decoder/tb/basic_msf_signal_tb.vhd
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42b98ecd
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
--use ieee.numeric_std_unsigned;
use
std
.
textio
.
all
;
--library STD;
--use STD.textio.all;
entity
basic_msf_signal_tb
is
end
entity
basic_msf_signal_tb
;
architecture
basic_msf_signal
of
basic_msf_signal_tb
is
--Signal Declaration--
signal
clk
:
std_logic
:
=
'0'
;
signal
fast_clk
:
std_logic
:
=
'0'
;
signal
rst
:
std_logic
:
=
'0'
;
signal
h_filter_in
:
std_logic
:
=
'1'
;
signal
year_out
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
signal
month_out
:
std_logic_vector
(
4
downto
0
)
:
=
(
others
=>
'0'
);
signal
d_month_out
:
std_logic_vector
(
5
downto
0
)
:
=
(
others
=>
'0'
);
signal
d_week_out
:
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
signal
hour_out
:
std_logic_vector
(
5
downto
0
)
:
=
(
others
=>
'0'
);
signal
minute_out
:
std_logic_vector
(
6
downto
0
)
:
=
(
others
=>
'0'
);
signal
msf_a_string
:
std_logic_vector
(
58
downto
0
)
:
=
(
others
=>
'0'
);
signal
msf_b_string
:
std_logic_vector
(
58
downto
0
)
:
=
(
others
=>
'0'
);
signal
bit_count
:
integer
:
=
0
;
--File variables--
file
f_TIME_DATA
:
text
;
begin
--Clock Generation--
CLOCK_CYCLE
:
process
begin
clk
<=
'0'
;
wait
for
50
ms
;
clk
<=
'1'
;
wait
for
50
ms
;
end
process
CLOCK_CYCLE
;
--Clock Generation--
FAST_CLOCK_CYCLE
:
process
begin
fast_clk
<=
'0'
;
wait
for
200
us
;
fast_clk
<=
'1'
;
wait
for
200
us
;
end
process
FAST_CLOCK_CYCLE
;
--Read time data from file--
DATA_READ
:
process
variable
file_line
:
line
;
--variable int_data : integer;
--variable str_data : string;
variable
f_year
:
integer
;
variable
f_month
:
integer
;
variable
f_dmonth
:
integer
;
variable
f_dweek
:
string
(
1
to
9
);
variable
f_hour
:
integer
;
variable
f_minute
:
integer
;
variable
remm
:
integer
;
begin
file_open
(
f_TIME_DATA
,
"H:\MSF_Project\time_data.csv"
,
read_mode
);
msf_a_string
(
58
downto
43
)
<=
(
others
=>
'0'
);
msf_b_string
(
58
downto
43
)
<=
"0000000011111110"
;
--default DUT1
readline
(
f_TIME_DATA
,
file_line
);
read
(
file_line
,
f_year
);
year_out
(
3
downto
0
)
<=
std_logic_vector
(
to_unsigned
((
f_year
-2000
)
mod
10
,
4
));
year_out
(
7
downto
4
)
<=
std_logic_vector
(
to_unsigned
((
f_year
-2000
-
((
f_year
-2000
)
mod
10
))
/
10
,
4
));
wait
until
rising_edge
(
fast_clk
);
msf_a_string
(
42
downto
35
)
<=
year_out
;
readline
(
f_TIME_DATA
,
file_line
);
read
(
file_line
,
f_month
);
month_out
(
3
downto
0
)
<=
std_logic_vector
(
to_unsigned
(
f_month
mod
10
,
4
));
month_out
(
4
downto
4
)
<=
std_logic_vector
(
to_unsigned
((
f_month
-
f_month
mod
10
)
/
10
,
1
));
wait
until
rising_edge
(
fast_clk
);
msf_a_string
(
34
downto
30
)
<=
month_out
;
readline
(
f_TIME_DATA
,
file_line
);
read
(
file_line
,
f_dmonth
);
d_month_out
(
3
downto
0
)
<=
std_logic_vector
(
to_unsigned
(
f_dmonth
mod
10
,
4
));
d_month_out
(
5
downto
4
)
<=
std_logic_vector
(
to_unsigned
((
f_dmonth
-
f_dmonth
mod
10
)
/
10
,
2
));
wait
until
rising_edge
(
fast_clk
);
msf_a_string
(
29
downto
24
)
<=
d_month_out
;
readline
(
f_TIME_DATA
,
file_line
);
read
(
file_line
,
f_dweek
);
if
f_dweek
(
1
to
6
)
=
"Monday"
then
d_week_out
<=
"001"
;
elsif
f_dweek
(
1
to
7
)
=
"Tuesday"
then
d_week_out
<=
"010"
;
elsif
f_dweek
(
1
to
9
)
=
"Wednesday"
then
d_week_out
<=
"011"
;
elsif
f_dweek
(
1
to
8
)
=
"Thursday"
then
d_week_out
<=
"100"
;
elsif
f_dweek
(
1
to
6
)
=
"Friday"
then
d_week_out
<=
"101"
;
elsif
f_dweek
(
1
to
8
)
=
"Saturday"
then
d_week_out
<=
"110"
;
else
d_week_out
<=
"111"
;
end
if
;
wait
until
rising_edge
(
fast_clk
);
msf_a_string
(
23
downto
21
)
<=
d_week_out
;
readline
(
f_TIME_DATA
,
file_line
);
read
(
file_line
,
f_hour
);
hour_out
(
3
downto
0
)
<=
std_logic_vector
(
to_unsigned
(
f_hour
mod
10
,
4
));
hour_out
(
5
downto
4
)
<=
std_logic_vector
(
to_unsigned
((
f_hour
-
f_hour
mod
10
)
/
10
,
2
));
wait
until
rising_edge
(
fast_clk
);
msf_a_string
(
20
downto
15
)
<=
hour_out
;
readline
(
f_TIME_DATA
,
file_line
);
read
(
file_line
,
f_minute
);
minute_out
(
3
downto
0
)
<=
std_logic_vector
(
to_unsigned
(
f_minute
mod
10
,
4
));
minute_out
(
6
downto
4
)
<=
std_logic_vector
(
to_unsigned
((
f_minute
-
f_minute
mod
10
)
/
10
,
3
));
wait
until
rising_edge
(
fast_clk
);
msf_a_string
(
14
downto
8
)
<=
minute_out
;
wait
until
rising_edge
(
fast_clk
);
msf_a_string
(
7
downto
0
)
<=
"01111110"
;
msf_b_string
(
6
downto
1
)
<=
"011111"
;
--insert parity algorithm
wait
;
end
process
DATA_READ
;
--Send data as MSF signal--
SEND_DATA
:
process
begin
--Start of minute indicator--
wait
until
rising_edge
(
clk
);
wait
until
rising_edge
(
clk
);
h_filter_in
<=
'0'
;
wait
for
450
ms
;
wait
until
rising_edge
(
clk
);
h_filter_in
<=
'1'
;
wait
for
450
ms
;
bit_count
<=
59
;
for
i
in
58
downto
0
loop
bit_count
<=
bit_count
-
1
;
wait
until
rising_edge
(
clk
);
h_filter_in
<=
'0'
;
wait
until
rising_edge
(
clk
);
h_filter_in
<=
msf_a_string
(
bit_count
)
xor
'1'
;
wait
until
rising_edge
(
clk
);
h_filter_in
<=
msf_b_string
(
bit_count
)
xor
'1'
;
--rely on don't care
wait
until
rising_edge
(
clk
);
h_filter_in
<=
'1'
;
wait
for
750
ms
;
end
loop
;
end
process
SEND_DATA
;
--end;
end
architecture
basic_msf_signal
;
\ No newline at end of file
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