Upload New File

MSF/RTC/hdl/rtc.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+entity rtc is
+	port(
+		clk_crystal	: in std_logic;
+		rst			: in std_logic;
+		time_ready	: in std_logic;
+
+		year_in		: in std_logic_vector (6 downto 0);
+		month_in	: in std_logic_vector (3 downto 0);
+		d_month_in	: in std_logic_vector (4 downto 0);
+		d_week_in	: in std_logic_vector (2 downto 0);
+		hour_in		: in std_logic_vector (4 downto 0);
+		minute_in	: in std_logic_vector (5 downto 0);
+
+		hour_out	: out std_logic_vector (4 downto 0);
+		minute_out	: out std_logic_vector (5 downto 0);
+		second_out	: out std_logic_vector (5 downto 0)
+		);
+end entity rtc;
+
+architecture behavioral of rtc is
+
+	signal clk_second	: std_logic := '1';
+
+	signal crys_count	: unsigned (13 downto 0) := (others => '0');
+	signal year_int		: unsigned (6 downto 0) := (others => '0');
+	signal month_int	: unsigned (3 downto 0) := (others => '0');
+	signal d_month_int	: unsigned (4 downto 0) := (others => '0');
+	signal d_week_int	: unsigned (2 downto 0) := (others => '0');
+	signal hour_int		: unsigned (4 downto 0) := (others => '0');
+	signal minute_int	: unsigned (5 downto 0) := (others => '0');
+	signal second_int	: unsigned (5 downto 0) := (others => '0');
+
+	begin
+
+		--Divide crystal oscillator down to 1Hz clock--
+		CLOCK_GEN: process
+		begin
+			if rst = '1' then --or start of pulse
+				crys_count <= 0;
+				clk_second <= '1';
+			elsif rising_edge(time_ready) then --synchronise to msf
+				crys_count <= 0;
+				clk_second <= '1';
+			elsif rising_edge(clk_crystal) then
+				crys_count <= crys_count + 1;
+				if crys_count = 16383 then
+					clk_second <= not(clk_second);
+				end if;
+			end if;
+		end process;
+
+		--Count seconds minutes and hours--
+		CLOCK_COUNT: process
+		begin
+			if rst = '1' then
+				second_int <= 0;
+				minute_int <= 0;
+				hour_int <= 0;
+
+			elsif rising_edge(time_ready) then --set time
+				second_int <= 59; --assume data comes at 59 seconds
+				minute_int <= to_unsigned(minute_in);
+				hour_int <= to_unsigned(hour_in);
+
+			elsif rising_edge(clk_second) then
+
+				if second_int = 59 then
+					second_int <= 0;
+
+					if minute_int = 59 then
+						minute_int <= 0;
+
+						if hour_int = 23 then
+							hour_int <= 0;
+						else
+							hour_int <= hour_int + 1;
+						end if;
+					else
+						minute_int <= minute_int + 1;
+					end if;
+				else
+					second_int <= second_int + 1;
+				end if;
+			end if;
+		end process
+
+		--Concurrent assignments--
+		second_out <= std_logic_vector(second_int);
+		minute_out <= std_logic_vector(minute_int);
+		hour_out <= std_logic_vector(hour_int);
+
+end behavioral;
\ No newline at end of file