Skip to content
Snippets Groups Projects
Commit 63e53e05 authored by Edward Longman's avatar Edward Longman
Browse files

Correct SPI config in main

parent d71fb23a
Branches
Tags
No related merge requests found
Hide whitespace changes
Inline Side-by-side
Showing
with 5 additions and 6 deletions
source/test/min2.c
+ 5
− 6
View file @ 63e53e05
...@@ -65,10 +65,9 @@ void main (void) ...@@ -65,10 +65,9 @@ void main (void)
P3DIR |= BIT4; P3DIR |= BIT4;
P3SEL0 &= ~BIT4; P3SEL0 &= ~BIT4;
P3SEL1 &= ~BIT4; P3SEL1 &= ~BIT4;
//Setup SPI
/* Keep peripheral in reset state*/ /* Keep peripheral in reset state*/
UCB1CTLW1 |= UCSWRST; UCB1CTLW0 |= UCSWRST;
UCB1CTL1 &= ~(UCSSEL_3);
//Reset all config //Reset all config
UCB1CTLW0 = ~(UCCKPH + UCCKPL + UC7BIT + UCMSB + UCB1CTLW0 = ~(UCCKPH + UCCKPL + UC7BIT + UCMSB +
UCMST + UCMODE_3 + UCSYNC); UCMST + UCMODE_3 + UCSYNC);
...@@ -86,9 +85,8 @@ void main (void) ...@@ -86,9 +85,8 @@ void main (void)
* supported by the supported radios: this could be optimized and done * supported by the supported radios: this could be optimized and done
* after chip detect. * after chip detect.
*/ */
UCB1CTLW0 |= 0x00+UCMST + UCSYNC + UCMODE_0 + UCMSB + UCCKPH; UCB1CTLW0 |= 0x00+UCMST + UCSYNC + UCMODE_0 + UCMSB + UCCKPH;
UCB1CTLW0 |= UCSSEL_2; UCB1CTLW0 |= UCSSEL_2;
UCB1BRW = 0x00;
UCB1BRW = 4; UCB1BRW = 4;
// select bit RF_MISO_PIN, RF_MOSI_PIN, RF_SCLK as peripheral // select bit RF_MISO_PIN, RF_MOSI_PIN, RF_SCLK as peripheral
...@@ -106,7 +104,8 @@ void main (void) ...@@ -106,7 +104,8 @@ void main (void)
RF_CS_N_PORT_OUT |= RF_CS_N_PIN; RF_CS_N_PORT_OUT |= RF_CS_N_PIN;
/* Release for operation */ /* Release for operation */
UCB1CTL1 &= ~UCSWRST; UCB1CTLW0 &= ~UCSWRST;
//trxRfSpiInterfaceInit(4);
__enable_interrupt(); __enable_interrupt();
/* Infinite loop with a 1 second timer */ /* Infinite loop with a 1 second timer */
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment