clean up clock and reset port pad connections and update GLIB dummy power pads

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v

@@ -97,9 +97,11 @@ module cmsdk_mcu_chip #(
   inout  wire          VDD,
   inout  wire          VSS,
 `endif
-  input  wire          XTAL1, // input
-  output wire          XTAL2, // output
-  input  wire          NRST,  // active low reset
+///  input  wire          XTAL1, // input
+  inout  wire          XTAL1, // input
+  inout  wire          XTAL2, // output
+///  input  wire          NRST,  // active low reset
+  inout  wire          NRST,  // active low reset
   inout  wire  [15:0]  P0,
   inout  wire  [15:0]  P1,
 
@@ -109,7 +111,8 @@ module cmsdk_mcu_chip #(
   output wire          TDO,
 `endif
   inout  wire          SWDIOTMS,
-  input  wire          SWCLKTCK);
+///  input  wire          SWCLKTCK);
+  inout  wire          SWCLKTCK);
 
 
 //------------------------------------
@@ -259,7 +262,7 @@ PAD_INOUT8MA_NOE uPAD_XTAL_I (
 PAD_INOUT8MA_NOE uPAD_XTAL_O (
    .PAD (XTAL2), 
    .O   (xtal_clk_out),
-   .I   (tielo), 
+   .I   ( ), 
    .NOE (tielo)
    );
 
@@ -828,7 +831,7 @@ PAD_INOUT8MA_NOE uPAD_P1_15 (
 
   cortexm0_rst_ctl u_rst_ctl
   (// Inputs
-   .GLOBALRESETn      (NRST),
+   .GLOBALRESETn      (nrst_in),
    .FCLK              (FCLK),
    .HCLK              (gated_hclk),
    .DCLK              (gated_dclk),
@@ -882,7 +885,7 @@ PAD_INOUT8MA_NOE uPAD_P1_15 (
 
   cm0p_ik_rst_ctl u_rst_ctl
   (// Inputs
-   .GLOBALRESETn      (NRST),
+   .GLOBALRESETn      (nrst_in),
    .FCLK              (FCLK),
    .HCLK              (gated_hclk),
    .DCLK              (gated_dclk),
@@ -1220,21 +1223,23 @@ assign ADPRESETREQ = adp_gpo8[0];
 // Flash memory
 //----------------------------------------
 cmsdk_ahb_rom
+//cmsdk_ahb_ram
   #(.MEM_TYPE(ROM_MEM_TYPE),
-//    .AW(16),  // 64K bytes flash ROM
-    .AW(13),  // 8K bytes flash ROM -Dhry
-//    .AW(10),  // 1K bytes flash ROM - Hello
-    .filename("image.hex"),
+    .AW(16),  // 64K bytes flash ROM
+//    .AW(13),  // 8K bytes flash ROM -Dhry
+///    .AW(10),  // 1K bytes flash ROM - Hello
+    .filename("../rtl_sim/image.hex"),
     .WS_N(`ARM_CMSDK_ROM_MEM_WS_N),
-    .WS_S(`ARM_CMSDK_ROM_MEM_WS_S),
-    .BE  (BE))
+    .WS_S(`ARM_CMSDK_ROM_MEM_WS_S)
+   ,.BE  (BE)
+   )
    u_ahb_rom (
     .HCLK             (HCLKSYS),
     .HRESETn          (HRESETn),
     .HSEL             (flash_hsel),  // AHB inputs
-//    .HADDR            (HADDR[15:0]),
-    .HADDR            (HADDR[12:0]),
-//    .HADDR            (HADDR[ 9:0]),
+    .HADDR            (HADDR[15:0]),
+//    .HADDR            (HADDR[12:0]),
+///    .HADDR            (HADDR[ 9:0]),
     .HTRANS           (HTRANS),
     .HSIZE            (HSIZE),
     .HWRITE           (HWRITE),
@@ -1303,18 +1308,18 @@ cmsdk_ahb_rom
 //----------------------------------------
 cmsdk_ahb_ram
   #(.MEM_TYPE(RAM_MEM_TYPE),
-///    .AW(16),  // 64K bytes SRAM
-    .AW(10),  // 1K bytes SRAM
-//    .AW( 9),  // 512 bytes SRAM
+    .AW(16),  // 64K bytes SRAM
+//    .AW(10),  // 1K bytes SRAM
+///    .AW( 9),  // 512 bytes SRAM
     .WS_N(`ARM_CMSDK_RAM_MEM_WS_N),
     .WS_S(`ARM_CMSDK_RAM_MEM_WS_S))
    u_ahb_ram (
     .HCLK             (HCLKSYS),
     .HRESETn          (HRESETn),
     .HSEL             (sram_hsel),  // AHB inputs
-///    .HADDR            (HADDR[15:0]),
-    .HADDR            (HADDR[ 9:0]),
-//    .HADDR            (HADDR[ 8:0]),
+    .HADDR            (HADDR[15:0]),
+//    .HADDR            (HADDR[ 9:0]),
+///    .HADDR            (HADDR[ 8:0]),
     .HTRANS           (HTRANS),
     .HSIZE            (HSIZE),
     .HWRITE           (HWRITE),

GLIB/pads/verilog/PAD_VDDIO.v

@@ -14,4 +14,5 @@ module PAD_VDDIO (
    PAD
    );
    inout PAD;
-endmodule // PAD_VDDIO
+   assign PAD = 1'b1;
+ endmodule // PAD_VDDIO

GLIB/pads/verilog/PAD_VDDSOC.v

@@ -15,4 +15,5 @@ module PAD_VDDSOC (
    PAD
    );
    inout PAD;
+   assign PAD = 1'b1;
 endmodule // PAD_VDDSOC

GLIB/pads/verilog/PAD_VSS.v

@@ -14,4 +14,5 @@ module PAD_VSS (
    PAD
    );
    inout PAD;
+   assign PAD = 1'b0;
 endmodule // PAD_VSS

GLIB/pads/verilog/PAD_VSSIO.v

@@ -14,5 +14,6 @@ module PAD_VSSIO (
    PAD
    );
    inout PAD;
+   assign PAD = 1'b0;
 endmodule // PAD_VSSIO