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Commit e35827b2 authored by dwf1m12's avatar dwf1m12
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clean up clock and reset port pad connections and update GLIB dummy power pads

parent c7aad314
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...@@ -97,9 +97,11 @@ module cmsdk_mcu_chip #( ...@@ -97,9 +97,11 @@ module cmsdk_mcu_chip #(
inout wire VDD, inout wire VDD,
inout wire VSS, inout wire VSS,
`endif `endif
input wire XTAL1, // input /// input wire XTAL1, // input
output wire XTAL2, // output inout wire XTAL1, // input
input wire NRST, // active low reset inout wire XTAL2, // output
/// input wire NRST, // active low reset
inout wire NRST, // active low reset
inout wire [15:0] P0, inout wire [15:0] P0,
inout wire [15:0] P1, inout wire [15:0] P1,
...@@ -109,7 +111,8 @@ module cmsdk_mcu_chip #( ...@@ -109,7 +111,8 @@ module cmsdk_mcu_chip #(
output wire TDO, output wire TDO,
`endif `endif
inout wire SWDIOTMS, inout wire SWDIOTMS,
input wire SWCLKTCK); /// input wire SWCLKTCK);
inout wire SWCLKTCK);
//------------------------------------ //------------------------------------
...@@ -259,7 +262,7 @@ PAD_INOUT8MA_NOE uPAD_XTAL_I ( ...@@ -259,7 +262,7 @@ PAD_INOUT8MA_NOE uPAD_XTAL_I (
PAD_INOUT8MA_NOE uPAD_XTAL_O ( PAD_INOUT8MA_NOE uPAD_XTAL_O (
.PAD (XTAL2), .PAD (XTAL2),
.O (xtal_clk_out), .O (xtal_clk_out),
.I (tielo), .I ( ),
.NOE (tielo) .NOE (tielo)
); );
...@@ -828,7 +831,7 @@ PAD_INOUT8MA_NOE uPAD_P1_15 ( ...@@ -828,7 +831,7 @@ PAD_INOUT8MA_NOE uPAD_P1_15 (
cortexm0_rst_ctl u_rst_ctl cortexm0_rst_ctl u_rst_ctl
(// Inputs (// Inputs
.GLOBALRESETn (NRST), .GLOBALRESETn (nrst_in),
.FCLK (FCLK), .FCLK (FCLK),
.HCLK (gated_hclk), .HCLK (gated_hclk),
.DCLK (gated_dclk), .DCLK (gated_dclk),
...@@ -882,7 +885,7 @@ PAD_INOUT8MA_NOE uPAD_P1_15 ( ...@@ -882,7 +885,7 @@ PAD_INOUT8MA_NOE uPAD_P1_15 (
cm0p_ik_rst_ctl u_rst_ctl cm0p_ik_rst_ctl u_rst_ctl
(// Inputs (// Inputs
.GLOBALRESETn (NRST), .GLOBALRESETn (nrst_in),
.FCLK (FCLK), .FCLK (FCLK),
.HCLK (gated_hclk), .HCLK (gated_hclk),
.DCLK (gated_dclk), .DCLK (gated_dclk),
...@@ -1220,21 +1223,23 @@ assign ADPRESETREQ = adp_gpo8[0]; ...@@ -1220,21 +1223,23 @@ assign ADPRESETREQ = adp_gpo8[0];
// Flash memory // Flash memory
//---------------------------------------- //----------------------------------------
cmsdk_ahb_rom cmsdk_ahb_rom
//cmsdk_ahb_ram
#(.MEM_TYPE(ROM_MEM_TYPE), #(.MEM_TYPE(ROM_MEM_TYPE),
// .AW(16), // 64K bytes flash ROM .AW(16), // 64K bytes flash ROM
.AW(13), // 8K bytes flash ROM -Dhry // .AW(13), // 8K bytes flash ROM -Dhry
// .AW(10), // 1K bytes flash ROM - Hello /// .AW(10), // 1K bytes flash ROM - Hello
.filename("image.hex"), .filename("../rtl_sim/image.hex"),
.WS_N(`ARM_CMSDK_ROM_MEM_WS_N), .WS_N(`ARM_CMSDK_ROM_MEM_WS_N),
.WS_S(`ARM_CMSDK_ROM_MEM_WS_S), .WS_S(`ARM_CMSDK_ROM_MEM_WS_S)
.BE (BE)) ,.BE (BE)
)
u_ahb_rom ( u_ahb_rom (
.HCLK (HCLKSYS), .HCLK (HCLKSYS),
.HRESETn (HRESETn), .HRESETn (HRESETn),
.HSEL (flash_hsel), // AHB inputs .HSEL (flash_hsel), // AHB inputs
// .HADDR (HADDR[15:0]), .HADDR (HADDR[15:0]),
.HADDR (HADDR[12:0]), // .HADDR (HADDR[12:0]),
// .HADDR (HADDR[ 9:0]), /// .HADDR (HADDR[ 9:0]),
.HTRANS (HTRANS), .HTRANS (HTRANS),
.HSIZE (HSIZE), .HSIZE (HSIZE),
.HWRITE (HWRITE), .HWRITE (HWRITE),
...@@ -1303,18 +1308,18 @@ cmsdk_ahb_rom ...@@ -1303,18 +1308,18 @@ cmsdk_ahb_rom
//---------------------------------------- //----------------------------------------
cmsdk_ahb_ram cmsdk_ahb_ram
#(.MEM_TYPE(RAM_MEM_TYPE), #(.MEM_TYPE(RAM_MEM_TYPE),
/// .AW(16), // 64K bytes SRAM .AW(16), // 64K bytes SRAM
.AW(10), // 1K bytes SRAM // .AW(10), // 1K bytes SRAM
// .AW( 9), // 512 bytes SRAM /// .AW( 9), // 512 bytes SRAM
.WS_N(`ARM_CMSDK_RAM_MEM_WS_N), .WS_N(`ARM_CMSDK_RAM_MEM_WS_N),
.WS_S(`ARM_CMSDK_RAM_MEM_WS_S)) .WS_S(`ARM_CMSDK_RAM_MEM_WS_S))
u_ahb_ram ( u_ahb_ram (
.HCLK (HCLKSYS), .HCLK (HCLKSYS),
.HRESETn (HRESETn), .HRESETn (HRESETn),
.HSEL (sram_hsel), // AHB inputs .HSEL (sram_hsel), // AHB inputs
/// .HADDR (HADDR[15:0]), .HADDR (HADDR[15:0]),
.HADDR (HADDR[ 9:0]), // .HADDR (HADDR[ 9:0]),
// .HADDR (HADDR[ 8:0]), /// .HADDR (HADDR[ 8:0]),
.HTRANS (HTRANS), .HTRANS (HTRANS),
.HSIZE (HSIZE), .HSIZE (HSIZE),
.HWRITE (HWRITE), .HWRITE (HWRITE),
......
...@@ -14,4 +14,5 @@ module PAD_VDDIO ( ...@@ -14,4 +14,5 @@ module PAD_VDDIO (
PAD PAD
); );
inout PAD; inout PAD;
assign PAD = 1'b1;
endmodule // PAD_VDDIO endmodule // PAD_VDDIO
...@@ -15,4 +15,5 @@ module PAD_VDDSOC ( ...@@ -15,4 +15,5 @@ module PAD_VDDSOC (
PAD PAD
); );
inout PAD; inout PAD;
assign PAD = 1'b1;
endmodule // PAD_VDDSOC endmodule // PAD_VDDSOC
...@@ -14,4 +14,5 @@ module PAD_VSS ( ...@@ -14,4 +14,5 @@ module PAD_VSS (
PAD PAD
); );
inout PAD; inout PAD;
assign PAD = 1'b0;
endmodule // PAD_VSS endmodule // PAD_VSS
...@@ -14,5 +14,6 @@ module PAD_VSSIO ( ...@@ -14,5 +14,6 @@ module PAD_VSSIO (
PAD PAD
); );
inout PAD; inout PAD;
assign PAD = 1'b0;
endmodule // PAD_VSSIO endmodule // PAD_VSSIO
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