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Commit 108772f7 authored by dwf1m12's avatar dwf1m12
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fpga_imp directory target board example scripts ready for experimental use

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Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga.scr 0 → 100755
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echo 'run' $0
echo 'target' $1
#set argv [list $1 $1]
#set argc 1
rm target_fpga
ln -sf target_fpga_$1 target_fpga
vivado -mode batch -source scripts/build_mcu_fpga_batch.tcl
rm -R vivado/built_mcu_fpga_$1
mv -f vivado/built_mcu_fpga vivado/built_mcu_fpga_$1
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_batch.tcl 0 → 100644
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# build_mcu_fpga_batch.tcl
#
# cmsdk_mcu sample design
# A Vivado script that demonstrates a very simple RTL-to-bitstream non-project batch flow
#
# NOTE: typical usage would be "vivado -mode tcl -source build_mcu_fpga_batch.tcl"
#
# STEP#0: define output directory area.
#
##if {$argc < 1} {
#puts "target_fpga arg must be \[ac701 \| arm_mps3 \| pynz_z2 \| zcu104\]"
#}
#set target [lindex $argv 0]
#puts "target requested : $target"
#set target_dir target_fpga
#append target_dir $target
#puts "target directory : $target_dir"
set outputDir ./vivado/built_mcu_fpga
file mkdir $outputDir
#
# STEP#1: setup design sources and constraints
#
# local search path for configurations
set search_path ../verilog
set cortexm0_vlog ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical
source scripts/rtl_source_cm0.tcl
set search_path [ concat $search_path $cortexm0_vlog/cortexm0_integration/verilog ]
read_verilog [ glob $cortexm0_vlog/cortexm0_integration/verilog/*.v ]
read_verilog [ glob $cortexm0_vlog/models/cells/*.v ]
# Arm unmodified CMSDK RTL
set cmsdk_vlog ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0
source scripts/rtl_source_cmsdk.tcl
set search_path [ concat $search_path $cmsdk_vlog/logical/models/memories ]
read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_memory_models_defs.v
read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_rom.v
read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_rom.v
read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_ram.v
read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_sram.v
# ADP, FT1248 and streamio IP
source scripts/rtl_source_soclabs_ip.tcl
# FPGA-specific pads
source scripts/rtl_source_fpga_ip.tcl
# soclabs modified mcu system
set soc_vlog ../verilog
read_verilog $soc_vlog/cmsdk_mcu_defs.v
read_verilog $soc_vlog/ahb_bootrom.v
read_verilog $soc_vlog/bootrom.v
read_verilog $soc_vlog/cmsdk_ahb_cs_rom_table.v
read_verilog $soc_vlog/cmsdk_apb_usrt.v
read_verilog $soc_vlog/cmsdk_mcu_addr_decode.v
read_verilog $soc_vlog/cmsdk_mcu_clkctrl.v
read_verilog $soc_vlog/cmsdk_mcu_pin_mux.v
read_verilog $soc_vlog/cmsdk_mcu_stclkctrl.v
read_verilog $soc_vlog/cmsdk_mcu_sysctrl.v
read_verilog $soc_vlog/cmsdk_mcu_system.v
read_verilog $soc_vlog/cmsdk_mcu_chip.v
# FPGA specific timing constraints
read_xdc target_fpga/fpga_timing.xdc
# FPGA board specific pin constraints
read_xdc target_fpga/fpga_pinmap.xdc
#
# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design
#
source target_fpga/fpga_synth.tcl
write_checkpoint -force $outputDir/post_synth
report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
report_power -file $outputDir/post_synth_power.rpt
#
# STEP#3: run placement and logic optimzation, report utilization and timing estimates, write checkpoint design
#
opt_design
place_design
phys_opt_design
write_checkpoint -force $outputDir/post_place
report_timing_summary -file $outputDir/post_place_timing_summary.rpt
#
# STEP#4: run router, report actual utilization and timing, write checkpoint design, run drc, write verilog and xdc out
#
route_design
write_checkpoint -force $outputDir/post_route
report_timing_summary -file $outputDir/post_route_timing_summary.rpt
report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt
report_clock_utilization -file $outputDir/clock_util.rpt
report_utilization -file $outputDir/post_route_util.rpt
report_power -file $outputDir/post_route_power.rpt
report_drc -file $outputDir/post_imp_drc.rpt
write_verilog -force $outputDir/cmsdk_mcu_impl_netlist.v
write_xdc -no_fixed_only -force $outputDir/cmsdk_mcu_impl.xdc
#
# STEP#5: generate a bitstream
#
write_bitstream -force $outputDir/cmsdk_mcu.bit
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_cm0.tcl 0 → 100644
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### Cortex-M0 rtl source build
set search_path [ concat $search_path $cortexm0_vlog/cortexm0/verilog ]
read_verilog [ glob $cortexm0_vlog/cortexm0/verilog/*.v ]
set search_path [ concat $search_path $cortexm0_vlog/cortexm0_dap/verilog ]
##read_verilog [ glob $cortexm0_vlog/cortexm0_dap/verilog/*.v ]
read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap_cdc.v
read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap_mast.v
read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_cdc.v
read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_jtag.v
###read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_sw_defs.v
read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp.v
###read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap_mast_defs.v
read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap.v
###read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_jtag_defs.v
read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_pwr.v
read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_sw.v
read_verilog $cortexm0_vlog/cortexm0_dap/verilog/CORTEXM0DAP.v
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_cmsdk.tcl 0 → 100644
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### CMSDK rtl source build
###read_verilog [ glob $cmsdk_vlog/logical/cmsdk_ahb_gpio/verilog/*.v ]
read_verilog $cmsdk_vlog/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v
read_verilog $cmsdk_vlog/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v
read_verilog $cmsdk_vlog/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v
read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_timer/verilog/*.v ]
read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_dualtimers/verilog/*.v ]
read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_watchdog/verilog/*.v ]
read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_uart/verilog/*.v ]
read_verilog $cmsdk_vlog/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
read_verilog [ glob $cmsdk_vlog/logical/cmsdk_ahb_slave_mux/verilog/*.v ]
read_verilog [ glob $cmsdk_vlog/logical/cmsdk_ahb_to_apb/verilog/*.v ]
read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_slave_mux/verilog/*.v ]
read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_subsystem/verilog/*.v ]
read_verilog [ glob $cmsdk_vlog/logical/cmsdk_ahb_bitband/verilog/*.v ]
read_verilog [ glob $cmsdk_vlog/logical/cmsdk_ahb_master_mux/verilog/*.v ]
read_verilog $cmsdk_vlog/logical/models/clkgate/cmsdk_clock_gate.v
read_verilog $cmsdk_vlog/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_fpga_ip.tcl 0 → 100644
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# rtl_source_fpga_ip.tcl
#
set fpgalib_vlog ../../../../../FPGALIB
read_verilog $fpgalib_vlog/pads/verilog/PAD_INOUT8MA_NOE.v
read_verilog $fpgalib_vlog/pads/verilog/PAD_VDDIO.v
read_verilog $fpgalib_vlog/pads/verilog/PAD_VSSIO.v
read_verilog $fpgalib_vlog/pads/verilog/PAD_VDDSOC.v
read_verilog $fpgalib_vlog/pads/verilog/PAD_VSS.v
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_soclabs_ip.tcl 0 → 100644
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# rtl_source_soclabs_ip.tcl
#
set iplib_vlog ../../../../../IPLIB
read_verilog $iplib_vlog/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
read_verilog $iplib_vlog/ADPcontrol_v1_0/ADPcontrol_v1_0.v
read_verilog $iplib_vlog/ADPcontrol_v1_0/ADPmanager.v
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_ac701/fpga_synth.tcl 0 → 100644
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synth_design -top cmsdk_mcu_chip -part xc7a200tfbg676-2
write_verilog -force $outputDir/cmsdk_mcu_synth_netlist.v
# # Create interface ports
#
# disconnect_net -net XTAL1 -objects {uPAD_XTAL_I/XTAL1}
# disconnect_net -net XTAL2 -objects {uPAD_XTAL_O/XTAL2}
# #disconnect_net -net xtal_clk_in] [get_pins XTAL1 uPAD_XTAL1_PAD/IOBUF3V3/I]]
# set sys_diff_clock [ create_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_diff_clock ]
# set_property -dict [ list \
# CONFIG.FREQ_HZ {200000000} \
# ] $sys_diff_clock
# set reset [ create_bd_port -dir I -type rst reset ]
# set_property -dict [ list \
# CONFIG.POLARITY {ACTIVE_HIGH} \
# ] $reset
# # Create instance: clk_wiz_20M, and set properties
# set clk_wiz_20M [ create_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_20M ]
# set_property -dict [ list \
# CONFIG.CLKOUT1_JITTER {155.788} \
# CONFIG.CLKOUT1_PHASE_ERROR {94.329} \
# CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {20.000} \
# CONFIG.CLK_IN1_BOARD_INTERFACE {sys_diff_clock} \
# CONFIG.MMCM_CLKFBOUT_MULT_F {4.250} \
# CONFIG.MMCM_CLKOUT0_DIVIDE_F {42.500} \
# CONFIG.RESET_BOARD_INTERFACE {reset} \
# CONFIG.USE_BOARD_FLOW {false} \
#] $clk_wiz_20M
# # Create interface connections
# connect_net -intf_net sys_diff_clock_1 [get_ports sys_diff_clock] [get_pins clk_wiz_20M/CLK_IN1_D]
# # Create port connections
# connect_net -net clk_wiz_0_clk_out1 [get_pins xtal_clk_in] [get_bd_pins clk_wiz_20M/clk_out1]
# connect_net -net reset_1 [get_bd_ports reset] [get_bd_pins clk_wiz_20M/reset]
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_ac701/fpga_timing.xdc 0 → 100644
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##################################################################################
## ##
## ZYNQ timing XDC ##
## ##
##################################################################################
create_clock -name CLK -period 30 [get_ports XTAL1]
create_clock -name VCLK -period 30 -waveform {5 20}
create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
create_clock -name VSWCLK -period 60 -waveform {5 35}
set_clock_groups -name async_clk_swclock -asynchronous \
-group [get_clocks -include_generated_clocks CLK] \
-group [get_clocks -include_generated_clocks VSWCLK]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[0]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[1]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[2]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[3]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[4]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[5]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[6]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[7]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[8]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[9]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[10]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[11]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[11]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[12]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[13]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[13]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[14]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[15]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[15]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[0]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[1]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[2]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[3]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[4]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[5]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[6]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[7]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[8]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[9]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[10]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[11]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[11]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[12]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[13]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[13]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[14]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[15]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[15]}]
set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_arm_mps3/fpga_synth.tcl 0 → 100644
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synth_design -top cmsdk_mcu_chip -part xcku115-flvb1760-1-c
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_arm_mps3/fpga_timing.xdc 0 → 100644
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##################################################################################
## ##
## Arm MPS3 Rev-C timing XDC ##
## ##
##################################################################################
create_clock -name CLK -period 30 [get_ports XTAL1]
create_clock -name VCLK -period 30 -waveform {5 20}
create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
create_clock -name VSWCLK -period 60 -waveform {5 35}
set_clock_groups -name async_clk_swclock -asynchronous \
-group [get_clocks -include_generated_clocks CLK] \
-group [get_clocks -include_generated_clocks SWCLK]
set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_SW[*]}]
set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_SW[*]}]
set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_nPB[*]}]
set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nPB[*]}]
set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports CB_nPOR]
set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports CB_nPOR]
set_output_delay -clock [get_clocks oscclk_0] -min -add_delay -1.200 [get_ports {USER_nLED[*]}]
set_output_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nLED[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[0]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[1]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[2]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[3]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[4]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[5]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[6]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[7]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[8]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[9]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[10]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P011]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[11]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[12]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P013]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[13]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[14]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P015]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[15]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[0]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[1]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[2]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[3]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[4]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[5]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[6]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[7]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[8]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[9]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[10]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P111]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[11]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[12]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P113]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[13]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[14]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P115]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[15]} ]
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc 0 → 100644
+ 228
− 0
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##################################################################################
## ##
## TUL pynq_z2 XDC ##
## ##
##################################################################################
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_0]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_1]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_2]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_3]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_4]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_5]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_6]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_7]
#set_property PACKAGE_PIN Y18 [get_ports PMOD0_0]
#set_property PACKAGE_PIN Y19 [get_ports PMOD0_1]
#set_property PACKAGE_PIN Y16 [get_ports PMOD0_2]
#set_property PACKAGE_PIN Y17 [get_ports PMOD0_3]
#set_property PACKAGE_PIN U18 [get_ports PMOD0_4]
#set_property PACKAGE_PIN U19 [get_ports PMOD0_5]
#set_property PACKAGE_PIN W18 [get_ports PMOD0_6]
#set_property PACKAGE_PIN W19 [get_ports PMOD0_7]
#set_property PULLUP true [get_ports PMOD0_2]
#set_property PULLUP true [get_ports PMOD0_3]
#set_property PULLUP true [get_ports PMOD0_4]
#set_property PULLUP true [get_ports PMOD0_5]
#set_property PULLUP true [get_ports PMOD0_6]
#set_property PULLUP true [get_ports PMOD0_7]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_0]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_1]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_2]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_3]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_4]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_5]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_6]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_7]
#PMODA pin0 : FTCLK
#set_property PACKAGE_PIN J9 [get_ports PMOD1_0]
#PMODA pin1 : FTSSN
#set_property PACKAGE_PIN K9 [get_ports PMOD1_1]
#PMODA pin2 : FTMISO
#set_property PACKAGE_PIN K8 [get_ports PMOD1_2]
#PMODA pin3 : FTMIOSIO
#set_property PACKAGE_PIN L8 [get_ports PMOD1_3]
#PMODA pin4 : UART2RXD
#set_property PACKAGE_PIN L10 [get_ports PMOD1_4]
#PMODA pin4 : UART2TXD
#set_property PACKAGE_PIN M10 [get_ports PMOD1_5]
#set_property PACKAGE_PIN M8 [get_ports PMOD1_6]
#set_property PACKAGE_PIN M9 [get_ports PMOD1_7]
#set_property PULLUP true [get_ports PMOD1_7]
#set_property PULLUP true [get_ports PMOD1_6]
#set_property PULLUP true [get_ports PMOD1_5]
#set_property PULLUP true [get_ports PMOD1_4]
#set_property PULLUP true [get_ports PMOD1_3]
#set_property PULLUP true [get_ports PMOD1_2]
#set_property PULLUP true [get_ports PMOD1_1]
#set_property PULLUP true [get_ports PMOD1_0]
set_property IOSTANDARD LVCMOS33 [get_ports XTAL1]
set_property IOSTANDARD LVCMOS33 [get_ports XTAL2]
set_property IOSTANDARD LVCMOS33 [get_ports NRST]
set_property IOSTANDARD LVCMOS33 [get_ports SWCLKTCK]
set_property IOSTANDARD LVCMOS33 [get_ports SWDIOTMS]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[0]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[1]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[2]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[3]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[4]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[5]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[6]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[7]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[8]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[9]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[10]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[11]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[12]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[13]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[14]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P0[15]} ]
set_property PULLUP true [get_ports {P0[0]} ]
set_property PULLUP true [get_ports {P0[1]} ]
set_property PULLUP true [get_ports {P0[2]} ]
set_property PULLUP true [get_ports {P0[3]} ]
set_property PULLUP true [get_ports {P0[4]} ]
set_property PULLUP true [get_ports {P0[5]} ]
set_property PULLUP true [get_ports {P0[6]} ]
set_property PULLUP true [get_ports {P0[7]} ]
set_property PULLUP true [get_ports {P0[8]} ]
set_property PULLUP true [get_ports {P0[9]} ]
set_property PULLUP true [get_ports {P0[10]} ]
set_property PULLUP true [get_ports {P0[11]} ]
set_property PULLUP true [get_ports {P0[12]} ]
set_property PULLUP true [get_ports {P0[13]} ]
set_property PULLUP true [get_ports {P0[14]} ]
set_property PULLUP true [get_ports {P0[15]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[0]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[1]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[2]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[3]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[4]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[5]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[6]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[7]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[8]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[9]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[10]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[11]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[12]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[13]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[14]} ]
set_property IOSTANDARD LVCMOS33 [get_ports {P1[15]} ]
set_property PULLUP true [get_ports {P1[0]} ]
set_property PULLUP true [get_ports {P1[1]} ]
set_property PULLUP true [get_ports {P1[2]} ]
set_property PULLUP true [get_ports {P1[3]} ]
set_property PULLUP true [get_ports {P1[4]} ]
set_property PULLUP true [get_ports {P1[5]} ]
set_property PULLUP true [get_ports {P1[6]} ]
set_property PULLUP true [get_ports {P1[7]} ]
set_property PULLUP true [get_ports {P1[8]} ]
set_property PULLUP true [get_ports {P1[9]} ]
set_property PULLUP true [get_ports {P1[10]} ]
set_property PULLUP true [get_ports {P1[11]} ]
set_property PULLUP true [get_ports {P1[12]} ]
set_property PULLUP true [get_ports {P1[13]} ]
set_property PULLUP true [get_ports {P1[14]} ]
set_property PULLUP true [get_ports {P1[15]} ]
### PMODA ###
#set_property PACKAGE_PIN Y18 [get_ports PMOD0_0]
#set_property PACKAGE_PIN Y19 [get_ports PMOD0_1]
#set_property PACKAGE_PIN Y16 [get_ports PMOD0_2]
#set_property PACKAGE_PIN Y17 [get_ports PMOD0_3]
#set_property PACKAGE_PIN U18 [get_ports PMOD0_4]
#set_property PACKAGE_PIN U19 [get_ports PMOD0_5]
#set_property PACKAGE_PIN W18 [get_ports PMOD0_6]
#set_property PACKAGE_PIN W19 [get_ports PMOD0_7]
## low row, PMOD-FT1248
#PMODAL pin1 to FTMISO
set_property PACKAGE_PIN Y18 [get_ports {P1[0]}]
#PMODAL pin2 to FTCLK
set_property PACKAGE_PIN Y19 [get_ports {P1[1]}]
#PMODAL pin3 to FTMIOSIO
set_property PACKAGE_PIN Y16 [get_ports {P1[2]}]
#PMODAL pin4 to FTSSN
set_property PACKAGE_PIN Y17 [get_ports {P1[3]}]
## upper row, AUP-SWD
#PMODAU pin1 to SWDIO
set_property PACKAGE_PIN U18 [get_ports SWDIOTMS]
#PMODAU pin2 to CLK15MHz
##set_property PACKAGE_PIN U19 [get_ports XTAL1]
#PMODAU pin3 to CLK30MHz
set_property PACKAGE_PIN W18 [get_ports XTAL1]
#PMODAU pin1 to SWDIO
set_property PACKAGE_PIN W19 [get_ports SWCLKTCK]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_XTAL_I/IOBUF3V3/O]
set_property PULLDOWN [get_ports SWDIOTMS]
set_property PULLDOWN [get_ports SWDIOTCK]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_SWDCLK_I/IOBUF3V3/O]
### PMODB ###
#set_property PACKAGE_PIN L10 [get_ports PMOD1_4]
#set_property PACKAGE_PIN M10 [get_ports PMOD1_5]
#set_property PACKAGE_PIN M8 [get_ports PMOD1_6]
#set_property PACKAGE_PIN M9 [get_ports PMOD1_7]
#PMODA pin4 : UART2RXD
#PMODA pin4 : UART2TXD
# LED0 to P0[0]
set_property PACKAGE_PIN R14 [get_ports {P0[0]}]
# LED1 to P0[1]
set_property PACKAGE_PIN P14 [get_ports {P0[1]}]
# LED2 to P0[2]
set_property PACKAGE_PIN N16 [get_ports {P0[2]}]
# LED3 to P0[3]
set_property PACKAGE_PIN M14 [get_ports {P0[3]}]
# SW0 to NRST (Down for active low)
set_property PACKAGE_PIN M20 [get_ports NRST]
# CLK125MHz (need dvider)
##set_property PACKAGE_PIN H16 [get_ports XTAL1]
## Vivado allocations
set_property PACKAGE_PIN V17 [get_ports {P0[10]}]
set_property PACKAGE_PIN R18 [get_ports {P0[11]}]
set_property PACKAGE_PIN T17 [get_ports {P0[12]}]
set_property PACKAGE_PIN R17 [get_ports {P0[13]}]
set_property PACKAGE_PIN R16 [get_ports {P0[14]}]
set_property PACKAGE_PIN W16 [get_ports {P0[15]}]
set_property PACKAGE_PIN T19 [get_ports {P0[4]}]
set_property PACKAGE_PIN P16 [get_ports {P0[5]}]
set_property PACKAGE_PIN P15 [get_ports {P0[6]}]
set_property PACKAGE_PIN P18 [get_ports {P0[7]}]
set_property PACKAGE_PIN N17 [get_ports {P0[8]}]
set_property PACKAGE_PIN V18 [get_ports {P0[9]}]
set_property PACKAGE_PIN N20 [get_ports {P1[10]}]
set_property PACKAGE_PIN P19 [get_ports {P1[11]}]
set_property PACKAGE_PIN N18 [get_ports {P1[12]}]
set_property PACKAGE_PIN U19 [get_ports {P1[13]}]
set_property PACKAGE_PIN U15 [get_ports {P1[14]}]
set_property PACKAGE_PIN U14 [get_ports {P1[15]}]
set_property PACKAGE_PIN V16 [get_ports {P1[4]}]
set_property PACKAGE_PIN W20 [get_ports {P1[5]}]
set_property PACKAGE_PIN V20 [get_ports {P1[6]}]
set_property PACKAGE_PIN U20 [get_ports {P1[7]}]
set_property PACKAGE_PIN T20 [get_ports {P1[8]}]
set_property PACKAGE_PIN P20 [get_ports {P1[9]}]
set_property PACKAGE_PIN W15 [get_ports VDD]
set_property PACKAGE_PIN V15 [get_ports VDDIO]
set_property PACKAGE_PIN U17 [get_ports VSS]
set_property PACKAGE_PIN T16 [get_ports VSSIO]
set_property PACKAGE_PIN Y14 [get_ports XTAL2]
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_synth.tcl 0 → 100644
+ 1
− 0
View file @ 108772f7
synth_design -top cmsdk_mcu_chip -part xc7z020clg400-1
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_timing.xdc 0 → 100644
+ 95
− 0
View file @ 108772f7
##################################################################################
## ##
## ZYNQ timing XDC ##
## ##
##################################################################################
create_clock -name CLK -period 30 [get_ports XTAL1]
create_clock -name VCLK -period 30 -waveform {5 20}
create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
create_clock -name VSWCLK -period 60 -waveform {5 35}
set_clock_groups -name async_clk_swclock -asynchronous \
-group [get_clocks -include_generated_clocks CLK] \
-group [get_clocks -include_generated_clocks VSWCLK]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_3]
#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
#set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {led_4bits_tri_o[*]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[0]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[1]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[2]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[3]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[4]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[5]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[6]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[7]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[8]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[9]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[10]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[11]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[11]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[12]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[13]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[13]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[14]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[15]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[15]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[0]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[1]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[2]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[3]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[4]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[5]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[6]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[7]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[8]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[9]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[10]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[11]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[11]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[12]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[13]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[13]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[14]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[15]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[15]}]
#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
#connect_debug_port dbg_hub/clk [get_nets clk]
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_synth.tcl 0 → 100644
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synth_design -top cmsdk_mcu_chip -part xczu7ev-ffvc1156-2-e
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_timing.xdc 0 → 100644
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##################################################################################
## ##
## ZYNQ timing XDC ##
## ##
##################################################################################
create_clock -name CLK -period 30 [get_ports XTAL1]
create_clock -name VCLK -period 30 -waveform {5 20}
create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
create_clock -name VSWCLK -period 60 -waveform {5 35}
set_clock_groups -name async_clk_swclock -asynchronous \
-group [get_clocks -include_generated_clocks CLK] \
-group [get_clocks -include_generated_clocks VSWCLK]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[0]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[1]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[2]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[3]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[4]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[5]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[6]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[7]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[8]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[9]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[10]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[11]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[11]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[12]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[13]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[13]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[14]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[15]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[15]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[0]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[1]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[2]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[3]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[4]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[5]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[6]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[7]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[8]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[9]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[10]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[11]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[11]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[12]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[13]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[13]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[14]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[15]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[15]}]
#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
#connect_debug_port dbg_hub/clk [get_nets clk]
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz
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No preview for this file type
FPGALIB/pads/verilog/PAD_INOUT8MA_NOE.v 0 → 100644
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// from GLIB_PADLIB.v
//-----------------------------------------------------------------------------
// soclabs generic IO pad model
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module PAD_INOUT8MA_NOE (
// Inouts
PAD,
// Outputs
I,
// Inputs
O,
NOE
);
inout PAD;
output I;
input O;
input NOE;
IOBUF #(
.IOSTANDARD ("LVCMOS33"),
.DRIVE(8)
) IOBUF3V3 (
.O(I),
.IO(PAD),
.I(O),
.T(NOE)
);
endmodule // PAD_INOUT8MA_NOE
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