Merge pull request #1 from XiaoanHe/17/11/2022--23/11/2022

17/11/2022  23/11/2022

Individual_Project/Core_Arithmetic/Arithmetic_tb.sv

+/////////////////////////////////////////////////////////////////////
+// Design unit: Arithmetic Testbench
+//            :
+// File name  : Arithmetic_tb.sv
+//            :
+// Description: Test Posit Adder Arithmetic
+//            :
+// Limitations: None
+//            : 
+// System     : SystemVerilog IEEE 1800-2005
+//            :
+// Author     : Xiaoan He (Jasper)
+//            : xh2g20@ecs.soton.ac.uk
+//
+// Revision   : Version 1.0 23/11/2022
+/////////////////////////////////////////////////////////////////////
+function [31:0] log2;
+input reg [31:0] value;
+	begin
+	value = value-1;
+	for (log2=0; value>0; log2=log2+1)
+        	value = value>>1;
+      	end
+endfunction
+
+module Arithmetic_tb;
+parameter N = 8, RS = log2(N), ES = 3;
+
+// input logic
+logic signed [N-2:0] InRemain1, InRemain2;
+logic Sign1, Sign2;
+logic signed [RS:0] RegimeValue1, RegimeValue2;
+logic [ES-1:0] Exponent1, Exponent2;
+logic [N-ES+2:0] Mantissa1, Mantissa2;
+
+// output logic
+logic [N-1:0] Add_Mant
+
+Arithmetic #(.N(N), .ES(ES)) Add1 (.*);
+
+initial
+    begin
+    
+    #10ns InRemain1 = '0, InRemain2 = '0, Sign1 = '0, Sign2 = '0, RegimeValue1 = '0, RegimeValue2 = '0, 
+          Exponent1 = '0, Exponent2 = '0, Mantissa1 = '0, Mantissa2 = '0;
+
+    #50ns InRemain1 = 7'b1110_010, InRemain2 = 7'b110_111_0, Sign1 = 0, Sign2 = 0, RegimeValue1 = 2, RegimeValue2 = 1,
+          Exponent1 = 3'b010, Exponent2 = 3'b111, Mantissa1 = '0, Mantissa2 = '0;
+
+    end
+
+endmodule
\ No newline at end of file

Individual_Project/Core_Arithmetic/Posit_Adder_Arithmetic.sv

+/////////////////////////////////////////////////////////////////////
+// Design unit: Posit Adder Arithmetic
+//            :
+// File name  : Posit_Adder_Arithmetic.sv
+//            :
+// Description: Mantissa addition and subtraction
+//            : exponent and regime computation
+//            :
+// Limitations: None
+//            : 
+// System     : SystemVerilog IEEE 1800-2005
+//            :
+// Author     : Xiaoan He (Jasper)
+//            : xh2g20@ecs.soton.ac.uk
+//
+// Revision   : Version 1.0 23/11/2022
+/////////////////////////////////////////////////////////////////////
+
+function [31:0] log2;
+    input reg [31:0] value;
+        begin
+            value = value-1;
+            for (log2=0; value>0; log2=log2+1)
+                value = value>>1;
+        end
+endfunction
+
+module Arithmetic #(parameter N = 8, parameter ES = 3, parameter RS = log2(N)) 
+(
+    input logic signed [N-2:0] InRemain1, InRemain2,
+    input logic Sign1, Sign2,
+    input logic signed [RS:0] RegimeValue1, RegimeValue2,
+    input logic [ES-1:0] Exponent1, Exponent2,
+    input logic [N-ES+2:0] Mantissa1, Mantissa2,
+    output logic [N-1:0] Add_Mant
+);
+
+// Confirm the operation (s1 xor s2)
+logic Operation = Sign1 ^ Sign2 ;
+
+// Find the greater input
+logic Greater_Than = (InRemain1[N-2:0] >  InRemain2[N-2:0])? 1'b1 : 1'b0;
+
+// Assign components to corresponding logic, L - Large S - Small
+logic LS = Greater_Than ? Sign1 : Sign2;
+logic LR = Greater_Than ? RegimeValue1 : RegimeValue2;
+logic LRC = Greater_Than? InRemain1[N-2] : InRemain2[N-2];
+logic LE = Greater_Than ? Exponent1 : Exponent2;
+logic LM = Greater_Than ? Mantissa1 : Mantissa2;
+
+logic SS = Greater_Than ? Sign2 : Sign1;
+logic SR = Greater_Than ? RegimeValue2 : RegimeValue1;
+logic SRC = Greater_Than? InRemain2[N-2] : InRemain1[N-2];
+logic SE = Greater_Than ? Exponent2 : Exponent1;
+logic SM = Greater_Than ? Mantissa2 : Mantissa1;
+
+// Mantissa Addition
+
+logic sign [RS:0] R_diff;
+/*
+find regime difference, 
+when both of them are +ve, the difference is RV1 - RV2
+when RV1 +ve but RV2 -ve, the difference is RV1 + RV2
+when RV1 -ve => RV2 also -ve, still RV1 - RV2
+*/
+if (RegimeValue1 >= 0 || RegimeValue2 >= 0)
+    R_diff = RegimeValue1 - RegimeValue2;
+else if (RegimeValue1 >= 0 || RegimeValue2 < 0)
+    R_diff = RegimeValue1 + RegimeValue2;
+else if (RegimeValue1 < 0)
+    R_diff = RegimeValue1 - RegimeValue2;
+
+logic E_diff;
+/*
+after the R_diff found, remember that the regime contributes into the exponent
+as (Useed ^ RegimeValue) where Useed = 2^(2^ES) 
+so the E_diff is (R_diff x log2(useed) + LE - SE)
+the reason why it is R_diff x log2(useed) is
+the exponent (2 ^ what)is what we want to find
+for exponent bits, it is the difference
+for regime bits, they are log2(Useed ^ RegimeValue) which is RegimeValue x (2^ES)
+*/
+E_diff = (R_diff*log2(2**(2**(ES)))) + (LE - SE); 
+
+logic SM_tmp = SM >> E_diff;
+logic Add_Mant = Operation ?  LM + SM_tmp : LM - SM_tmp;
+endmodule
\ No newline at end of file

Individual_Project/Core_Arithmetic/Posit_Arithmetic.mpf

+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+maxii = $MODEL_TECH/../altera/vhdl/maxii
+maxv = $MODEL_TECH/../altera/vhdl/maxv
+fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
+sgate = $MODEL_TECH/../altera/vhdl/sgate
+arriaii = $MODEL_TECH/../altera/vhdl/arriaii
+arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
+arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
+arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
+arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
+arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
+stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
+stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
+stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
+cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
+cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
+cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
+cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
+stratixv = $MODEL_TECH/../altera/vhdl/stratixv
+stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
+stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
+arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
+arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
+arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
+arriav = $MODEL_TECH/../altera/vhdl/arriav
+cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
+twentynm = $MODEL_TECH/../altera/vhdl/twentynm
+twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
+twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
+cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
+;
+; Verilog Section
+;
+altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
+altera_ver = $MODEL_TECH/../altera/verilog/altera
+altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
+lpm_ver = $MODEL_TECH/../altera/verilog/220model
+220model_ver = $MODEL_TECH/../altera/verilog/220model
+maxii_ver = $MODEL_TECH/../altera/verilog/maxii
+maxv_ver = $MODEL_TECH/../altera/verilog/maxv
+fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
+sgate_ver = $MODEL_TECH/../altera/verilog/sgate
+arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
+arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
+arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
+arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
+arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
+arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
+stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
+stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
+stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
+stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
+stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
+stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
+arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
+arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
+arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
+arriav_ver = $MODEL_TECH/../altera/verilog/arriav
+arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
+arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
+cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
+cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
+cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
+cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
+cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
+cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
+cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
+twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
+twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
+twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
+cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100 ns
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
+[Project]
+** Warning: ; Warning -- Do not edit the project properties directly.
+;            Property names are dynamic in nature and property
+;            values have special syntax.  Changing property data directly
+;            can result in a corrupt MPF file.  All project properties
+;            can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 2
+Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Posit_Adder_Arithmetic.sv
+Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Arithmetic_tb.sv
+Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick = 
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick = 
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick = 
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick = 
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick = 
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick = 
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick = 
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick = 
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick = 
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick = 
+XML_DoubleClick = Edit
+XML_CustomDoubleClick = 
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick = 
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick = 
+TDB_DoubleClick = Edit
+TDB_CustomDoubleClick = 
+UPF_DoubleClick = Edit
+UPF_CustomDoubleClick = 
+PCF_DoubleClick = Edit
+PCF_CustomDoubleClick = 
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick = 
+VRM_DoubleClick = Edit
+VRM_CustomDoubleClick = 
+DEBUGDATABASE_DoubleClick = Edit
+DEBUGDATABASE_CustomDoubleClick = 
+DEBUGARCHIVE_DoubleClick = Edit
+DEBUGARCHIVE_CustomDoubleClick = 
+Project_Major_Version = 2020
+Project_Minor_Version = 1

Individual_Project/Core_Arithmetic/work/_info

+m255
+K4
+z2
+13
+!s112 1.1
+!i10d 8192
+!i10e 25
+!i10f 100
+cModel Technology
+dH:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction

Individual_Project/Data Extraction/Data_Extraction.cr.mti

+{H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Posit_Extraction.sv} {1 {vlog -work work -sv -stats=none {H:\INDIVIDUAL PROJECT\Posit\Individual_Project\Data Extraction\Posit_Extraction.sv}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling package Posit_Extraction_sv_unit
+-- Compiling module Data_Extraction
+
+Top level modules:
+	Data_Extraction
+
+} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Leading_Bit_Detector.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Leading_Bit_Detector.sv}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module Leading_Bit_Detector
+
+Top level modules:
+	Leading_Bit_Detector
+
+} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Test_Data_Extraction.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Test_Data_Extraction.sv}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling package Test_Data_Extraction_sv_unit
+-- Compiling module Test_Data_Extraction
+
+Top level modules:
+	Test_Data_Extraction
+
+} {} {}}

Individual_Project/Data Extraction/Leading_Bit_Detector.sv

+/////////////////////////////////////////////////////////////////////
+// Design unit: Leading Bit Detector
+//            :
+// File name  : Leading_Bit_Detector.sv
+//            :
+// Description: Given the first bit of the regime bit
+//              find the first bit different from it
+//            :
+// Limitations: None
+//            : 
+// System     : SystemVerilog IEEE 1800-2005
+//            :
+// Author     : Xiaoan He (Jasper)
+//            : xh2g20@ecs.soton.ac.uk
+//
+// Revision   : Version 1.0 21/11/2022
+/////////////////////////////////////////////////////////////////////
+
+module Leading_Bit_Detector #( parameter N = 8, parameter ES = 3, parameter RS = log2(N))
+(
+    input logic signed [N-2:0] InRemain,
+    output logic signed [RS:0] EndPosition,
+    output logic RegimeCheck
+);
+
+function [31:0] log2;
+input reg [31:0] value;
+	begin
+	value = value-1;
+	for (log2=0; value>0; log2=log2+1)
+        	value = value>>1;
+      	end
+endfunction
+
+//logic RegimeCheck; 
+int i;
+
+always_comb
+begin
+    RegimeCheck = InRemain[N-2]; //the MSB of InRemain (In[6])is the number to be checked
+    
+    EndPosition = '0;
+    EndPosition = EndPosition + 1'b1; // initial EP starts from InRemain[1] as InRemain[0] is RC
+
+    for(i = 1; i < (N-2); i++) 
+        begin
+            /* 
+            compareing MSB of InRemain to the follwing bits
+            until the different bit turns up    
+            */
+            if (RegimeCheck == InRemain[((N-2)-i)])
+                //begin
+                EndPosition = EndPosition + 1'b1;
+                //end
+            else 
+                break;
+        end
+
+end
+endmodule
\ No newline at end of file

Individual_Project/Data Extraction/Posit_Extraction.sv

+/////////////////////////////////////////////////////////////////////
+// Design unit: DataExtraction
+//            :
+// File name  : Posit_Extraction.sv
+//            :
+// Description: Extracting posit element from n bits binary number
+//            :
+// Limitations: None
+//            : 
+// System     : SystemVerilog IEEE 1800-2005
+//            :
+// Author     : Xiaoan He (Jasper)
+//            : xh2g20@ecs.soton.ac.uk
+//
+// Revision   : Version 1.0 22/11/2022
+/////////////////////////////////////////////////////////////////////
+
+// `ifndef log_2
+// `define log_2
+// `include "log_2.sv"
+
+function [31:0] log2;
+    input reg [31:0] value;
+        begin
+            value = value-1;
+            for (log2=0; value>0; log2=log2+1)
+                value = value>>1;
+        end
+endfunction
+
+module Data_Extraction #( parameter N = 8, parameter ES = 3, parameter RS = log2(N))
+(
+    input logic signed [N-1:0] In,
+    output logic Sign,
+    output logic signed [RS:0] RegimeValue,
+    output logic [ES-1:0] Exponent,
+    output logic [N-ES+2:0] Mantissa
+);
+
+logic signed [N-2:0] InRemain;
+logic RegimeCheck; 
+logic [RS:0] EndPosition;
+logic signed [N-2:0] ShiftedRemain;
+logic [(N-ES+2)-1-(N-ES-2)-1:0] ZERO = '0;
+int i;
+Leading_Bit_Detector #(.N(N), .ES(ES)) LBD1 (.*);
+
+always_comb
+begin
+    // Sign Bit Extraction
+    Sign = In[N-1];
+    InRemain = Sign ? (~In[N-2:0] + 1'b1) : In[N-2:0]; // if sign bit is true, then 2's compliment
+
+    // Regime Bits Extraction
+    /*
+     There is a Leading_Bit_Detector defined before the always_comb block 
+     which takes the input without sign bit as module input and outputs 
+     EndPosition of Regime Bits and RegimeCheck which is the 1st bit of Regime bits
+    */
+    if(RegimeCheck == 1'b1)
+        RegimeValue = EndPosition - 1;
+    else if (RegimeCheck == 0)
+        RegimeValue = -EndPosition;
+
+    //Exponent Bits Extraction
+    ShiftedRemain = InRemain << (EndPosition + 1 );
+    Exponent = ShiftedRemain[N-1:((N-1)-ES)];
+
+    //Mantissa Bits Extraction
+    Mantissa = {1'b1, ShiftedRemain[N-ES-2:0], ZERO};
+end
+endmodule
\ No newline at end of file

Individual_Project/Data Extraction/Test_Data_Extraction.sv

+/////////////////////////////////////////////////////////////////////
+// Design unit: TestDataExtraction
+//            :
+// File name  : testExtract.sv
+//            :
+// Description: Testbench for extracting posit element 
+//              from n bits binary number
+//            :
+// Limitations: None
+//            : 
+// System     : SystemVerilog IEEE 1800-2005
+//            :
+// Author     : Xiaoan He (Jasper)
+//            : xh2g20@ecs.soton.ac.uk
+//
+// Revision   : Version 1.0 21/11/2022
+/////////////////////////////////////////////////////////////////////
+function [31:0] log2;
+input reg [31:0] value;
+	begin
+	value = value-1;
+	for (log2=0; value>0; log2=log2+1)
+        	value = value>>1;
+      	end
+endfunction
+
+module Test_Data_Extraction;
+parameter N = 8, RS = log2(N), ES = 3;
+
+//input logic
+logic signed [N-1:0]In;
+
+//output logic
+logic Sign;
+logic signed [RS:0] RegimeValue;
+logic [ES-1:0] Exponent;
+logic [N-ES+2:0] Mantissa;
+
+Data_Extraction #(.N(N), .ES(ES)) extract1 (.*);
+
+initial
+    begin
+        // initial input is nothing
+        #10ns In = 8'b0_0000000;
+        #50ns In = 8'b0_01_000_01;  // R = -1, E = 100, M = 1.01
+        #50ns In = 8'b0_10_001_10;  // R = 0, E = 100, M = 1.1
+        #50ns In = 8'b0_001_010_0;  // R = -2, E = 100, M = 1.01
+        #50ns In = 8'b0_110_011_1;  // R = 1, E = 100, M = 1.01
+        #50ns In = 8'b0_0001_100;   // R = -3, E = 100, M = 1.01
+        #50ns In = 8'b0_1110_101;   // R = 2, E = 100, M = 1.01
+        #50ns In = 8'b1_01_000_01;  // 101_1111
+        #50ns In = 8'b1_10_001_10;  // 011_1010
+        #50ns In = 8'b1_001_010_0;  // 110_1100
+        #50ns In = 8'b1_110_011_1;  // 001_s1001
+        #50ns In = 8'b1_0001_100;   // 111_0100
+        #50ns In = 8'b1_1110_101;   // 000_1011
+
+
+    end
+endmodule
\ No newline at end of file

Individual_Project/Data Extraction/log_2.sv

+/////////////////////////////////////////////////////////////////////
+// Design unit: Logarithm Base 2
+//            :
+// File name  : log_2.sv
+//            :
+// Description: Just be used to compute the Regime Size (RS)
+//            : which is equal to log2(the number of total bits)
+//            :
+// Limitations: None
+//            : 
+// System     : SystemVerilog IEEE 1800-2005
+//            :
+// Author     : Xiaoan He (Jasper)
+//            : xh2g20@ecs.soton.ac.uk
+//
+// Revision   : Version 1.0 19/11/2022
+/////////////////////////////////////////////////////////////////////
+
+#ifndef log_2
+#define log_2
+
+function [31:0] log2;
+input logic [31:0] value;
+	begin
+	value = value-1;
+	for (log2=0; value>0; log2=log2+1)
+        	value = value>>1;
+      	end
+endfunction
\ No newline at end of file

Individual_Project/Data Extraction/wave

+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -radix binary -childformat {{{/Test_Data_Extraction/In[7]} -radix binary} {{/Test_Data_Extraction/In[6]} -radix binary} {{/Test_Data_Extraction/In[5]} -radix binary} {{/Test_Data_Extraction/In[4]} -radix binary} {{/Test_Data_Extraction/In[3]} -radix binary} {{/Test_Data_Extraction/In[2]} -radix binary} {{/Test_Data_Extraction/In[1]} -radix binary} {{/Test_Data_Extraction/In[0]} -radix binary}} -expand -subitemconfig {{/Test_Data_Extraction/In[7]} {-height 15 -radix binary} {/Test_Data_Extraction/In[6]} {-height 15 -radix binary} {/Test_Data_Extraction/In[5]} {-height 15 -radix binary} {/Test_Data_Extraction/In[4]} {-height 15 -radix binary} {/Test_Data_Extraction/In[3]} {-height 15 -radix binary} {/Test_Data_Extraction/In[2]} {-height 15 -radix binary} {/Test_Data_Extraction/In[1]} {-height 15 -radix binary} {/Test_Data_Extraction/In[0]} {-height 15 -radix binary}} /Test_Data_Extraction/In
+add wave -noupdate -radix decimal -childformat {{{/Test_Data_Extraction/RegimeValue[3]} -radix decimal} {{/Test_Data_Extraction/RegimeValue[2]} -radix decimal} {{/Test_Data_Extraction/RegimeValue[1]} -radix decimal} {{/Test_Data_Extraction/RegimeValue[0]} -radix decimal}} -expand -subitemconfig {{/Test_Data_Extraction/RegimeValue[3]} {-height 15 -radix decimal} {/Test_Data_Extraction/RegimeValue[2]} {-height 15 -radix decimal} {/Test_Data_Extraction/RegimeValue[1]} {-height 15 -radix decimal} {/Test_Data_Extraction/RegimeValue[0]} {-height 15 -radix decimal}} /Test_Data_Extraction/RegimeValue
+add wave -noupdate -radix binary -childformat {{{/Test_Data_Extraction/Exponent[2]} -radix binary} {{/Test_Data_Extraction/Exponent[1]} -radix binary} {{/Test_Data_Extraction/Exponent[0]} -radix binary}} -expand -subitemconfig {{/Test_Data_Extraction/Exponent[2]} {-height 15 -radix binary} {/Test_Data_Extraction/Exponent[1]} {-height 15 -radix binary} {/Test_Data_Extraction/Exponent[0]} {-height 15 -radix binary}} /Test_Data_Extraction/Exponent
+add wave -noupdate -radix binary -childformat {{{/Test_Data_Extraction/Mantissa[7]} -radix binary} {{/Test_Data_Extraction/Mantissa[6]} -radix binary} {{/Test_Data_Extraction/Mantissa[5]} -radix binary} {{/Test_Data_Extraction/Mantissa[4]} -radix binary} {{/Test_Data_Extraction/Mantissa[3]} -radix binary} {{/Test_Data_Extraction/Mantissa[2]} -radix binary} {{/Test_Data_Extraction/Mantissa[1]} -radix binary} {{/Test_Data_Extraction/Mantissa[0]} -radix binary}} -expand -subitemconfig {{/Test_Data_Extraction/Mantissa[7]} {-height 15 -radix binary} {/Test_Data_Extraction/Mantissa[6]} {-height 15 -radix binary} {/Test_Data_Extraction/Mantissa[5]} {-height 15 -radix binary} {/Test_Data_Extraction/Mantissa[4]} {-height 15 -radix binary} {/Test_Data_Extraction/Mantissa[3]} {-height 15 -radix binary} {/Test_Data_Extraction/Mantissa[2]} {-height 15 -radix binary} {/Test_Data_Extraction/Mantissa[1]} {-height 15 -radix binary} {/Test_Data_Extraction/Mantissa[0]} {-height 15 -radix binary}} /Test_Data_Extraction/Mantissa
+add wave -noupdate -radix binary -expand /Test_Data_Extraction/extract1/InRemain
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {9 ns} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 200
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ns} {525 ns}

Individual_Project/Data Extraction/work/_info

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Individual_Project/Data Extraction/work/_vmake

+m255
+K4
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