Delete Posit-Multiplier directory

Posit-Multiplier/DSR_left_N_S.v

-module DSR_left_N_S(a,b,c);
-        parameter N=16;
-        parameter S=4;
-        input [N-1:0] a;
-        input [S-1:0] b;
-        output [N-1:0] c;
-
-wire [N-1:0] tmp [S-1:0];
-assign tmp[0]  = b[0] ? a << 7'd1  : a; 
-genvar i;
-generate
-	for (i=1; i<S; i=i+1)begin:loop_blk
-		assign tmp[i] = b[i] ? tmp[i-1] << 2**i : tmp[i-1];
-	end
-endgenerate
-assign c = tmp[S-1];
-
-endmodule

Posit-Multiplier/DSR_right_N_S.v

-module DSR_right_N_S(a,b,c);
-        parameter N=16;
-        parameter S=4;
-        input [N-1:0] a;
-        input [S-1:0] b;
-        output [N-1:0] c;
-
-wire [N-1:0] tmp [S-1:0];
-assign tmp[0]  = b[0] ? a >> 7'd1  : a; 
-genvar i;
-generate
-	for (i=1; i<S; i=i+1)begin:loop_blk
-		assign tmp[i] = b[i] ? tmp[i-1] >> 2**i : tmp[i-1];
-	end
-endgenerate
-assign c = tmp[S-1];
-
-endmodule

Posit-Multiplier/LOD_N.v

-module LOD_N (in, out);
-
-  function [31:0] log2;
-    input reg [31:0] value;
-    begin
-      value = value-1;
-      for (log2=0; value>0; log2=log2+1)
-	value = value>>1;
-    end
-  endfunction
-
-parameter N = 64;
-parameter S = log2(N); 
-input [N-1:0] in;
-output [S-1:0] out;
-
-wire vld;
-LOD #(.N(N)) l1 (in, out, vld);
-endmodule
-
-
-module LOD (in, out, vld);
-
-  function [31:0] log2;
-    input reg [31:0] value;
-    begin
-      value = value-1;
-      for (log2=0; value>0; log2=log2+1)
-	value = value>>1;
-    end
-  endfunction
-
-
-parameter N = 64;
-parameter S = log2(N);
-
-   input [N-1:0] in;
-   output [S-1:0] out;
-   output vld;
-
-  generate
-    if (N == 2)
-      begin
-	assign vld = |in;
-	assign out = ~in[1] & in[0];
-      end
-    else if (N & (N-1))
-      LOD #(1<<S) LOD ({1<<S {1'b0}} | in,out,vld);
-    else
-      begin
-	wire [S-2:0] out_l, out_h;
-	wire out_vl, out_vh;
-	LOD #(N>>1) l(in[(N>>1)-1:0],out_l,out_vl);
-	LOD #(N>>1) h(in[N-1:N>>1],out_h,out_vh);
-	assign vld = out_vl | out_vh;
-	assign out = out_vh ? {1'b0,out_h} : {out_vl,out_l};
-      end
-  endgenerate
-endmodule

Posit-Multiplier/LZD_N.v

-module LZD_N (in, out);
-
-  function [31:0] log2;
-    input reg [31:0] value;
-    begin
-      value = value-1;
-      for (log2=0; value>0; log2=log2+1)
-	value = value>>1;
-    end
-  endfunction
-
-parameter N = 64;
-parameter S = log2(N); 
-input [N-1:0] in;
-output [S-1:0] out;
-
-wire vld;
-LZD #(.N(N)) l1 (in, out, vld);
-endmodule
-
-
-module LZD (in, out, vld);
-
-  function [31:0] log2;
-    input reg [31:0] value;
-    begin
-      value = value-1;
-      for (log2=0; value>0; log2=log2+1)
-	value = value>>1;
-    end
-  endfunction
-
-
-parameter N = 64;
-parameter S = log2(N);
-
-   input [N-1:0] in;
-   output [S-1:0] out;
-   output vld;
-
-  generate
-    if (N == 2)
-      begin
-	assign vld = ~∈
-	assign out = in[1] & ~in[0];
-      end
-    else if (N & (N-1))
-      LZD #(1<<S) LZD ({1<<S {1'b0}} | in,out,vld);
-    else
-      begin
-	wire [S-2:0] out_l;
-	wire [S-2:0] out_h;
-	wire out_vl, out_vh;
-	LZD #(N>>1) l(in[(N>>1)-1:0],out_l,out_vl);
-	LZD #(N>>1) h(in[N-1:N>>1],out_h,out_vh);
-	assign vld = out_vl | out_vh;
-	assign out = out_vh ? {1'b0,out_h} : {out_vl,out_l};
-      end
-  endgenerate
-endmodule

Posit-Multiplier/Posit_Multiplier_Reference.cr.mti

-{H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/posit_mult.v} {1 {vlog -work work -stats=none {H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/posit_mult.v}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module posit_mult
-
-Top level modules:
-	posit_mult
-
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/LOD_N.v} {1 {vlog -work work -stats=none {H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/LOD_N.v}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module LOD_N
--- Compiling module LOD
-
-Top level modules:
-	LOD_N
-
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/data_extract.v} {1 {vlog -work work -stats=none {H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/data_extract.v}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module data_extract
-
-Top level modules:
-	data_extract
-
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/DSR_right_N_S.v} {1 {vlog -work work -stats=none {H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/DSR_right_N_S.v}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module DSR_right_N_S
-
-Top level modules:
-	DSR_right_N_S
-
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/DSR_left_N_S.v} {1 {vlog -work work -stats=none {H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/DSR_left_N_S.v}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module DSR_left_N_S
-
-Top level modules:
-	DSR_left_N_S
-
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/LZD_N.v} {1 {vlog -work work -stats=none {H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/LZD_N.v}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module LZD_N
--- Compiling module LZD
-
-Top level modules:
-	LZD_N
-
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/posit_mult_8bit_tb.v} {1 {vlog -work work -stats=none {H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/posit_mult_8bit_tb.v}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module posit_mult_8bit_tb_v
-
-Top level modules:
-	posit_mult_8bit_tb_v
-
-} {} {}}

Posit-Multiplier/Readme.md

-# Posit Multiplier HDL Arithmetic:
-
-Here, we can find the Posit Multiplier module. It includes following files.
-
-1. posit_mult.v         :       Top-module which takes N (posit word size) and es (posit exponent size).
-2. data_extract.v       :       Posit data extract sub-module.
-3. DSR_right_N_S.v      :       Dynamic right shifter sub-module.
-4. DSR_left_N_S.v       :       Dynamic left shifter sub-module.
-5. LOD_N.v              :       Leading-One-Detector sub-module.
-6. LZD_N.v              :       Leading-Zero-Detector sub-module.
-
-Below are the files for test-module for posit mult with N=8, ES=4 (User can test for other options).
-It is an all exhaustive test for 8-bit operands (excluding Infinity multiplications to avoid comparision with julia pachage interupts for them).
-
-7. posit_mult_8bit_tb.v : Test-bench module.
-8. posit_mult_8bit.sh           : A bash script to invoke and run modelsim simulator to run the test-bench.
-9. Pin1_8bit.txt                : Input-1 8-bit (Infinity multiplications are removed to avoid interupt from corresponding julia result comparisions)
-10. Pin2_8bit.txt               : Input-2 8-bit (Infinity multiplications are removed to avoid interupt from corresponding julia result comparisions)
-11. Pout_8bit_ES4.txt           : Pre-stored posit multiplication results for comparison purpose.
-
-**. error_8bit.txt              : File will be generated during simulation which contains the difference of
-                                result produce by the Verilog module with pre-stored posit addition results.
-
-
-12. julia_posit8_mult.sh        : This is a bash shell script for posit addition using julia posit package. It is currently using 8-bit inputs.
-                                  Julia posit package can be downloaded from https://github.com/interplanetary-robot/SigmoidNumbers

Posit-Multiplier/data_extract.v

-module data_extract(in, rc, regime, exp, mant, Lshift);
-
-function [31:0] log2;
-input reg [31:0] value;
-	begin
-	value = value-1;
-	for (log2=0; value>0; log2=log2+1)
-        	value = value>>1;
-      	end
-endfunction
-
-parameter N=16;
-parameter Bs=log2(N);
-parameter es = 2;
-input [N-1:0] in;
-output rc;
-output [Bs-1:0] regime, Lshift;
-output [es-1:0] exp;
-output [N-es-1:0] mant;
-
-wire [N-1:0] xin = in;
-assign rc = xin[N-2];
-wire [Bs-1:0] k0, k1;
-LOD_N #(.N(N)) xinst_k0(.in({xin[N-2:0],1'b0}), .out(k0));
-LZD_N #(.N(N)) xinst_k1(.in({xin[N-3:0],2'b0}), .out(k1));
-
-assign regime = xin[N-2] ? k1 : k0;
-assign Lshift = xin[N-2] ? k1+1 : k0;
-
-wire [N-1:0] xin_tmp;
-DSR_left_N_S #(.N(N), .S(Bs)) ls (.a({xin[N-3:0],2'b0}),.b(Lshift),.c(xin_tmp));
-
-assign exp= xin_tmp[N-1:N-es];
-assign mant= xin_tmp[N-es-1:0];
-
-endmodule
-

Posit-Multiplier/julia_posit8_mult.sh

-#!/bin/bash
-
-function posit_mult(y1,y2)
-		print(PS(y1),"\t")
-		print(PS(y2),"\t")
-	       	println(PS(y1)*PS(y2))
-end
-
-if ARGS[1] == "--help"
-	println("Usgae: julia julia_posit8_mult.sh N<size of operands> es<Exp size>")
-else
-	using SigmoidNumbers
-	N = parse(ARGS[1])
-	es = parse(ARGS[2])
-	PS=Posit{N,es}
-	f1=open("Pin1_8bit.txt")
-	f2=open("Pin2_8bit.txt")
-	lines1 = readlines(f1)
-	lines2 = readlines(f2)
-	for l = 1:65536
-		x1="0b"lines1[l]
-		x2="0b"lines2[l]
-		y1=parse(x1)
-		y2=parse(x2)
-		posit_arith(y1,y2)
-	end
-end
-
-

Posit-Multiplier/posit_mult.v

-`timescale 1ns / 1ps
-
-module posit_mult (in1, in2, start, out, inf, zero, done);
-
-function [31:0] log2;
-input reg [31:0] value;
-	begin
-	value = value-1;
-	for (log2=0; value>0; log2=log2+1)
-        	value = value>>1;
-      	end
-endfunction
-
-parameter N = 16;
-parameter Bs = log2(N); 
-parameter es = 3;
-
-input [N-1:0] in1, in2;
-input start; 
-output [N-1:0] out;
-output inf, zero;
-output done;
-
-wire start0= start;
-wire s1 = in1[N-1];
-wire s2 = in2[N-1];
-wire zero_tmp1 = |in1[N-2:0];
-wire zero_tmp2 = |in2[N-2:0];
-wire inf1 = in1[N-1] & (~zero_tmp1),
-	inf2 = in2[N-1] & (~zero_tmp2);
-wire zero1 = ~(in1[N-1] | zero_tmp1),
-	zero2 = ~(in2[N-1] | zero_tmp2);
-assign inf = inf1 | inf2,
-	zero = zero1 & zero2;
-
-//Data Extraction
-wire rc1, rc2;
-wire [Bs-1:0] regime1, regime2, Lshift1, Lshift2;
-wire [es-1:0] e1, e2;
-wire [N-es-1:0] mant1, mant2;
-wire [N-1:0] xin1 = s1 ? -in1 : in1;
-wire [N-1:0] xin2 = s2 ? -in2 : in2;
-data_extract #(.N(N),.es(es)) uut_de1(.in(xin1), .rc(rc1), .regime(regime1), .exp(e1), .mant(mant1), .Lshift(Lshift1));
-data_extract #(.N(N),.es(es)) uut_de2(.in(xin2), .rc(rc2), .regime(regime2), .exp(e2), .mant(mant2), .Lshift(Lshift2));
-
-wire [N-es:0] m1 = {zero_tmp1,mant1}, 
-	m2 = {zero_tmp2,mant2};
-
-//Sign, Exponent and Mantissa Computation
-wire mult_s = s1 ^ s2;
-
-wire [2*(N-es)+1:0] mult_m = m1*m2;
-wire mult_m_ovf = mult_m[2*(N-es)+1];
-wire [2*(N-es)+1:0] mult_mN = ~mult_m_ovf ? mult_m << 1'b1 : mult_m;
-
-wire [Bs+1:0] r1 = rc1 ? {2'b0,regime1} : -regime1;
-wire [Bs+1:0] r2 = rc2 ? {2'b0,regime2} : -regime2;
-wire [Bs+es+1:0] mult_e  =  {r1, e1} + {r2, e2} + mult_m_ovf;
-
-//Exponent and Regime Computation
-wire [es+Bs:0] mult_eN = mult_e[es+Bs+1] ? -mult_e : mult_e;
-wire [es-1:0] e_o = (mult_e[es+Bs+1] & |mult_eN[es-1:0]) ? mult_e[es-1:0] : mult_eN[es-1:0];
-wire [Bs:0] r_o = (~mult_e[es+Bs+1] || (mult_e[es+Bs+1] & |mult_eN[es-1:0])) ? mult_eN[es+Bs:es] + 1'b1 : mult_eN[es+Bs:es];
-
-//Exponent and Mantissa Packing
-wire [2*N-1:0]tmp_o = {{N{~mult_e[es+Bs+1]}},mult_e[es+Bs+1],e_o,mult_mN[2*(N-es):N-es+2]};
-
-
-//Including Regime bits in Exponent-Mantissa Packing
-wire [2*N-1:0] tmp1_o;
-DSR_right_N_S #(.N(2*N), .S(Bs+1)) dsr2 (.a(tmp_o), .b(r_o[Bs] ? {Bs{1'b1}} : r_o), .c(tmp1_o));
-
-
-//Final Output
-wire [2*N-1:0] tmp1_oN = mult_s ? -tmp1_o : tmp1_o;
-assign out = inf|zero|(~mult_mN[2*(N-es)+1]) ? {inf,{N-1{1'b0}}} : {mult_s, tmp1_oN[N-1:1]},
-	done = start0;
-
-endmodule
-

Posit-Multiplier/posit_mult_8bit.sh

-vlib work
-
-vlog "posit_mult.v" 
-vlog "posit_mult_8bit_tb.v"
-vlog "DSR_right_N_S.v" 
-vlog "LOD_N.v" 
-vlog "LZD_N.v" 
-vlog "DSR_left_N_S.v"
-vlog "data_extract.v"
-
-vsim -t ps work.posit_mult_8bit_tb_v
-view wave
-add wave *
-run -all

Posit-Multiplier/posit_mult_8bit_tb.v

-`timescale 1ns / 1ps
-module posit_mult_8bit_tb_v;
-
-function [31:0] log2;
-input reg [31:0] value;
-	begin
-	value = value-1;
-	for (log2=0; value>0; log2=log2+1)
-        	value = value>>1;
-      	end
-endfunction
-
-parameter N=8;
-parameter Bs=log2(N);
-parameter es=3;
-
-reg [N-1:0] in1, in2;
-reg start; 
-wire [N-1:0] out;
-wire done;
-
-	reg clk;
-	integer outfile;
-
-
-// Instantiate the Unit Under Test (UUT)
-posit_mult #(.N(N), .es(es)) uut (in1, in2, start, out, inf, zero, done);
-
-reg [N-1:0] data1 [1:65534];
-reg [N-1:0] data2 [1:65534];
-initial $readmemb("Pin1_8bit.txt",data1);
-initial $readmemb("Pin2_8bit.txt",data2);
-
-reg [15:0] i;
-	
-	initial begin
-		// Initialize Inputs
-		in1 = 0;
-		in2 = 0;
-		clk = 0;
-		start = 0;
-	
-		
-		// Wait 100 ns for global reset to finish
-		#100 i=0;
-		#20 start = 1;
-                #652790 start = 0;
-		#100;
-		
-		$fclose(outfile);
-		$finish;
-	end
-	
- always #5 clk=~clk;
-
-  always @(posedge clk) begin			
- 	in1=data1[i];	
-	in2=data2[i];
-	if(i==16'hffff)
-  	      $finish;
-	else i = i + 1;
- end
-
-initial outfile = $fopen("error_8bit.txt", "wb");
-
-reg [N-1:0] result [1:65534];
-initial $readmemb("Pout_8bit_ES4.txt",result);
-reg [N-1:0] diff;
-always @(negedge clk) begin
-	if(start)begin
-     	diff = (result[i-1] > out) ? result[i-1]-out : out-result[i-1];
-     	$fwrite(outfile, "%d\n",diff);
-     	end
-end
-endmodule
-

Posit-Multiplier/work/_info

-m255
-K4
-z2
-!s11f vlog 2020.1 2020.02, Feb 28 2020
-13
-!s112 1.1
-!i10d 8192
-!i10e 25
-!i10f 100
-cModel Technology
-dH:/INDIVIDUAL PROJECT/Posit/posit_adder_verilog
-vdata_extract
-Z0 !s110 1675721709
-!i10b 1
-!s100 bjeF6F64W7Lj7z?e;6_fD2
-Z1 !s11b Dg1SIo80bB@j0V0VzS_@n1
-Ib_J[Oh7M8aioU?h;XPOoi3
-Z2 VDg1SIo80bB@j0V0VzS_@n1
-Z3 dH:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier
-Z4 w1560477736
-8H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/data_extract.v
-FH:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/data_extract.v
-!i122 1
-L0 1 36
-Z5 OV;L;2020.1;71
-r1
-!s85 0
-31
-Z6 !s108 1675721709.000000
-!s107 H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/data_extract.v|
-!s90 -reportprogress|300|-work|work|-stats=none|H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/data_extract.v|
-!i113 1
-Z7 o-work work
-Z8 tCvgOpt 0
-vDSR_left_N_S
-Z9 !s110 1675721710
-!i10b 1
-!s100 B?i1M95RNBCz5m0iM@LFO3
-R1
-IMnHzdzDMA_h_gmGFAMU9f2
-R2
-R3
-R4
-8H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/DSR_left_N_S.v
-FH:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/DSR_left_N_S.v
-!i122 2
-Z10 L0 1 18
-R5
-r1
-!s85 0
-31
-R6
-!s107 H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/DSR_left_N_S.v|
-!s90 -reportprogress|300|-work|work|-stats=none|H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/DSR_left_N_S.v|
-!i113 1
-R7
-R8
-n@d@s@r_left_@n_@s
-vDSR_right_N_S
-R9
-!i10b 1
-!s100 OUIjYV3Wfb0T1J7O0;5nK0
-R1
-I1ORn05PS9EAE^@g1`BJ=a1
-R2
-R3
-R4
-8H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/DSR_right_N_S.v
-FH:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/DSR_right_N_S.v
-!i122 3
-R10
-R5
-r1
-!s85 0
-31
-Z11 !s108 1675721710.000000
-!s107 H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/DSR_right_N_S.v|
-!s90 -reportprogress|300|-work|work|-stats=none|H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/DSR_right_N_S.v|
-!i113 1
-R7
-R8
-n@d@s@r_right_@n_@s
-vLOD
-R9
-!i10b 1
-!s100 NGgdm6?:UYZE6fJe=CDMG1
-R1
-I:8jlGKoGdUaQz1l`h8:PM2
-R2
-R3
-R4
-Z12 8H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/LOD_N.v
-Z13 FH:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/LOD_N.v
-!i122 4
-L0 22 38
-R5
-r1
-!s85 0
-31
-R11
-Z14 !s107 H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/LOD_N.v|
-Z15 !s90 -reportprogress|300|-work|work|-stats=none|H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/LOD_N.v|
-!i113 1
-R7
-R8
-n@l@o@d
-vLOD_N
-R9
-!i10b 1
-!s100 ZI7FE7`XoKeKii^RZhd7;1
-R1
-IKCcMdXH84Rh79U2Cg_akG2
-R2
-R3
-R4
-R12
-R13
-!i122 4
-Z16 L0 1 19
-R5
-r1
-!s85 0
-31
-R11
-R14
-R15
-!i113 1
-R7
-R8
-n@l@o@d_@n
-vLZD
-R9
-!i10b 1
-!s100 gnbXAb9=>n6JYcHRHZBb13
-R1
-ILd_gH4O6OU=UF^EbTmVcL2
-R2
-R3
-R4
-Z17 8H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/LZD_N.v
-Z18 FH:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/LZD_N.v
-!i122 5
-L0 22 39
-R5
-r1
-!s85 0
-31
-R11
-Z19 !s107 H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/LZD_N.v|
-Z20 !s90 -reportprogress|300|-work|work|-stats=none|H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/LZD_N.v|
-!i113 1
-R7
-R8
-n@l@z@d
-vLZD_N
-R9
-!i10b 1
-!s100 9a?oF>>8T:iG[B^5h[oZh0
-R1
-Ij9e?5g2Leh52YV]UdFl673
-R2
-R3
-R4
-R17
-R18
-!i122 5
-R16
-R5
-r1
-!s85 0
-31
-R11
-R19
-R20
-!i113 1
-R7
-R8
-n@l@z@d_@n
-vposit_mult
-R9
-!i10b 1
-!s100 42dDeoKEhTEzVlTJ`EIz81
-R1
-I_;jJE=4T[^L<SbP:M[Y7Y1
-R2
-R3
-R4
-8H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/posit_mult.v
-FH:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/posit_mult.v
-!i122 6
-L0 3 77
-R5
-r1
-!s85 0
-31
-R11
-!s107 H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/posit_mult.v|
-!s90 -reportprogress|300|-work|work|-stats=none|H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/posit_mult.v|
-!i113 1
-R7
-R8
-vposit_mult_8bit_tb_v
-R0
-!i10b 1
-!s100 Da^^8jB9ZQQPia6IeA[S:1
-R1
-IZSK;nEFRBS7Y:iUI30@?j0
-R2
-R3
-w1675721622
-8H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/posit_mult_8bit_tb.v
-FH:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/posit_mult_8bit_tb.v
-!i122 0
-L0 2 74
-R5
-r1
-!s85 0
-31
-R6
-!s107 H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/posit_mult_8bit_tb.v|
-!s90 -reportprogress|300|-work|work|-stats=none|H:/INDIVIDUAL PROJECT/Posit/Posit-Multiplier/posit_mult_8bit_tb.v|
-!i113 1
-R7
-R8