Fix gear shift reg in PLL

IP_wrappers/PLL_integration_layer.v

@@ -48,8 +48,8 @@ reg enp_reg;
 reg enr_reg;
 reg gear_shift_reg;
 
-reg [11:0] gear_shift_counter;
-reg [11:0] enable_counter;
+reg [15:0] gear_shift_counter;
+reg [15:0] enable_counter;
 
 reg [3:0] divvcop_reg;
 reg [3:0] divvcor_reg;
@@ -98,14 +98,33 @@ always @(posedge ref_clk or negedge resetn) begin
     end
 end
 
+always @(posedge ref_clk or negedge resetn) begin
+    if(~resetn) begin 
+        gear_shift_counter  = 16'h0000;
+        enable_counter      = 16'h0000;
+    end else begin 
+        if((gear_shift_reg == 1'b1)) begin
+            gear_shift_counter = gear_shift_counter+1;
+            if (gear_shift_counter>16'h3E88) begin
+                gear_shift_counter = 16'h0000;
+            end
+        end else begin
+            if((enp_reg==1'b0)||(enr_reg==1'b0)) begin
+                enable_counter = enable_counter+1;
+                if(enable_counter>16'h2718) begin
+                    enable_counter = 16'h0000;
+                end
+            end
+        end
+    end    
+end
+
 always @(*) begin
     if(~resetn) begin
         bypass_reg          = 1'b0;
         enp_reg             = 1'b0; 
         enr_reg             = 1'b0;
         gear_shift_reg      = 1'b1;
-        gear_shift_counter  = 16'h0000;
-        enable_counter      = 16'h0000;
         pll_lock_reg        = 1'b0;
 
         // Default startup of PLL
@@ -125,18 +144,14 @@ always @(*) begin
         PLL_test_rd_en      = 1'b0;
     end else begin
         if((gear_shift_reg == 1'b1)) begin
-            gear_shift_counter = gear_shift_counter+1;
-            if (gear_shift_counter>12'h200) begin
+            if (gear_shift_counter>16'h3E80) begin
                 gear_shift_reg = 1'b0;
-                gear_shift_counter = 12'h000;
             end
         end else begin
             if((enp_reg==1'b0)||(enr_reg==1'b0)) begin
-                enable_counter = enable_counter+1;
-                if(enable_counter>12'h200) begin
+                if(enable_counter>16'h2710) begin
                     enp_reg = 1'b1;
                     enr_reg = 1'b1;
-                    enable_counter = 12'h000;
                 end
             end
         end
@@ -180,16 +195,10 @@ always @(*) begin
                     end
                 end
                 10'h001: begin
-                    if(PSTRB[0]==1'b1)
-                        gear_shift_counter[7:0] =  PWDATA[7:0];
-                    if(PSTRB[1]==1'b1)
-                        gear_shift_counter[11:8] = PWDATA[11:8];
+                    PSLVERR_reg = 1'b1; 
                 end
                 10'h002: begin
-                    if(PSTRB[0]==1'b1)
-                        enable_counter[7:0] =  PWDATA[7:0];
-                    if(PSTRB[1]==1'b1)
-                        enable_counter[11:8] = PWDATA[11:8];
+                    PSLVERR_reg = 1'b1; 
                 end
                 10'h003: begin
                     if(PSTRB[0]==1'b1)